XRT7298
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APPLICA TIONS
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GENERAL DESCRIPTION
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ORDERING INFORMATION
Part No.
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XRT7298
BLOCK DIAGRAM
Figure 1. XRT7298 Block Diagram
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XRT7298
PIN CONFIGURATION
5&/.
5/223
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7$26
9
51'$7$
53'$7$
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28 Lead PDIP (0.600”)
28 Lead SOJ (Jedec,0.300”)
PIN DESCRIPTION
Pin #
Symbol
5&/.
5/223
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T ype
,
,
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Description
'6676
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7$26
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73'$7$
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DS3, STS-1 or E3 Select Pin
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5 V Digital Supply
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T ransmit Positive Data
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T ransmit NegativeData.
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T ransmit Clock
IRU 73'$7$ DQG 71'$7$
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Encoder Disable.
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Receive Clock Input.
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PIN DESCRIPTION (CONT’D)
Pin #
Symbol
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2
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Receive NegativeData.
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Receive Positive Data
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Receive Clock Output
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Driver Monitor Output.
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Monitor Ring Input
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Monitor T ip Input
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T ransmit Ring Output
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T ransmit T ip Output.
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Receive Positive Data
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Receive NegativeData
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Bipolar Violation Output
Description
Note:
1
If a bipolarviolationoccurs,RPOS andRNEG cancorrespond thedecoded
to
versions of RNDAT A andRPDAT A respectively If
.
DECODIS is high,RPOS andRNEG alwaystrackRPDAT A andRNDAT A respectively
.
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XRT7298
ELECTRICAL CHARACTERISTICS
(See Figure 8 )
T est Conditions: V
DD
= 5V
±
5%, T
A
= -40
G
C to +85
G
C, unless otherwise specified. All timing characteristics
are measuredwith 10pF loading.
Symbol
Parameter
Min.
T yp.
Max.
Units
AC Electrical Characteristics
W5
W)
W768
W7+2
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DC Electrical Characteristics
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Notes:
1
Whentheencoders enabled, handlingdelayof six TCLK clockcyclesfor B3ZS andseven clockcyclesfor HDB3
i
a
alwaysexists between
TPDA T A/TNDAT A andTTIP/TRING. The handlingdelayis reduced
tothreeanda halfcycleswhentheen
coderis disabled.
2
Whenthedecoders enabled, handlingdelayof six anda halfRCLK clockcycleswill alwaysexist between
i
a
RPDAT A/RNDA A
T
andRPOS/RNEG. The handlingdelayis reduced oneandhalfRCLK clockcycleswhenthedecoders disabled.
to
i
3
Supply currentis measuredwithtransmittersendingall ones AMI signal andwithT ransmit Level (TXLEV) set to high.
4
All inputs exceptpin 19, 20 andpin 26.
Specifications are subject to changewithout notice
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