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PHR2010C2842BGTB

器件型号:PHR2010C2842BGTB
器件类别:无源元件    电阻器   
文件大小:113KB,共6页
厂商名称:Vishay(威世)
厂商官网:http://www.vishay.com
标准:
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器件描述

Fixed Resistor, Thin Film, 0.5W, 28400ohm, 150V, 0.1% +/-Tol, 5ppm/Cel, Surface Mount, 2010, CHIP

参数
参数名称属性值
是否Rohs认证符合
Objectid145068564437
包装说明CHIP
Reach Compliance Codeunknown
ECCN代码EAR99
其他特性HIGH PRECISION
构造Rectangular
JESD-609代码e4
安装特点SURFACE MOUNT
端子数量2
最高工作温度155 °C
最低工作温度-65 °C
封装高度1.02 mm
封装长度5.72 mm
封装形式SMT
封装宽度2.8 mm
包装方法TR, Plastic
额定功率耗散 (P)0.5 W
额定温度70 °C
参考标准ESCC4001/023
电阻28400 Ω
电阻器类型FIXED RESISTOR
尺寸代码2010
表面贴装YES
技术THIN FILM
温度系数5 ppm/°C
端子面层Gold (Au)
端子形状WRAPAROUND
容差0.1%
工作电压150 V

文档预览

PHR
www.vishay.com
Vishay Sfernice
ESCC (
) 4001/023 Qualified High Precision (5 ppm, 0.01 %),
Thin Film Chip Resistors
FEATURES
• Load life stability at ± 70 °C for 2000 h:
0.15 % under Pn
• Low temperature coefficient down to ± 5 ppm/°C
• Very low noise (< -35 dB) and voltage coefficient
(< 0.01 ppm/V)
DESIGN SUPPORT TOOLS
Models
Available
click logo to get started
• Resistance range: 10
to 3 M (depending on size)
• Laser trimmed tolerances to ± 0.01 %
• TCR in lot tracking
5 ppm/°C
• Termination: Thin film technology
• SnPb terminations over nickel barrier
• ESCC 4001 (generic specifications)
• ESCC 4001/023 (detailed specifications)
• ESCC qualified
• SMD wraparound chip resistor
• Operating temperature range: -65 °C to +155 °C
• From 0402 to 2010
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
Vishay Sfernice Thin Film division holds ESCC QML
qualification (ESCC technology flow qualification).
These High-Rel. components are ideal for low noise and
precision applications, superior stability, low temperature
coefficient of resistance, and low voltage coefficient, Vishay
Sfernice’s precision thin film wraparound resistors exceed
requirements of MIL-PRF-55342G characteristics Y
(± 10 ppm/°C).
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
ESCC
SIZE VARIANT
NUMBER
0402 13 and 14
0603 01 and 05
0805 02 and 06
1206 03 and 07
2010 04 and 08
RATED
POWER
RESISTANCE
AT + 70 °C
RANGE
(Pn)
W
(1)
10 to 150K
10 to 500K
10 to 750K
10 to 3.5M
10 to 6M
0.05
0.1
0.125
0.25
0.50
LIMITING
ELEMENT
VOLTAGE
(UL)
V
(1)
30
35
75
100
150
INSULATION
VOLTAGE
(U
i
)
V
50
100
200
300
300
TOLERANCE
±%
0.01, 0.02, 0.05, 0.1
0.01, 0.02, 0.05, 0.1
0.01, 0.02, 0.05, 0.1
0.01, 0.02, 0.05, 0.1
0.01, 0.02, 0.05, 0.1
TEMPERATURE
COEFFICIENT
± ppm/°C
5, 10, 25
5, 10, 25
5, 10, 25
5, 10, 25
5, 10, 25
PHR 0402
PHR 0603
PHR 0805
PHR 1206
PHR 2010
Note
(1)
Limiting voltages and power rating are already derated (for maximum ratings admissible, refer to P chip:
www.vishay.com/cod?53017)
CLIMATIC SPECIFICATIONS
Operating temperature
range
Soldering temperature
(T
sol
)
-65 °C; +155 °C
260 °C, immersion 10 s
MECHANICAL SPECIFICATIONS
Substrate material
Technology
Film
Protection
Terminations
Alumina
Thin film
Nickel chromium
with mineral
passivation
Epoxy and silicone
B type:
SnPb over nickel barrier
for solder reflow
(1)
G type:
gold over nickel barrier
Note
(1)
For B terminations use recommended reflow profile #1 as per
Application Note “Guidelines for Vishay Sfernice Resistive and
Inductive Components” (document number: 52029)
Revision: 03-Jan-2019
Document Number: 53037
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHR
www.vishay.com
Vishay Sfernice
DIMENSIONS
in millimeters
A
D
D
C
B
E
E
VARIANT
NUMBER
01, 05
02, 06
03, 07
04, 08
13, 14
STYLE
0603
0805
1206
2010
0402
MIN.
1.39
1.78
2.87
4.95
0.87
A
MAX.
2.16
2.55
3.64
5.72
1.64
MIN.
0.62
1.14
1.47
2.41
0.47
B
MAX.
1.01
1.53
1.86
2.8
0.86
DIMENSIONS
C
MIN.
MAX.
0.25
1.02
0.25
1.02
0.25
1.02
0.25
1.02
0.25
1.02
D
MIN.
0.17
0.17
0.17
0.35
0.09
MAX.
0.51
0.51
0.51
0.85
0.38
MIN.
0.25
0.25
0.25
0.35
0.12
E
MAX.
0.51
0.51
0.51
0.85
0.38
TRACEABILITY DEFINITIONS
The two major traceability elements are defined as:
• The primary process lot number named Front End lot (FE lot). One “FE lot” is composed of several wafers issued from the
same thin film deposition sequence.
• The date code named Batch Number (BN). The “BN” is defined after completion of the end of production testing sequence.
The lot homogeneity is given by the “FE lot” and not by the “BN”.
According to the applied rules validated by the ESCC through the product qualification, the following situations are agreed:
• Parts coming from different “FE lost” might have the same “BN”.
• A maximum of two different “BN” might be applied to the same “FE lot” to enable the use of overruns from a previous PO.
• Unless requested / approved by the customer the “BN” will be 2 years old maximum.
SPECIFIC TRACEABILITY REQUIREMENTS
The following specific requirements have to be treated as:
• A customer who requires “Lot Homogeneity” has to mention it on the PO as “SINGLE PRODUCTION LOT”.
• A customer who requires “Lot Homogeneity” in addition to a “Single Batch Number” has to mention it on the PO as “SINGLE
PRODUCTION LOT AND OPTION R0101”.
END OF PRODUCTION TESTING
Mandatory testing performed at the end of the production process:
• 100 % overload: Voltage
6.25 Pn x Rn
or 2 UL whichever is less - duration 2 s
• 100 % burn in: 168 h at Pn at 70 °C
OPTIONS
LOT VALIDATION TESTING
For procurement of qualified components, lot validation testing is not required and shall only be performed if specifically
stipulated in the purchase order.
For procurement of unqualified components, lot validation testing shall be performed as stipulated in the purchase order. The
need for lot validation testing shall be determined by the orderer.
When lot validation testing is required, it shall consist of the performance of one or more of the tests or subgroup test sequences
of chart F4 indicated in the ESA Generic Specification ESCC 4001. The testing to be performed and the sample size shall be as
stipulated in the purchase order. When procurement of more than one component type is involved from a family, range or series,
the selection of representative samples shall also be stipulated in the purchase order.
Lot validation testing will be composed of one LVT charges and LVT samples:
• Lot validation test charges has to be ordered separately on purchase order.
• Lot validation samples have to be ordered separately on purchase orderer.
FINAL INSPECTION
If requested by the orderer a final inspection can be performed on site.
Final inspection has to be stipulated separately on purchase order.
Revision: 03-Jan-2019
Document Number: 53037
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHR
www.vishay.com
Vishay Sfernice
LAND PATTERN
in millimeters
G
min.
Z
max.
CHIP SIZE
0402
0603
0805
1206
2010
Z
max.
1.55
2.37
2.76
3.91
5.93
G
min.
0.15
0.35
0.74
1.85
3.71
X
m
ax
.
X
max.
0.73
0.98
1.40
1.73
2.67
Note
• Suggested land pattern: According to IPC-7351A
QUALIFIED OHMIC RANGE
MODEL
ESCC
VARIANT
OHMIC
RANGE
()
10 to < 50
01 to 08
and
13 to 14
50 to < 100
100 to < 250
250
(1)
QUALIFIED OHMIC RANGE
TOLERANCE
(%)
0.1
0.05 and 0.1
PHR
0.02, 0.05 and 0.1
01 to 08
and
13 to 14
MODEL
ESCC
VARIANT
OHMIC
RANGE
()
(1)
TEMPERATURE
COEFFICIENT
(ppm/°C)
ESCC
CODE
2
2
1
0
2
1
0
9
10 to < 20 E: 25 (-55 °C; +155 °C)
E : 25 (-55 °C ; +155 °C)
20 to < 50 Y : 10 (-55 °C ; +155 °C)
Z : 5 (+22 °C ; +70 °C)
50
E : 25 (-55 °C ; +155 °C)
Y : 10 (-55 °C ; +155 °C)
Z : 5 (+22 °C ; +70 °C)
C : 5 (-55 °C ; +155 °C)
PHR
0.01, 0.02, 0.05 and 0.1
(1)
QUALIFIED OHMIC RANGE: MAX. VALUE
PHR 0402
PHR 0603
100 k (67 k for TCR C) 200 k (160 k for TCR C)
PHR 0805
250 k
PHR 1206
1 M
PHR 2010
3 M
Note
(1)
For values, TCR, tolerance outside of qualified range: Please consult
POPULAR OPTIONS
OPTION 0041
Production according to ESCC 4001/023 for: Cases, ohmic
values, tolerance or TCR outside of qualified range.
Please consult Vishay Sfernice for feasibility.
EXTENDED FEATURES
You may consult Vishay Sfernice for chip sizes, ohmic
values and tolerances outside of the qualified range.
POWER DERATING CURVE
RATED POWER (W)
0.500
2010
PACKAGING
Two types of packaging are available: Waffle-pack and tape
and reel.
NUMBER OF PIECES PER PACKAGE
SIZE
WAFFLE
PACK
2" × 2"
100
50
140
60
TAPE AND REEL
(2)
MIN.
MAX.
5000
4000
1000
8 mm
TAPE
WIDTH
0.250
1206
0402
0603
0805
1206
2010
0.125
0.100
0.050
0
0
0805
0603
0402
70
155
AMBIENT TEMPERATURE (°C)
Note
(2)
MoQ: 50 pieces
Revision: 03-Jan-2019
Document Number: 53037
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHR
www.vishay.com
Vishay Sfernice
REQUIREMENTS
ESA/SCC 4001/023
± 0.05 % + (0.05
x 100/Rn)
± 0.05 % + (0.05
x 100/Rn)
± 0.05 % + (0.05
x 100/Rn)
MIL-PRF-55342G
0.10 %
0.1 %
(for 100 cycles)
-
PERFORMANCE
TEST
Short time overload
Rapid temperature
change
Soldering
(thermal shock)
Terminal strength:
adhesion bend strength
of end plated facing
Climatic sequence
Load life
High temperature exposure
CONDITIONS
U
=
6.25 Pn x Rn
U
max.
< 2 UL - 2 s
-55 °C / +155 °C 5 cycles
CEI 66-2-14 Test Na
260 °C / 10 s
CEI 68-2-20 A Test T6
(met. 1A)
CEI 115-1 Clause 4.32
CEI 115-1 Clause 4.33
CEI 67-2-1 / CEI 68-2-2
CEI 67-2-13 / CEI 68-2-30
2000 h Pn at +70 °C
90’ / 30’ cycle
2000 h Pn at +155 °C
CEI 68-2-20A Test B
TYPICAL
± 0.01 %
± 0.01 %
± 0.015 % (for 500 cycles)
± 0.005 %
± 0.05 % + (0.05
x 100/Rn)
± 0.10 % + (0.05
x 100/Rn)
± 0.15 % + (0.05
x 100/Rn)
± 0.15 % + (0.05
x 100/Rn)
-
-
0.5 %
± 0.10 %
(duration 1000 h)
± 0.01 %
± 0.02 %
Insulation resistance > 1 G
± 0.02 %
Insulation resistance > 1 G
± 0.05 %
Insulation resistance > 1 G
ESCC/PHR CODIFICATION CORRESPONDENCE TABLES
VARIANT
13
01
02
03
04
14
05
06
07
08
PHR
MODEL
CASE SIZE
0402
0603
0805
1206
2010
0402
0603
0805
1206
2010
G (gold)
B (tin/lead)
TERMINATION
ESCC/PHR CODIFICATION CORRESPONDENCE TABLES
TEMPERATURE COEFFICIENT
5 ppm/°C (+22 °C; +70 °C)
10 ppm/°C (-55 °C; +155 °C)
25 ppm/°C (-55 °C; +155 °C)
5 ppm/°C (-55 °C; +155 °C)
ESCC CODE
0
1
2
9
PHR CODE
Z
Y
E
C
ESCC/PHR CODIFICATION CORRESPONDENCE TABLES
TOLERANCE
0.1 %
0.05 %
0.02 %
0.01 %
ESCC CODE
B
W
P
L
PHR CODE
B
W
P
L
Revision: 03-Jan-2019
Document Number: 53037
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
PHR
www.vishay.com
Vishay Sfernice
GLOBAL PART NUMBER INFORMATION
LIMITED TO 18 DIGITS: If more digits are necessary a codification of some digits might be necessary
P
TYPE
PHR0402
PHR0603
PHR0805
PHR1206
PHR2010
H
R
0
TCR
6
0
3
Y
1
0
0
3
B
B
T
1
PACKAGING
For more
information
see
Codification
of Packaging
table
4
OPTION
Leave
blank
if no
option
Y
= ± 10 ppm/°C
E
= ± 25 ppm/°C
Z
= 5 ppm/°C
(+22 °C; +70 °C)
C
= 5 ppm/°C
(-55 °C; +155 °C)
OHMIC
VALUE
The first three digits are
significant figures and the
last digit specifies the
number of zero to follow. R
designates decimal point.
Example:
10R0
= 10
3901
= 3900
1004
= 1 M
TOLERANCE
L
= ± 0.01 %
P
= ± 0.02 %
W
= ± 0.05 %
B
= ± 0.10 %
TERMINATION
B:
SnPb over
nickel barrier
G:
gold
Note
Terminations B:
Variants 01 / 02 / 03 / 04 and 13
Terminations G:
Variants 05 / 06 / 07 / 08 and 14
GLOBAL PART NUMBER INFORMATION
ESCC Code
4
ESCC SPEC
4001023
0
0
1
VARIANT
0
2
3
0
1
1
0
0
3
B
1
TCR
13
or
14
= 0402
01
or
05
= 0603
02
or
06
= 0805
03
or
07
= 1206
04
or
08
= 2010
OHMIC
VALUE
The first three digits are
significant figures and the
last digit specifies the
number of zero to follow. R
designates decimal point.
Example:
10R0
= 10
3901
= 3900
1004
= 1 M
TOLERANCE
L
= ± 0.01 %
P
= ± 0.02 %
W
= ± 0.05 %
B
= ± 0.10 %
1
= ± 10 ppm/°C
0
= ± 5 ppm/°C
(+22 °C; +70 °C)
2
= ± 25 ppm/°C
9
= ± 5 ppm/°C
(-55 °C; +155 °C)
CODIFICATION PACKAGING
- Waffle Pack
CODE 18
W
WA
PACKAGING
25 min. (100 min. for size 0402), 1 mult
100 min., 100 mult
(1)
CODIFICATION PACKAGING
- Paper Tape
(2)
CODE 18
PT
PA
PB
PC
PD
(3)
PE
(3)
PACKAGING
100 min., 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape
CODIFICATION PACKAGING
- Plastic Tape
(2)
CODE 18
T
TA
TB
TC
TD
TE
TF
PACKAGING
50 min. (100 min. for size 0402), 1 mult
100 min., 100 mult
250 min., 250 mult
500 min., 500 mult
1000 min., 1000 mult
2500 min., 2500 mult
Full tape
(3)
(1)
PF
(3)(4)
Notes
Available only in size 1206
(2)
Plastic tape in standard for all sizes. Paper tape in option for
0402, 0603, 0805 and 1206. Please consult Vishay Sfernice for
2010 size
(3)
Not available for size 0402
(4)
Qantity depending on size of chips
Revision: 03-Jan-2019
Document Number: 53037
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000

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