notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM
is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. A, 01/29/2019
1
IS49NLS96400,IS49NLS18320
1 Package Ballout and Description
1.1 576Mb (64Mx9) Separate I/O BGA Ball-out (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VREF
VDD
VTT
A22
1
A21
A5
A8
BA2
NF
2
2
VSS
DNU
3
DNU
3
DNU
3
DNU
DNU
A6
A9
NF
2
3
3
3
VEXT
DNU
3
DNU
3
DNU
3
DNU
DNU
A7
VSS
VDD
VDD
VSS
A17
DNU
DNU
3
3
3
3
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
Q0
Q1
QK0#
Q2
Q3
A2
VSS
VDD
VDD
VSS
A12
Q4
Q5
Q6
Q7
Q8
VEXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D4
D5
D6
D7
D8
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
DK#
CS#
A16
DNU
DNU
3
3
DNU
3
DNU
3
DNU
3
ZQ
DNU
3
DNU
3
DNU
3
VEXT
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
9
9
2
2
2
1
3
1
1
22
4
144
Notes:
NOTES:
1. Reserved for
for future
This may optionally be
1) Reserved
future use.
use. This may
connected to GND.
optionally be
This signal is internally connected and
connected to GND.
2. No function.
2) Reserved for future
of a clock input signal.
has parasitic characteristics
use. This signal is
internally connected and has parasitic
This may optionally be connected to GND.
3. Do not use. This signal
address input signal.
characteristics of an
is internally connected and
has parasitic
optionally be connected to
This may
characteristics of a I/O. This may
optionally be connected to GND. Note that if ODT is
GND.
enabled, these pins are High-Z.
3) No function. This signal is internally
connected and has parasitic
characteristics of a clock input signal.
This may optionally be connected to
GND.
4) Do not use. This signal is internally
connected and has parasitic
characteristics of a I/O. This may
optionally be connected to GND. Note
that if ODT is enabled, these pins will be
connected to VTT.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. A, 01/29/2019
2
IS49NLS96400,IS49NLS18320
1.2 576Mb (32Mx18) Separate I/O BGA Ball-out (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
1
VREF
VDD
VTT
A22
1
A21
2
A5
A8
BA2
NF
3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
2
VSS
D4
D5
D6
D7
D8
A6
A9
NF
3
DK#
CS#
A16
D14
D15
QK1
D16
D17
ZQ
3
VEXT
Q4
Q5
Q6
Q7
Q8
A7
VSS
VDD
VDD
VSS
A17
Q14
Q15
QK1#
Q16
Q17
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5
6
7
8
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
Q0
Q1
QK0#
Q2
Q3
A2
VSS
VDD
VDD
VSS
A12
Q9
Q10
Q11
Q12
Q13
VEXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
18
18
2
4
2
1
3
1
1
2
4
144
Notes:
NOTES:
1. Reserved for future use. This may optionally be
1) Reserved for future use. This may
connected to GND.
optionally be connected to GND.
2. Reserved for future use. This signal is internally
2) Reserved for future use. This signal is
connected and has parasitic characteristics of an address
internally connected and
be connected to
input signal. This may optionally
has parasitic
GND.
3. No function. This
of an
is internally connected and
characteristics
signal
address input signal.
has parasitic
optionally be connected to GND.
This may
characteristics of a clock input signal. This
may optionally be connected to GND.
internally
3) No function. This signal is
connected and has parasitic characteristics
of a clock input signal. This may optionally
be connected to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. A, 01/29/2019
3
IS49NLS96400,IS49NLS18320
1.3 Ball Descriptions
Symbol
A*
BA*
CK, CK#
CS#
D*
Type
Input
Input
Input
Input
Input
Description
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE
REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK.
Bank address inputs: Selects to which internal bank a command is being applied to.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising
edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the command
decoder is disabled, new commands are ignored, but internal operations continue.
Data input: The D signals form the input data bus. During WRITE commands, the data is sampled at both
edges of DK.
Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to both
edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For both the x9 and x18 devices, all D
signals are referenced to DK and DK#. DK and DK# pins must always be supplied to the device.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM is
sampled HIGH. DM is sampled on both edges of DK. Tie signal to ground if not used.
IEEE 1149.1 clock input: This ball must be tied to V
SS
if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
Input reference voltage: Nominally V
DDQ
/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus
impedance. Q output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
Data input: The Q signals form the output data bus. During READ commands, the data is referenced to both
edges of QK*.
Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x18 device, QK0 and QK0# are aligned with Q0-Q8, while QK1 and QK1# are aligned
with Q9-Q17. For the x9 device, all Q signals are aligned with QK0 and QK0#.
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not used.
Power supply: Nominally, 1.8V.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
Power supply: Nominally, 2.5V.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, V
DDQ
/2.
Reserved for future use: This signal is not connected and can be connected to ground.
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
No function: These balls can be connected to ground.
4
DK, DK#
Input
DM
TCK
TMS,TDI
WE#,
REF#
V
REF
ZQ
Input
Input
Input
Input
Input
I/O
Q*
Output
QK*,
QK*#
QVLD
TDO
V
DD
V
DDQ
V
EXT
V
SS
V
SSQ
V
TT
A22
DNU
NF
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
-
-
-
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. A, 01/29/2019
IS49NLS96400,IS49NLS18320
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Item
I/O Voltage
Voltage on V
EXT
supply relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Min
0.3
0.3
0.3
0.3
Max
V
DDQ
+ 0.3
2.8
2.1
2.1
Units
V
V
V
V
Note: Stress greater than those listed in this table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.2 DC Electrical Characteristics and Operating Conditions
Description
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Termination voltage
Input high voltage
Input low voltage
Output high current
Output low current
Clock input leakage current
Input leakage current
Output leakage current
Reference voltage current
V
OH
= V
DDQ
/2
V
OL
= V
DDQ
/2
0V ≤ V
IN
≤ V
DD
0V ≤ V
IN
≤ V
DD
0V ≤ V
IN
≤ V
DDQ
Conditions
Symbol
V
EXT
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
I
OH
I
OL
I
LC
I
LI
I
LO
I
REF
Min
2.38
1.7
1.4
0.49 x V
DDQ
0.95 x V
REF
V
REF
+ 0.1
V
SSQ
0.3
(V
DDQ
/2)/
(1.15 x RQ/5)
(V
DDQ
/2)/
(1.15 x RQ/5)
5
5
5
5
Max
2.63
1.9
V
DD
0.51 x V
DDQ
1.05 x V
REF
V
DDQ
+ 0.3
V
REF
0.1
(V
DDQ
/2)/
(0.85 x RQ/5)
(V
DDQ
/2)/
(0.85 x RQ/5)
5
5
5
5
Units
V
V
V
V
V
V
V
A
A
µA
µA
µA
µA
Notes
2
2,3
4,5,6
7,8
2
2
9, 10,
11
9, 10,
11
Notes:
1. All voltages referenced to V
SS
(GND).
2. Overshoot: V
IH
(AC) ≤ V
DD
+ 0.7V for t ≤ t
CK
/2. Undershoot: V
IL
(AC) ≥ –0.5V for t ≤ t
CK
/2. During normal operation, V
DDQ
must not exceed V
DD
. Control input signals
may not have pulse widths less than t
CK
/2 or operate at frequencies exceeding t
CK
(MAX).
3. V
DDQ
can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of V
REF
is expected to be 0.5 x V
DDQ
of the transmitting device. V
REF
is expected to track variations in V
DDQ
.
5. Peak-to-peak AC noise on V
REF
must not exceed ±2 percent V
REF
(DC).
6. V
REF
is expected to equal V
DDQ
/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V
REF
may not exceed ±2 percent of the DC value. Thus, from V
DDQ
/2, V
REF
is allowed ±2 percent V
DDQ
/2 for DC error and an additional ±2 percent V
DDQ
/2 for AC noise.
This measurement is to be taken at the nearest V
REF
bypass capacitor.
7. V
TT
is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
8. On-die termination may be selected using mode register A9 (for non-multiplexed address mode) or Ax9 (for multiplexed address mode). A resistance R
TT
from
each data input signal to the nearest V
TT
can be enabled. R
TT
= 125–185Ω at 95°C T
C
.
9. I
OH
and I
OL
are defined as absolute values and are measured at V
DDQ
/2. I
OH
flows from the device, I
OL
flows into the device.
10. If MRS bit A8 or Ax8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
2.3 Capacitance
(T
A
= 25 °C, f = 1MHz)
Parameter
Address / Control Input capacitance
I/O, Output, Other capacitance (D, Q, DM, QK, QVLD)
Clock Input capacitance
JTAG pins
Symbol
C
IN
C
IO
C
CLK
C
J
Test Conditions
V
IN
=0V
V
IO
=0V
V
CLK
=0V
V
J
=0V
Min
1.5
3.5
2
2
Max
2.5
5
3
5
Units
pF
pF
pF
pF
Note. These parameters are not 100% tested and capacitance is not tested on ZQ pin.
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