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TRU050-TACHA-12M6240000

器件型号:TRU050-TACHA-12M6240000
器件类别:模拟混合信号IC    信号电路   
厂商名称:Microsemi
厂商官网:https://www.microsemi.com
标准:
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器件描述

Phase Locked Loop, CDIP16, SMD-16

参数
参数名称属性值
是否Rohs认证符合
厂商名称Microsemi
包装说明SMD-16
Reach Compliance Codecompli
模拟集成电路 - 其他类型PHASE LOCKED LOOP
JESD-30 代码R-CDIP-T16
JESD-609代码e4
长度20.32 mm
湿度敏感等级1
功能数量1
端子数量16
最高工作温度70 °C
最低工作温度
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)260
认证状态Not Qualified
座面最大高度4.69 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
温度等级COMMERCIAL
端子面层Gold (Au) - with Nickel (Ni) barrie
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
宽度7.62 mm

文档预览

TRU050
Complete VCXO based Phase-Locked Loop
Features
Output Frequencies to 65.536 MHz
5.0 V or 3.3Vdc Operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS Outputs
0/70° or –40/85° Temperature Range
C
Ceramic SMD Package
RoHS/Lead Free Compliant Versions
The TRU050, VCXO based PLL
Description
The VI TRU050 is a user-configurable crystal-based
PLL integrated circuit. It includes a digital phase
detector, op-amp, VCXO and additional integrated
functions for use in digital synchronization
applications. Loop filter software is available as well
SPICE models for circuit simulation.
Applications
Frequency Translation
Clock Smoothing
NRZ Clock Recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low Jitter PLL’s
Figure 1. TRU050 Block Diagram
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 1 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
TRU050, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Output Frequency (ordering
option)
Out 1, 5V option
Out 1, 3.3V option
1
Supply Voltage
+5
+3.3
Supply Current
Output Logic Levels
2
Output Logic High
2
Output Logic Low
Output Transition Times
2
Rise Time
2
Fall Time
Input Logic Levels
2
Output Logic High
2
Output Logic Low
Loss of Signal Indication
2
Output Logic High
2
Output Logic Low
Nominal Frequency on Loss of Signal
Output 1
Output 2
3
Symmetry or Duty Cycle
Out 1
Out 2
RCLK
Absolute Pull Range,
ordering option
o
ver operating temp, aging, power supply
variations
Symbol
Min
1.000
1.000
Typical
Maximum
Units
65.636
51.840
5.0
3.3
5.5
3.6
65
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
V
DD
4.5
3.0
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.5
0.5
5
5
2.0
0.5
2.5
0.5
±75
±75
SYM1
SYM2
RCLK
APR
40/60
45/55
40/60
±50
±80
±100
0.5
0.3
Positive
0.53
0.35
0/70 or –40/85
%
%
%
ppm
Test Conditions for APR (+5V option)
Test Conditions for APR (+3.3V option)
Gain Transfer
Phase Detector Gain
+5V option
+3.3V Option
Operating temperature,
ordering option
Control Voltage Leakage Current
V
C
V
C
4.5
3.0
V
V
I
VCXO
±1
rad/V
rad/V
°C
uA
1. A good quality 0.01uF in parrallel with a 0.1 uf capacitor should be located as close to pin 16 to ground as possible.
2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which these parameters are
tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.
T
R
80
%
T
F
I
DD
16
650Ω
1.4V
20
%
V
DD
+
-
.
1µF
.01µF
I
C
V
C
1
+
-
3
On Time
Period
15pF
1.8k
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RDATA and RCLK
Test Conditions (25±5°
C)
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 2 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
TRU050, VCXO Based PLL
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional
operation is not implied at these or any other conditions in excess of conditions represented in the operational
sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect
device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Storage Temperature
Soldering Temperature/Duration
Clock and Data Input Range
Symbol
V
DD
Tstorage
T
PEAK
/ t
P
CLKIN, DATAIN
Ratings
7
-55/125
260 / 40
Gnd-0.5 to V
DD
+0.5
Unit
Vdc
°C
°C/sec
V
Reliability
The TRU050 is capable of meeting the following qualification tests.
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014, 100% Tested
MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the the TRU050, proper precautions should be taken
when handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD
susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit
parameters used to define the model.
Table 4. ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
1500V
1000V
MIL-STD 3015
JESD 22-C101
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 3 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
TRU050, VCXO Based PLL
TRU050 Theory of Operation
Phase Detector
The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.
DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about a
50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN
and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by
more than a few hundred millivolts.
The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to produce
a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a block
diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does not
have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be centered
in the middle of the DATAIN signal, see figure 6.
The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3
volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ
signals, but 0.25 could be used as a starting point for data density.
The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant
ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications
such as 8kHz frequency translation, see figures 8 and 9.
Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so
under normal locked conditions and input frequencies >1MHz, PHO will be about V
DD
/2 and will not vary
signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary according
to the input frequency offset, but PHO will remain relatively constant.
Data In
(pin 7)
D
Clock In
(pin 9)
Q
1
30 kΩ
20 kΩ
D
Q
2
PHO
(pin 6)
Gain = 5 V / 2π
Gain = 2 / 3
Figure 4. Simplified Phase Detector Block Diagram
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 4 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
TRU050, VCXO Based PLL
V
DD
−π
V
d
V
DD
/2
0
Relative
Phase (θ
e
)
0V
Gain Slope = V
DD
/ 2π
Figure 5. Open Loop Phase Detector Transfer Curve
Recovered Clock and Data Alignment Outputs
The TRU050 is designed to recover an imbedded clock from an NRZ data signal and retime it with a data
pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and the
outputs are taken off Pin 11, RCLK, and Pin 12, RDATA. Under locked conditions, the falling edge of RCLK is
centered in the RDATA pattern. Also, there is a 1.5 clock cyle delay between DATAIN and RDATA. Figure 6
shows the relationship between the DATAIN, CLKIN, RDATA and RCLK.
Data In
Data1
Clock In
Recovered
Data
Data1
Recovered Clock
Figure 6. Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomidated by using a TRU050 at twice the
baud rate.
Loss of Signal, LOS and LOSIN
The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is
normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected
DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the TRU050’s
LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 1) is switched to an internal
voltage which centers OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS automatically closes the op
amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage equal to the +op
amp voltage (pin 4), usually VDD/2.
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 5 of 14
Tel: 1-88-VECTRON-1
Web:
www.vectron.com
Rev:
4/12/2016
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