NCP1611
Enhanced, High-Efficiency
Power Factor Controller
The NCP1611 is designed to drive PFC boost stages based on an
innovative
Current Controlled Frequency Fold−back
(CCFF)
method. In this mode, the circuit classically operates in
Critical
conduction
Mode
(CrM) when the inductor current exceeds a
programmable value. When the current is below this preset level, the
NCP1611 linearly decays the frequency down to about 20 kHz when
the current is null.
CCFF
maximizes the efficiency at both nominal
and light load. In particular, the stand−by losses are reduced to a
minimum.
Like in
FCCrM
controllers, internal circuitry allows near−unity
power factor even when the switching frequency is reduced. Housed in
a SO−8 package, the circuit also incorporates the features necessary
for robust and compact PFC stages, with few external components.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
CASE 751
SUFFIX D
1
NCP1611x = Specific Device Code
x = A or B
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
NCP1611x
ALYW
G
•
Near−Unity Power Factor
•
Critical Conduction Mode (CrM)
•
Current Controlled Frequency Fold−back (CCFF): Low Frequency
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Safety Features
Operation is Forced at Low Current Levels
PIN CONNECTIONS
On−time Modulation to Maintain a Proper Current Shaping in CCFF
1
V
control
Feedback
Mode
V
sense
V
CC
Skip Mode Near the Line Zero Crossing
FF
control
DRV
Fast Line / Load Transient Compensation (Dynamic Response
GND
CS/ZCD
Enhancer)
Valley Turn on
(Top View)
High Drive Capability: −500 mA / +800 mA
ORDERING INFORMATION
V
CC
Range: from 9.5 V to 35 V
See detailed ordering and shipping information in the package
dimensions section on page 28 of this data sheet.
Low Start−up Consumption
A Version: Low V
CC
Start−up Level (10.5 V), B Version: High V
CC
Start−up level (17.0 V)
Line Range Detection
Configurable for Low Harmonic Content across Wide
•
Low Duty−Cycle Operation if the Bypass Diode is
Line/Load Range
Shorted
EN61000−3−2 Class C Compliant across Wide Load
•
Open Ground Pin Fault Monitoring
Range for Dimmable Light Ballasts
•
Saturated Inductor Protection
This is a Pb−Free Device
•
Detailed Safety Testing Analysis (Refer to Application
Note AND9064/D)
Typical Applications
Non−latching, Over−Voltage Protection
Brown−Out Detection
Soft−Start for Smooth Start−up Operation (A version)
Over Current Limitation
Disable Protection if the Feedback Pin is Not
Connected
•
Thermal Shutdown
•
PC, TV, Adapters Power Supplies
•
LED Drivers and Light Ballasts (including dimmable
versions)
•
All Off−Line Applications Requiring Power Factor
Correction
©
Semiconductor Components Industries, LLC, 2015
1
January, 2015 − Rev. 4
Publication Order Number:
NCP1611/D
NCP1611
Vin
I
L
Vbulk
L1
.
.
D1
Dzcd
Vbulk
Ac line
R X1
R X2
Rbo1
1
2
3
8
7
6
5
Feedback
Rfb1
R zcd
Vcc
Q1
Rocp
EMI
Filter
Cin
Rbo2
Rfb2
4
Rz
Cz
Cp
LOAD
R FF
C bulk
R sense
Figure 1. Typical Application Schematic
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2
NCP1611
MAXIMUM RATINGS TABLE
Symbol
V
CC
V
CONTROL
V
sense
FFcontrol
CS/ZCD
DRV
FB
P
D
R
qJA
T
J
T
Jmax
T
Smax
T
Lmax
ESD
HBM
ESD
MM
Pin
7
1
2
3
4
6
8
Rating
Power Supply Input
V
CONTROL
pin (Note 1)
V
sense
pin (Note 5)
FFcontrol pin
Input Voltage
Current Injected to pin 4 (Note 4)
Driver Voltage (Note 1)
Driver Current
Feedback pin
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ T
A
= 70°C
Thermal Resistance Junction to Air
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
ESD Capability, HBM model (Note 2)
ESD Capability, Machine Model (Note 2)
Value
−0.3, + 35
−0.3, V
CONTROL
MAX (*)
−0.3, +10
−0.3, +10
−0.3, +35
+5
−0.3, V
DRV
(*)
−500, +800
−0.3, +10
550
145
−40 to +125
150
−65 to 150
300
> 2000
> 200
Unit
V
V
V
V
V
mA
V
mA
V
mW
°C/W
°C
°C
°C
°C
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. “V
CONTROL
MAX” is the pin1 clamp voltage and “V
DRV
” is the DRV clamp voltage (V
DRVhigh
). If V
CC
is below V
DRVhigh
, “V
DRV
” is V
CC
.
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
4. Maximum CS/ZCD current that can be injected into pin4
NCP1611
VCC
ESD diode
R1
Ipin4
CS/ZCD
2k
CS/ZCD
circuitry
7.4V
Maintain Ipin4
below 5 mA
ESD diode
GND
5. Recommended maximum V
sense
voltage for optimal operation is 4.5 V.
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3
NCP1611
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: V
CC
= 15 V, T
J
from −40°C to +125°C, unless otherwise specified)
Symbol
START−UP AND SUPPLY CIRCUIT
V
CC(on)
Start−Up Threshold,
V
CC
increasing:
A version
B version
Minimum Operating Voltage, V
CC
falling
Hysteresis (V
CC
(on )
−
V
CC
(off )
)
A version
B version
Start−Up Current,
V
CC
= 9.4 V
Operating Consumption, no switching (V
sense
pin being grounded)
Operating Consumption, 50 kHz switching, no load on DRV pin
V
9.75
15.80
8.50
0.75
6.00
−
−
−
10.50
17.00
9.00
1.50
8.00
20
0.5
2.0
11.25
18.20
9.50
−
−
50
1.0
3.0
mA
mA
mA
V
V
Rating
Min
Typ
Max
Unit
V
CC(off)
V
CC(HYST)
I
CC(start)
I
CC(op)1
I
CC(op)2
CURRENT CONTROLLED FREQUENCY FOLD−BACK
T
DT1
T
DT2
T
DT3
I
DT1
I
DT2
V
SKIP−H
V
SKIP−L
V
SKIP−HYST
GATE DRIVE
T
R
T
F
R
OH
R
OL
I
SOURCE
I
SINK
V
DRVlow
V
DRVhigh
REGULATION BLOCK
V
REF
Feedback Voltage Reference:
from 0°C to 125°C
Over the temperature range
Error Amplifier Current Capability
Error Amplifier Gain
V
control
Pin Voltage
− @
V
FB
= 2 V
− @
V
FB
= 3 V
Ratio (V
OUT
Low Detect Threshold /
V
REF
) (guaranteed by design)
Ratio (V
OUT
Low Detect Hysteresis /
V
REF
) (guaranteed by design)
V
control
Pin Source Current when (V
OUT
Low Detect) is activated
V
2.44
2.42
−
110
−
−
95.0
−
180
2.50
2.50
±20
220
4.5
0.5
95.5
−
220
2.54
2.54
−
290
−
−
96.0
0.5
250
%
%
mA
mA
mS
V
Output voltage rise−time @
C
L
= 1 nF, 10−90% of output signal
Output voltage fall−time @
C
L
= 1 nF, 10−90% of output signal
Source resistance
Sink resistance
Peak source current,
V
DRV
= 0 V (guaranteed by design)
Peak sink current,
V
DRV
= 12 V (guaranteed by design)
DRV pin level at
V
CC
close to
V
CC
(off )
with a 10 kW resistor to GND
DRV pin level at
V
CC
= 35 V (R
L
= 33 kW,
C
L
= 1 nF)
−
−
−
−
−
−
8.0
10
30
20
10
7.0
500
800
−
12
−
−
−
−
−
−
−
14
ns
ns
W
W
mA
mA
V
V
Dead−Time,
V
FFcontrol
= 2.60 V (Note 6)
Dead−Time,
V
FFcontrol
= 1.75 V
Dead−Time,
V
FFcontrol
= 1.00 V
FFcontrol pin current,
V
sense
= 1.4 V and
V
control
maximum
FFcontrol pin current,
V
sense
= 2.8 V and
V
control
maximum
FFcontrol pin Skip Level,
V
FFcontrol
rising
FFcontrol pin Skip Level,
V
FFcontrol
falling
FFcontrol pin Skip Hysteresis
−
14
32
180
110
−
0.55
50
−
18
38
200
135
0.75
0.65
−
0
22
44
220
160
0.85
−
−
ms
ms
ms
mA
mA
V
V
mV
I
EA
G
EA
V
CONTROL
−V
CONTROL
MAX
−V
CONTROL
MIN
V
OUT
L / V
REF
H
OUT
L / V
REF
I
BOOST
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
V
CS(th)
Current Sense Voltage Reference
450
500
550
mV
6. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (T
ZD
parameter of the
“Current Sense and Zero Current Detection Blocks” section).
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NCP1611
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: V
CC
= 15 V, T
J
from −40°C to +125°C, unless otherwise specified)
Symbol
Rating
Min
Typ
Max
Unit
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
T
LEB,OCP
T
LEB,OVS
T
OCP
V
ZCD(th)H
V
ZCD(th)L
V
ZCD(hyst)
R
ZCD/CS
V
CL(pos)
I
ZCD(bias)
I
ZCD(bias)
T
ZCD
T
SYNC
T
WDG
T
WDG(OS)
T
TMO
I
ZCD(gnd)
STATIC OVP
D
MIN
ON−TIME CONTROL
T
ON(LL)
T
ON(LL)2
T
ON(HL)
T
ON(LL)(MIN)
T
ON(HL)(MIN)
Maximum On Time,
V
sense
= 1.4 V and
V
control
maximum (CrM)
On Time,
V
sense
= 1.4 V and
V
control
= 2.5 V (CrM)
Maximum On Time,
V
sense
= 2.8 V and
V
control
maximum (CrM)
Minimum On Time,
V
sense
= 1.4 V (not tested, guaranteed by characterization)
Minimum On Time,
V
sense
= 2.8 V (not tested, guaranteed by characterization)
22
10.5
7.3
−
−
25
12.5
8.5
−
−
29
14.0
9.6
200
100
ms
ms
ms
ns
ns
Duty Cycle,
V
FB
= 3 V,
V
control
Pin Open
−
−
0
%
Over−Current Protection Leading Edge Blanking Time (guaranteed by design)
“Overstress” Leading Edge Blanking Time (guaranteed by design)
Over−Current Protection Delay from
V
CS/ZCD
>
V
CS(th)
to DRV low
(dV
CS/ZCD
/ dt = 10 V/ms)
Zero Current Detection,
V
CS/ZCD
rising
Zero Current Detection,
V
CS/ZCD
falling
Hysteresis of the Zero Current Detection Comparator
V
ZCD(th)H
over V
CS(th)
Ratio
CS/ZCD Positive Clamp @
I
CS/ZCD
= 5 mA
CS/ZCD Pin Bias Current,
V
CS/ZCD
= 0.75 V
CS/ZCD Pin Bias Current,
V
CS/ZCD
= 0.25 V
(V
CS/ZCD
<
V
ZCD
(th )L
) to (DRV high)
Minimum ZCD Pulse Width
Watch Dog Timer
Watch Dog Timer in “OverStress” Situation
Time−Out Timer
Source Current for CS/ZCD pin impedance Testing
100
50
−
675
200
375
1.4
−
0.5
0.5
−
−
80
400
20
−
200
100
40
750
250
500
1.5
15.6
−
−
60
110
200
800
30
250
350
170
200
825
300
−
1.6
−
2.0
2.0
200
200
320
1200
50
−
ns
ns
ns
mV
mV
mV
−
V
mA
mA
ns
ns
ms
ms
ms
mA
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP AND UVP)
R
softOVP
R
softOVP(HYST)
R
fastOVP2
R
UVP
R
UVP(HYST)
(I
B
)
FB
Ratio (Soft OVP Threshold,
V
FB
rising) over
V
REF
(V
softOVP
/V
REF
)
(guaranteed by design)
Ratio (Soft OVP Hysteresis) over
V
REF
(guaranteed by design)
Ratio (Fast OVP Threshold,
V
FB
rising) over
V
REF
(V
fastOVP
/V
REF
)
(guaranteed by design)
Ratio (UVP Threshold,
V
FB
rising) over
V
REF
(V
UVP
/V
REF
)
(guaranteed by design)
Ratio (UVP Hysteresis) over
V
REF
(guaranteed by design)
FB Pin Bias Current @
V
FB
=
V
OV
P
and
V
FB
=
V
UVP
104
1.5
106
8
−
50
105
2.0
107
12
−
200
106
2.5
108
16
1
450
%
%
%
%
%
nA
BROWN−OUT PROTECTION AND FEED−FORWARD
V
BOH
V
BOL
V
BO(HYST)
T
BO(blank)
I
CONTROL(BO)
Brown−Out Threshold,
V
sense
rising
Brown−Out Threshold,
V
sense
falling
Brown−Out Comparator Hysteresis
Brown−Out Blanking Time
V
control
Pin Sink Current,
V
sense
<
V
BOL
0.96
0.86
60
35
40
1.00
0.90
100
50
50
1.04
0.94
−
65
60
V
V
mV
ms
mA
6. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (T
ZD
parameter of the
“Current Sense and Zero Current Detection Blocks” section).
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