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530EB1301M00DG

器件型号:530EB1301M00DG
器件类别:无源元件    振荡器   
文件大小:215KB,共12页
厂商名称:Silicon Laboratories Inc
标准:  
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器件描述

LVPECL Output Clock Oscillator, 1301MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

参数
参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称Silicon Laboratories Inc
包装说明ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
其他特性TRAY
最长下降时间0.35 ns
频率调整-机械NO
频率稳定性20%
JESD-609代码e4
制造商序列号530
安装特点SURFACE MOUNT
标称工作频率1301 MHz
最高工作温度85 °C
最低工作温度-40 °C
振荡器类型LVPECL
物理尺寸7.0mm x 5.0mm x 1.85mm
最长上升时间0.35 ns
最大供电电压2.75 V
最小供电电压2.25 V
标称供电电压2.5 V
表面贴装YES
最大对称度55/45 %
端子面层Nickel/Gold (Ni/Au)

文档预览

S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Si530/531
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
V
IH
V
IL
Operating Temperature Range
T
A
Min
2.97
2.25
1.71
0.75 x V
DD
–40
Typ
3.3
2.5
1.8
111
99
90
81
60
Max
3.63
2.75
1.89
121
108
98
88
75
0.5
85
V
ºC
V
Units
mA
Notes:
1.
Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.
2.
OE pin includes a 17 kΩ pullup resistor to V
DD
.
Table 2. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2
Symbol
f
O
Test Condition
LVPECL/LVDS/CML
CMOS
Min
10
10
–7
–20
–50
Typ
±1.5
Max
945
160
+7
+20
+50
±3
±10
Units
MHz
ppm
Initial Accuracy
f
i
1,3
Measured at +25 °C at time of
shipping
Temperature Stability
ppm
ppm
ppm
Frequency drift over first year
Aging
f
a
Frequency drift over 15 year
life
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Selectable parameter specified by part number.
4.
Time from powerup or tristate mode to f
O
.
2
Rev. 1.1
Si530/531
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Test Condition
Temp stability = ±7 ppm
Total Stability
Temp stability = ±20 ppm
Temp stability = ±50 ppm
Powerup Time
4
t
OSC
Min
Typ
Max
±20
±31.5
±61.5
10
Units
ppm
ppm
ppm
ms
Notes:
1.
See Section 3. "Ordering Information" on page 7 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Selectable parameter specified by part number.
4.
Time from powerup or tristate mode to f
O
.
Table 3. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
CMOS Output Option
3
V
O
V
OD
V
OH
V
OL
mid-level
swing
(diff)
I
OH
= 32 mA
I
OL
= 32 mA
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
1
1.20
V
DD
V
V
PP
V
45
0.4
350
55
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
ps
ns
%
Symmetry (duty cycle)
SYM
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
Notes:
1.
50
to V
DD
– 2.0 V.
2.
R
term
= 100
(differential).
3.
C
L
= 15 pF
Rev. 1.1
3
Si530/531
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)*
for F
OUT
> 500 MHz
Phase Jitter (RMS)*
for F
OUT
of 125 to 500 MHz
Symbol
Test Condition
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
Typ
0.25
0.26
0.36
0.34
Max
0.40
0.37
0.50
0.42
ps
Units
ps
φ
J
φ
J
12 kHz to 20 MHz (OC-48)
50 kHz to 20 MHz (OC-192)
*Note:
Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Table 5. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
Typ
2
14
Max
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
120.00 MHz
LVDS
–112
–122
–132
–137
–144
–150
n/a
156.25 MHz
LVPECL
–105
–122
–128
–135
–144
–147
n/a
622.08 MHz
LVPECL
–97
–107
–116
–121
–134
–146
–148
Units
dBc/Hz
4
Rev. 1.1
Si530/531
Table 7. Absolute Maximum Ratings
1
Parameter
Maximum Operating Temperature
Supply Voltage
Input Voltage (any input pin)
Storage Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)
2
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
Symbol
T
AMAX
V
DD
V
I
T
S
ESD
T
PEAK
t
P
Rating
85
–0.5 to +3.8
–0.5 to V
DD
+ 0.3
–55 to +125
2500
260
20–40
Units
ºC
Volts
Volts
ºC
Volts
ºC
seconds
Notes:
1.
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2.
The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO
for further information, including soldering profiles.
Table 8. Environmental Compliance
The Si530/531 meets the following qualification test requirements.
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross & Fine Leak
Resistance to Solvents
Conditions/Test Method
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Rev. 1.1
5
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