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ALD4702ASB

器件型号:ALD4702ASB
器件类别:模拟混合信号IC    放大器电路   
文件大小:60KB,共6页
厂商名称:ALD [Advanced Linear Devices]
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器件描述

Operational Amplifier, 4 Func, 2000uV Offset-Max, CMOS, PDSO14, SOIC-14

参数
参数名称属性值
是否Rohs认证不符合
厂商名称ALD [Advanced Linear Devices]
零件包装代码SOIC
包装说明,
针数14
Reach Compliance Codeunknown
ECCN代码EAR99
放大器类型OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB)0.0003 µA
标称共模抑制比83 dB
最大输入失调电压2000 µV
JESD-30 代码R-PDSO-G14
湿度敏感等级1
负供电电压上限-6.6 V
标称负供电电压 (Vsup)-2.5 V
功能数量4
端子数量14
最高工作温度70 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)225
认证状态Not Qualified
标称压摆率1.9 V/us
供电电压上限6.6 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式GULL WING
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
标称均一增益带宽1500 kHz

文档预览

A
DVANCED
L
INEAR
D
EVICES,
I
NC.
ALD4702A/ALD4702B
ALD4702
QUAD 5V RAIL-TO-RAIL PRECISION OPERATIONAL AMPLIFIER
GENERAL DESCRIPTION
The ALD4702 is a quad monolithic precision CMOS rail-to-rail
operational amplifier intended for a broad range of analog applications
using
±2.5V
to
±6V
dual power supply systems, as well as +4V to
+12V battery operated systems. All device characteristics are
specified for +5V single supply or
±2.5V
dual supply systems. Total
supply current for four operational amplifiers is 6mA maximum at 5V
supply voltage. It is manufactured with Advanced Linear Devices'
enhanced ACMOS silicon gate CMOS process.
The ALD4702 is designed to offer a trade-off of performance
parameters providing a wide range of desired specifications. It offers
the popular industry pin configuration of LM324 and ICL7641 types.
The ALD4702 has been developed specifically with the +5V single
supply or
±2.5V
dual supply user. Several important characteristics
of the device make many applications easy to implement for these
supply voltages. First, the operational amplifier can operate with rail
to rail input and output voltages. This feature allows numerous
analog serial stages to be implemented without losing operating
voltage margin. Secondly, the device was designed to accommodate
mixed applications where digital and analog circuits may work off the
same 5V power supply. Thirdly, the output stage can drive up to
400pF capacitive and 5KΩ resistive loads in non-inverting unity gain
connection and double the capacitance in the inverting unity gain
mode.
These features, coupled with extremely low input currents, high
voltage gain, useful bandwidth of 1.5MHz, a slew rate of 2.1V/µs, low
power dissipation, low offset voltage and temperature drift, make the
ALD4702 a truly versatile, user friendly, operational amplifier.
The ALD4702 is designed and fabricated with silicon gate CMOS
technology, and offers 1pA typical input bias current. On-chip offset
voltage trimming allows the device to be used without nulling in most
applications. The device offers typical offset drift of less than 7µV/
°C
which eliminates many trim or temperature compensation circuits.
For precision applications, the ALD4702 is designed to settle to
0.01% in 8µs.
FEATURES
• Rail-to-rail input and output voltage ranges
• Symmetrical push-pull class AB output drivers
• All parameters specified for +5V single supply
or
±2.5V
dual supply systems
• Inputs can extend beyond supply rails by 300mV
• Outputs settle to 2mV of supply rails
• High load capacitance capability up to 4000pF
• No frequency compensation required --
unity gain stable
• Extremely low input bias currents --
1.0pA typical
• Ideal for high source impedance applications
• Dual power supply
±2.5V
to
±5.0V
operation
• Single power supply +5V to +12V operation
• High voltage gain-typically 85V/mV @
±2.5V
and 250V/mV @
±5.0V
• Drive as low as 2KΩ load with 5mA drive current
• Output short circuit protected
• Unity gain bandwidth of 1.5MHz
• Slew rate of 1.9V/µs
• Low power dissipation
APPLICATIONS
Voltage amplifier
Voltage follower/buffer
Charge integrator
Photodiode amplifier
Data acquisition systems
High performance portable instruments
Signal conditioning circuits
Sensor and transducer amplifiers
Low leakage amplifiers
Active filters
Sample/Hold amplifier
Picoammeter
Current to voltage convert
Coaxial cable driver
PIN CONFIGURATION
ORDERING INFORMATION
Operating Temperature Range*
-55°C to +125°C
0°C to +70°C
0°C to +70°C
14-Pin
CERDIP
Package
ALD4702A DB
ALD4702B DB
ALD4702 DB
14-Pin
Small Outline
Package (SOIC)
ALD4702A SB
ALD4702B SB
ALD4702 SB
14-Pin
Plastic Dip
Package
ALD4702A PB
ALD4702B PB
ALD4702 PB
OUT
A
-IN
A
1
2
14
13
12
11
10
9
8
OUT
D
-IN
D
+IN
D
V-
+IN
C
-IN
C
OUT
C
+IN
A
3
V+
4
+IN
B
5
-IN
B
OUT
B
6
7
* Contact factory for industrial temperature range
DB, PB, SB Package
© 1998 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
+
referenced to V
-
Supply voltage, V
S
referenced to V
-
Differential input voltage range
Power dissipation
Operating temperature range PB, SB package
DB package
Storage temperature range
Lead temperature, 10 seconds
-0.3V to V++13.2V
±6.6V
+ +0.3V
-0.3V to V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
T
A
= 25
°
C V
S
=
±
2.5V unless otherwise specified
Parameter
Supply
Voltage
Input Offset
Voltage
Input Offset
Current
Input Bias
Current
Input Voltage
Range
Input
Resistance
Input Offset
Voltage Drift
Power Supply
Rejection Ratio
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
Output
Voltage
Range
Symbol
V
S
V
+
V
OS
I
OS
I
B
V
IR
R
IN
TCV
OS
PSRR
65
65
65
65
15
-0.3
-2.8
10
12
1.0
1.0
Min
±2.0
4.0
4702A
Typ
Max
±6.0
12.0
1.0
2.0
25
240
30
300
5.3
+2.8
-0.3
-2.8
10
12
1.0
1.0
Min
±2.0
4.0
4702B
Typ Max
±6.0
12.0
2.0
3.5
25
240
30
300
5.3
+2.8
-0.3
-2.8
10
12
1.0
1.0
Min
±2.0
4.0
4702
Typ
Max
±6.0
12.0
5.0
6.5
25
240
30
300
5.3
+2.8
Unit
V
V
mV
mV
pA
pA
pA
pA
V
V
µV/°C
dB
R
S
100KΩ
R
S
100KΩ
0°C
T
A
+70°C
R
S
100KΩ
0°C
T
A
+70°C
R
L
= 10KΩ
R
L
1MΩ
R
L
= 1MΩ Single supply
0°C
T
A
+70°C
R
L
= 10KΩ Dual supply
0°C
T
A
+70°C
Test Conditions
Dual Supply
Single Supply
R
S
100KΩ
0°C
T
A
+70°C
T
A
= 25°C
0°C
T
A
+70°C
T
A
= 25°C
0°C
T
A
+70°C
V
+
= +5V
V
S
=
±2.5V
7
83
83
83
83
28
100
0.002
4.998
-2.44
2.44
8
0.01
65
65
65
65
15
7
83
83
83
83
28
100
0.01
60
60
60
60
12
7
83
83
83
83
28
100
0.01
CMRR
dB
A
V
V/mV
V/mV
V
V
O
low
V
O
high
V
O
low
V
O
high
4.99
0.002
4.99 4.998
0.002
4.99 4.998
-2.40
2.40
2.40
-2.44 -2.40
2.44
8
2.40
-2.44 -2.40
2.44
8
V
Output Short
Circuit Current
Supply
Current
Power
Dissipation
Input
Capacitance
Bandwidth
Slew Rate
Rise time
Overshoot
Factor
I
SC
mA
I
S
P
D
C
IN
B
W
S
R
t
r
0.7
1.1
4.0
6.0
4.0
6.0
4.0
6.0
mA
V
IN
= 0V No Load
V
S
=
±2.5V
All four amplifiers
20
30
20
30
20
30
mW
1
1
1
pF
1.5
1.9
0.2
10
0.7
1.1
1.5
1.9
0.2
10
0.7
1.1
1.5
1.9
0.2
10
MHz
V/µs
µs
%
A
V
= +1 R
L
= 10KΩ
R
L
= 10KΩ
R
L
= 10KΩ C
L
= 100pF
ALD4702A/ALD4702B
ALD4702
Advanced Linear Devices
2
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
T
A
= 25
°
C V
S
=
±
2.5V unless otherwise specified
Parameter
Maximum Load
Capacitance
Symbol
C
L
Min
4702A
Typ
400
4000
Max
Min
4702B
Typ
400
4000
Max
Min
4702
Typ
400
4000
Max
Uni
pF
pF
Test Conditions
Gain = 1
Gain = 5
Input Noise
Voltage
e
n
26
26
26
nV/√Hz
f = 1KHz
Input Current
Noise
i
n
0.6
0.6
0.6
fA/√Hz
f = 10Hz
Settling
Time
t
s
8.0
3.0
8.0
3.0
8.0
3.0
µs
µs
0.01%
0.1% A
V
= -1
R
L
= 5KΩ C
L
= 50pF
T
A
= 25
°
C V
S
=
±
5.0V unless otherwise specified
Parameter
Power Supply
Rejection Ratio
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
Output Voltage
Range
Bandwidth
Slew Rate
Symbol
PSRR
4702A
Min
Typ
83
Max
4702B
Min Typ
83
Max
Min
4702
Typ
83
Max
Unit
dB
Test Conditions
R
S
100KΩ
CMRR
83
83
83
dB
R
S
100KΩ
A
V
V
O
low
V
O
high
B
W
S
R
250
250
250
V/mV
R
L
= 10KΩ
R
L
= 10KΩ
4.8
-4.90
4.93
1.7
2.8
-4.8
4.8
-4.90
4.93
1.7
2.8
-4.8
4.8
-4.90
4.93
1.7
2.8
-4.8
V
MHz
V/µs
A
V
= +1
C
L
= 50pF
V
S
= +5.0V -55
°
C
T
A
+125
°
C unless otherwise specified
Parameter
Input Offset
Voltage
Input Offset
Current
Input Bias
Current
Power Supply
Rejection Ratio
Common Mode
Rejection Ratio
Large Signal
Voltage Gain
Output Voltage
Range
Symbol
V
OS
I
OS
I
B
PSRR
CMRR
A
V
V
O
low
V
O
high
60
60
10
75
83
25
0.1
4.9
0.2
4.8
Min
4702A DA
Typ Max
2.0
8.0
10.0
60
60
10
75
83
25
0.1
4.9
0.2
4.8
Min
4702B DA
Typ Max
4.0
8.0
10.0
60
60
7
75
83
25
0.1
4.9
0.2
Min
4702 DA
Typ
Max
7.0
8.0
10.0
Unit
mV
nA
nA
dB
dB
V/mV
V
R
S
100KΩ
R
S
100KΩ
A
V
= +1
R
L
10KΩ
R
L
10KΩ
Test Conditions
R
S
100KΩ
4.8
ALD4702A/ALD4702B
ALD4702
Advanced Linear Devices
3
Design & Operating Notes:
1. The ALD4702 CMOS operational amplifier uses a 3 gain stage
architecture and an improved frequency compensation scheme to
achieve large voltage gain, high output driving capability, and better
frequency stability. The ALD4702 is internally compensated for unity
gain stability using a novel scheme. This design produces a clean
single pole roll off in the gain characteristics while providing for more
than 70 degrees of phase margin at the unity gain frequency. A unity
gain buffer using the ALD4702 will typically drive 400pF of external
load capacitance without stability problems. In the inverting unity gain
configuration, it can drive up to 800pF of load capacitance. Compared
to other CMOS operational amplifiers, the ALD4702 is much more
resistant to parasitic oscillations.
2. The ALD4702 has complementary p-channel and n-channel input
differential stages connected in parallel to accomplish rail-to-rail input
common mode voltage range. With the common mode input voltage
close to the power supplies, one of the two differential stages is
switched off internally. To maintain compatibility with other opera-
tional amplifiers, this switching point has been selected to be about
1.5V above the negative supply voltage. As offset voltage trimming on
the ALD4702 is made when the input voltage is symmetrical to the
supply voltages, this internal switching does not affect a large variety
of applications such as an inverting amplifier or non-inverting amplifier
with a gain greater than 2.5 (5V operation), where the common mode
voltage does not make excursions below this switching point.
3. The input bias and offset currents are essentially input protection diode
reverse bias leakage currents, and are typically less than 1pA at
room temperature. This low input bias current assures that the
analog signal from the source will not be distorted by input bias
currents. For applications where source impedance is very high,
it may be necessary to limit noise and hum pickup through proper
shielding.
4. The output stage consists of class AB complementary output
drivers, capable of driving a low resistance load. The output
voltage swing is limited by the drain to source on-resistance of the
output transistors as determined by the bias circuitry, and the
value of the load resistor when connected. In the voltage follower
configuration, the oscillation resistant feature, combined with the
rail to rail input and output feature, makes the ALD4702 an
effective analog signal buffer for medium to high source imped-
ance sensors, transducers, and other circuit networks.
5. The ALD4702 operational amplifier has been designed with static
discharge protection. Internally, the design has been carefully
implemented to minimize latch up. However, care must be
exercised when handling the device to avoid strong static fields.
In using the operational amplifier, the user is advised to power up
the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages to not exceed 0.3V of the power
supply voltage levels. Alternatively, a 100KΩ or higher value
resistor at the input terminals will limit input currents to acceptable
levels while causing very small or negligible accuracy effects.
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
±7
±6
COMMON MODE INPUT
)
VOLTAGE RANGE (V
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
1000
} -55°C
T
A
= 25°C
OPEN LOOP VOLTAGE
GAIN (V/mV)
±5
±4
±3
±2
±1
0
0
±1
±2
±3
±4
±5
±6
±7
} +25°C
100
} +125°C
10
R
L
= 10KΩ
R
L
= 5KΩ
1
0
±2
±4
SUPPLY VOLTAGE (V)
±6
±8
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
10000
12
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
10
8
T
A
= -55°C
6
4
2
0
-25°C
+25°C
+80°C
+125°C
INPUTS GROUNDED
OUTPUTS UNLOADED
INPUT BIAS CURRENT (pA)
1000
100
V
S
=
±
2.5V
10
1.0
0.1
-50
-25
0
25
50
75
100
125
±1
±2
±3
±4
±5
±6
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ALD4702A/ALD4702B
ALD4702
Advanced Linear Devices
4
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE
120
±25°C ≤
T
A
125°C
RL = 10KΩ
R
L
= 10KΩ
OPEN LOOP VOLTAGE GAIN AS
A FUNCTION OF FREQUENCY
100
80
60
40
20
0
-20
0
45
90
135
180
1
10
100
1K
10K
100K
1M
10M
V
S
=
±2.5V
T
A
= 25°C
±7
OUTPUT VOLTAGE SWING (V)
±5
±4
±3
±2
0
±1
±2
R
L
= 2KΩ
±3
±4
±5
±6
±7
OPEN LOOP VOLTAGE
GAIN (dB)
±6
PHASE SHIFT IN DEGREES
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
INPUT OFFSET VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE
REPRESENTATIVE UNITS
INPUT OFFSET VOLTAGE (mV)
V
S
=
±2.5V
INPUT OFFSET VOLTAGE AS A FUNCTION
OF COMMON MODE INPUT VOLTAGE
15
INPUT OFFSET VOLTAGE (mV)
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5
-50
-25
0
+25
+50
10
5
0
-5
-10
-15
V
S
=
±2.5V
T
A
= 25°C
+75
+100 +125
-2
-1
0
+1
+2
+3
AMBIENT TEMPERATURE (°C)
COMMON MODE INPUT VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
OPEN LOOP VOLTAGE GAIN (V/mV)
1000
VOLTAGE NOISE DENSITY AS A
FUNCTION OF FREQUENCY
150
VOLTAGE NOISE DENSITY
(nV/
Hz)
V
S
=
±2.5V
T
A
= 25°C
100
125
100
75
50
25
0
V
S
=
±2.5V
T
A
= 25°C
10
1
1K
10K
100K
1000K
10
100
1K
10K
100K
1000K
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
LARGE - SIGNAL TRANSIENT
RESPONSE
5V/div
V
S
=
±2.5V
T
A
= 25°C
R
L
= 10KΩ
C
L
= 50pF
SMALL - SIGNAL TRANSIENT
RESPONSE
100 mV/div
V
S
=
±2.5V
T
A
= 25°C
R
L
= 10KΩ
C
L
= 50pF
1V/div
2µs/div
20 mV/div
2µs/div
ALD4702A/ALD4702B
ALD4702
Advanced Linear Devices
5
与ALD4702ASB相近的元器件有:ALD4702PB、ALD4702SB、ALD4702APB、ALD4702BPB、ALD4702BSB。描述及对比如下:
型号 ALD4702ASB ALD4702PB ALD4702SB ALD4702APB ALD4702BPB ALD4702BSB
描述 Operational Amplifier, 4 Func, 2000uV Offset-Max, CMOS, PDSO14, SOIC-14 Operational Amplifier, 4 Func, 6500uV Offset-Max, CMOS, PDIP14, PLASTIC, DIP-14 Operational Amplifier, 4 Func, 6500uV Offset-Max, CMOS, PDSO14, SOIC-14 Operational Amplifier, 4 Func, 2000uV Offset-Max, CMOS, PDIP14, PLASTIC, DIP-14 Operational Amplifier, 4 Func, 3500uV Offset-Max, CMOS, PDIP14, PLASTIC, DIP-14 Operational Amplifier, 4 Func, 3500uV Offset-Max, CMOS, PDSO14, SOIC-14
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 ALD [Advanced Linear Devices] ALD [Advanced Linear Devices] ALD [Advanced Linear Devices] ALD [Advanced Linear Devices] ALD [Advanced Linear Devices] ALD [Advanced Linear Devices]
零件包装代码 SOIC DIP SOIC DIP DIP SOIC
针数 14 14 14 14 14 14
Reach Compliance Code unknown unknown unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
放大器类型 OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB) 0.0003 µA 0.0003 µA 0.0003 µA 0.0003 µA 0.0003 µA 0.0003 µA
标称共模抑制比 83 dB 83 dB 83 dB 83 dB 83 dB 83 dB
最大输入失调电压 2000 µV 6500 µV 6500 µV 2000 µV 3500 µV 3500 µV
JESD-30 代码 R-PDSO-G14 R-PDIP-T14 R-PDSO-G14 R-PDIP-T14 R-PDIP-T14 R-PDSO-G14
湿度敏感等级 1 1 1 1 1 1
负供电电压上限 -6.6 V -6.6 V -6.6 V -6.6 V -6.6 V -6.6 V
标称负供电电压 (Vsup) -2.5 V -2.5 V -2.5 V -2.5 V -2.5 V -2.5 V
功能数量 4 4 4 4 4 4
端子数量 14 14 14 14 14 14
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE IN-LINE SMALL OUTLINE IN-LINE IN-LINE SMALL OUTLINE
峰值回流温度(摄氏度) 225 225 225 225 225 225
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
标称压摆率 1.9 V/us 1.9 V/us 1.9 V/us 1.9 V/us 1.9 V/us 1.9 V/us
供电电压上限 6.6 V 6.6 V 6.6 V 6.6 V 6.6 V 6.6 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
表面贴装 YES NO YES NO NO YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子形式 GULL WING THROUGH-HOLE GULL WING THROUGH-HOLE THROUGH-HOLE GULL WING
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
标称均一增益带宽 1500 kHz 1500 kHz 1500 kHz 1500 kHz 1500 kHz 1500 kHz
阻抗匹配集
带有阻抗和导纳圈的史密斯圆图[attach]686290[/attach] 高速PCB设计为什么要控制阻抗匹配原理图——HDMI这些电阻是做阻抗匹配还是扛静电用的?天线阻抗匹配与极宽带天线的设计天线阻抗匹配与极宽带天线的设计微带传输线阻抗匹配工程实例阻抗匹配基本原理及设计方法阻抗匹配原理功率放大器的阻抗匹配阻抗匹配与史密斯(Smith...
btty038 RF/无线
海思Hi3516EV200/Hi3518EV300资料
Hi3516EV200 经济型HD IP Camera SoC主要特点处理器内核 ARM Cortex A7@ 900MHz,32KB I-Cache,32KB DCache/128KB L2 cache 支持 Neon 加速,集成FPU 处理单元视频编码 H.264 BP/MP/HP,支持I/P 帧 H.265 Main Profile,支持I/P...
littleshrimp 国产芯片交流
弱弱的问一个ARM启动代码的问题
以下是一级向量表ResetEntryb ResetHandler;复位处理b HandlerUndef;未定义处理b HandlerSWI;SWI中断处理b HandlerPabort;指令中止处理b HandlerDabort;数据中止处理b .;保留b HandlerIRQ;中断处理b HandlerFIQ;快速中断处理;----------------...
sanwa_chen ARM技术
Synopsys syn_vZ-2007.03-SP5的安装问题
初来乍到,不知道这问题该发哪,只好发这了。发错了,请斑斑移到该去的地方,就是别删阿。鞠躬linux红帽系统。安装完Synopsys syn_vZ-2007.03-SP5后,可以用了,但是在其/dw目录下,子目录/syn_ver要比/sim_ver少好多文件,用的人说这两个目录下的文件应该是对等的,我就是按照默认的那种安装一路next,然后就好了。请问我少做了...
shdh6015 嵌入式系统
三十岁之前要完成的事
做为一个人都会去想自己要做什么事,做为男人我们不同的阶段有不同的事要做,给自己一条路,就好比给了生活的动力与方向。我时刻在思考着我的人生该怎样去过,看一下这篇文章,还是会有些体会的。 1,事业永远第一   虽然金钱不是万能的,但没有钱是万万不能的,虽然这句话很俗,但绝对有道理,所以30岁之前,请把你大部分精力放在你的事业上.    2,别把钱看得太重   不...
sdjntl 聊聊、笑笑、闹闹
如何制作最小的2.4G无线USB_dongle
NORDIC官方给出的2.4G无线USB_dongle制作的指导方法,很实用,感兴趣的就下载吧![attach]56837[/attach]...
lilya RF/无线

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