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GAL
®
20RA10 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
GAL20RA10
Ordering Part Number
GAL20RA10B-10LP
GAL20RA10B-15LP
GAL20RA10B-20LP
GAL20RA10B-30LP
GAL20RA10B-20LPI
GAL20RA10B-7LJ
GAL20RA10B-10LJ
GAL20RA10B-15LJ
GAL20RA10B-20LJ
GAL20RA10B-30LJ
GAL20RA10B-20LJI
Product Status
Reference PCN
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
GAL20RA10
High-Speed Asynchronous E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 9 ns Maximum from Clock Input to Data Output
— TTL Compatible 8 mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
Functional Block Diagram
PL
8
I
OLMC
I/O/Q
8
• TEN OUTPUT LOGIC MACROCELLS
— Independent Programmable Clocks
— Independent Asynchronous Reset and Preset
— Registered or Combinatorial with Polarity
— Full Function and Parametric Compatibility with
PAL20RA10
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— State Machine Control
— Standard Logic Consolidation
— Multiple Clock Logic Designs
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E
2
) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E
2
CMOS circuitry achieves power levels as low
as 75mA typical I
CC
which represents a substantial savings in power
when compared to bipolar counterparts. E
2
technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(80X40)
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
8
I
OLMC
I/O/Q
Description
OE
Pin Configuration
PLCC
Vcc
NC
DIP
PL
1
24
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I
I
I
I
I
I
I/O/Q
PL
I/O/Q
4
2
28
26
I
I
I
5
25
I/O/Q
I/O/Q
I/O/Q
GAL
20RA10
I
I
6
7
NC
I
I
I
9
GAL20RA10
Top View
14
16
23
18
NC
21
I/O/Q
I/O/Q
11
12
19
18
I/O/Q
GND
OE
I
I
I/O/Q
I/O/Q
NC
GND
12
13
OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
20ra10_02
1
Specifications
GAL20RA10
GAL20RA10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
7.5
10
Tsu (ns)
3
4
Tco (ns)
9
11
Icc (mA)
100
100
100
Ordering #
GAL20RA10B-7LJ
GAL20RA10B-10LP
GAL20RA10B-10LJ
GAL20RA10B-15LP
GAL20RA10B-15LJ
Package
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
15
7
15
100
100
Industrial Grade Specifications
Tpd (ns)
20
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
20
10
20
100
GAL20RA10B-20LP
GAL20RA10B-20LJ
24-Pin Plastic DIP
28-Lead PLCC
100
30
20
30
100
GAL20RA10B-30LP
GAL20RA10B-30LJ
24-Pin Plastic DIP
28-Lead PLCC
100
Tsu (ns)
10
Tco (ns)
20
Icc (mA)
120
Ordering #
Package
GAL20RA10B-20LPI
GAL20RA10B-20LJI
24-Pin Plastic DIP
28-Lead PLCC
120
Part Number Description
XXXXXXXX
_
XX
X X X
GAL20RA10B
Device Name
Speed (ns)
Power
Grade
Blank = Commercial
I = Industrial
L = Low Power
Package
P = Plastic DIP
J = PLCC
2
Specifications
GAL20RA10
Output Logic Macrocell (OLMC)
The GAL20RA10 OLMC consists of 10 D flip-flops with indi-
vidual asynchronous programmable reset, preset and clock product
terms. The sum of four product terms and an Exclusive-OR pro-
vide a programmable polarity D-input to each flip-flop. An output
enable term combined with the dedicated output enable pin pro-
vides tri-state control of each output. Each OLMC has a flip-flop
bypass, allowing any combination of registered or combinatorial
outputs.
The GAL20RA10 has 10 dedicated input pins and 10 program-
mable I/O pins, which can be either inputs, outputs, or dynamic I/
O. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange I/O pin assignments without restric-
tion.
Asynchronous Reset and Preset
Each GAL20RA10 macrocell has an independent asynchronous
reset and preset control product term. The reset and preset product
terms are level sensitive, and will hold the flip-flop in the reset or
preset state while the product term is active independent of the clock
or D-inputs. It should be noted that the reset and preset term al-
ter the state of the flip-flop whose output is inverted by the output
buffer. A reset of the flip-flop will result in the output pin becoming
a logic high and a preset will result in a logic low.
RESET PRESET
FUNCTION
0
0
Registered function of data product term
1
0
Reset register to "0" (device pin = "1")
0
1
Preset register to "1" (device pin = "0")
1
1
Register-bypass (combinatorial output)
An independent clock control product term is provided for each
GAL20RA10 macrocell. Data is clocked into the flip-flop on the
active edge of the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These clocks
can be derived from any pin or combination of pins and/or feedback
from other flip-flops. Multiple clock sources allow a number of
asynchronous register functions to be combined into a single
GAL20RA10. This allows the designer to combine discrete logic
functions into a single device.
The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flip-
flop. The polarity of the pin is active low when XOR bit is pro-
grammed (or zero) and is active high when XOR bit is erased (or
one). Because of the inverted output buffer, the XOR gate output
node is opposite polarity from the pin. It should be noted that the
programmable polarity only affects the data latched into the flip-flop
on the active edge of the clock product term. The reset, preset and
preload will alter the state of the flip-flop independent of the state
of programmable polarity bit. The ability to program the active po-
larity of the D-inputs can be used to reduce the total number of
product terms used, by allowing the DeMorganization of the logic
functions. This logic reduction is accomplished by the logic com-
piler, and does not require the designer to define the polarity.
The output of each GAL20RA10 macrocell is controlled by the
“AND’ing” of an independent output enable product term and a
common active low output enable pin (pin 13 on DIP package / pin
16 on PLCC package). The output is enabled while the output en-
able product term is active and the output enable pin is low. This
output control structure allows several output enable alternatives.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Independent Programmable Clocks
Combinatorial Control
Programmable Polarity
Parallel Flip-Flop Preload
Output Enable
3
The register in each GAL20RA10 macrocell may be bypassed by
asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell as
a combinatorial output, or to fix the macrocell as combinatorial only
by forcing both reset and preset product terms active. Some logic
compilers will configure macrocells as registered or combinatorial
based on the logic equations, others require the designer to force
the reset and preset product terms active for combinatorial
macrocells.
The flip-flops of a GAL20RA10 can be reset or preset from the
I/O pins by applying a logic low to the preload pin (pin 1 on DIP
package / pin 2 on PLCC package) and applying the desired logic
level to each I/O pin. The I/O pins must remain valid for the preload
setup and hold time. All 10 flip-flops are reset or preset during
preload, independent of all other OLMC inputs.
A logic low on an I/O pin during preload will preset the flip-flop, a
logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin will disable all 10 outputs of the
GAL20RA10 when held high.
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