Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F002 device
■
High performance
— Access times as fast as 55 ns
■
Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top or bottom boot block configurations available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 write cycle guarantee per
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■
Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21527
Rev:
D
Amendment/0
Issue Date:
November 28, 2000
GENERAL DESCRIPTION
The Am29F002B Family consists of 2 Mbit, 5.0
volt-only Flash memory devices organized as 262,144
bytes. The Am29F002B offers the RESET# function,
the Am29F002NB does not. The data appears on
DQ7–DQ0. The device is offered in 32-pin PLCC,
32-pin TSOP, and 32-pin PDIP packages. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt V
CC
supply. No V
PP
is required for
write or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and
benefits of the Am29F002, which was manufactured
using 0.5 µm process technology.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
(This feature is not available on the Am29F002NB.)
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29F002B/Am29F002NB
November 28, 2000
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F002B/Am29F002NB Device Bus Operations . . . . . .8
Figure 4. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 17
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . .
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . .
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
19
Figure 5. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . .
Writing Commands/Command Sequences . . . . . . . . . . . . . . .
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . .
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
8
9
9
9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 21
Figure 6. Maximum Negative Overshoot Waveform . . . . . . . . . . . 21
Figure 7. Maximum Positive Overshoot Waveform . . . . . . . . . . . . 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Key to Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 29
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 30
Figure 14. Toggle Bit Timings (During Embedded Algorithms) . . . 30
Figure 15. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Temporary Sector Unprotect Timing Diagram
(Am29F002B only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Alternate CE# Controlled Write Operation Timings . . . 33
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Am29F002B/Am29F002NB Autoselect Codes (High
Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 10
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . .11
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Low V
CC
Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . 12
Byte Program Command Sequence . . . . . . . . . . . . . . . . . . . 12
Figure 2. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 13
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . 15
Command Definitions ............................................................. 16
Table 5. Am29F002B/Am29F002NB Command Definitions . . . . . .16
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 17
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase and Programming Performance . . . . . . . 34
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 34
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 34
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 35
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36
PD 032—32-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . 36
PL 032—32-Pin Plastic Leaded Chip Carrier . . . . . . . . . . . . 37
TS 032—32-Pin Standard Thin Small Package . . . . . . . . . . 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision A (July 1998) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision B (January 1999) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision C (November 12, 1999) . . . . . . . . . . . . . . . . . . . . . 39
Revision D (November 28, 2000) . . . . . . . . . . . . . . . . . . . . . 39
November 28, 2000
Am29F002B/Am29F002NB
3
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
V
CC
= 5.0 V ± 5%
V
CC
= 5.0 V ± 10%
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
55
55
30
-55
-70
70
70
30
-90
90
90
35
-120
120
120
50
Am29F002B/Am29F002NB
BLOCK DIAGRAM
DQ0
–
DQ7
V
CC
V
SS
RESET#
n/a Am29F002NB
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A17
4
Am29F002B/Am29F002NB
November 28, 2000
CONNECTION DIAGRAMS
NC on Am29F002NB
NC on Am29F002NB
RESET#
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
PDIP
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A16
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A12
A15
WE#
RESET#
4 3 2
1 32 31 30
29
28
27
26
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
PLCC
WE#
A17
25
24
23
22
21
DQ5
DQ6
14 15 16 17 18 19 20
DQ1
DQ2
DQ3
V
SS
DQ4
NC on Am29F002NB
A11
A9
A8
A13
A14
A17
WE#
V
CC
RESET#
A16
A15
A12
A7
A6
A5
A4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
November 28, 2000
Am29F002B/Am29F002NB
5
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