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HY5V66EFP-5

器件型号:HY5V66EFP-5
器件类别:存储    存储   
厂商名称:SK Hynix(海力士)
厂商官网:http://www.hynix.com/eng/
标准:
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器件描述

Synchronous DRAM, 4MX16, 4.5ns, CMOS, PBGA54, 8 X 8 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-54

参数
参数名称属性值
是否Rohs认证符合
厂商名称SK Hynix(海力士)
零件包装代码BGA
包装说明TFBGA, BGA54,9X9,32
针数54
Reach Compliance Codeunknown
ECCN代码EAR99
访问模式FOUR BANK PAGE BURST
最长访问时间4.5 ns
其他特性AUTO/SELF REFRESH
最大时钟频率 (fCLK)200 MHz
I/O 类型COMMON
交错的突发长度1,2,4,8
JESD-30 代码S-PBGA-B54
JESD-609代码e1
长度8 mm
内存密度67108864 bit
内存集成电路类型SYNCHRONOUS DRAM
内存宽度16
功能数量1
端口数量1
端子数量54
字数4194304 words
字数代码4000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织4MX16
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TFBGA
封装等效代码BGA54,9X9,32
封装形状SQUARE
封装形式GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)260
电源3.3 V
认证状态Not Qualified
刷新周期4096
座面最大高度1.2 mm
自我刷新YES
连续突发长度1,2,4,8,FP
最大待机电流0.002 A
最大压摆率0.12 mA
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Silver/Copper (Sn/Ag/Cu)
端子形式BALL
端子节距0.8 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间20
宽度8 mm

文档预览

64Mb Synchronous DRAM based on 1M x 4Bank x16 I/O
Document Title
4Bank x 1M x 16bits Synchronous DRAM
Revision History
Revision No.
0.1
History
Initial Draft
Draft Date
Dec. 2004
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / Dec. 2004
1
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F(P) Series
DESCRIPTION
11
Preliminary
The Hynix HY5V66E(L)F(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5V66E(L)F(P) is organized as 4banks of 1,048,576 x 16.
HY5V66E(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
54 Ball FBGA (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
Internal four banks operation
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 2, 3 Clocks
Burst Read Single Write operation
Rev. 0.1 / Dec. 2004
2
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F(P) Series
ORDERING INFORMATION
Part Number
HY5V66E(L)F(P)-5
HY5V66E(L)F(P)-6
HY5V66E(L)F(P)-7
HY5V66E(L)F(P)-H
Clock
Frequency
200MHz
166MHz
143MHz
133MHz
4Banks x 1Mbits
x16
LVTTL
54 Ball FBGA
Organization
Interface
Package
11
Preliminary
Note:
1. HY5V66EF Series: Normal power, Leaded.
2. HY5V66ELF Series: Low power, Leaded.
3. HY5V66EFP Series: Normal power, Lead Free.
4. HY5V66ELFP Series: Low power, Lead Free.
Rev. 0.1 / Dec. 2004
3
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F(P) Series
BALL CONFIGURATION
11
Preliminary
9
8
7
3
2
1
A
B
C
D
E
F
G
H
J
54 Ball
FBGA
0.8mm
Ball Pitch
<Bottom View>
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
VSS
2
DQ15
3
VSSQ
7
A
B
C
D
E
F
G
H
J
VDDQ
8
DQ0
9
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ11
VSSQ
VDDQ
DQ4
DQ9
VDDQ
VSSQ
DQ6
NC
VSS
VDD
LDQM
CLK
CKE
/CAS
/RAS
A11
A9
BA0
BA1
A7
A6
A0
A1
A5
A4
A3
A2
< Top View >
Rev. 0.1 / Dec. 2004
4
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F(P) Series
BALL DESCRIPTION
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS,
WE
UDQM,
LDQM
DQ0 ~
DQ15
V
DD
/ V
SS
V
DDQ
/
V
SSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among (deep) power down, suspend or self refresh
Chip Select: Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Bank Address: Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask: Controls output buffers in read mode and masks input data in write mode
Data Input / Output: Multiplexed data input / output pin
Power supply
I/O Power supply
No connection : These pads should be left unconnected
11
Preliminary
Rev. 0.1 / Dec. 2004
5
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