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Datasheet> 器件分类 > 存储> 存储> IDT72P51777L7-5BBI
 

IDT72P51777L7-5BBI

器件型号：IDT72P51777L7-5BBI
器件类别：存储    存储   
文件大小：753KB，共88页
厂商名称：IDT (Integrated Device Technology)
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器件描述

FIFO, 256KX40, 3.8ns, Asynchronous, CMOS, PBGA376

参数
参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间3.8 ns
最大时钟频率 (fCLK)133 MHz
JESD-30 代码S-PBGA-B376
JESD-609代码e0
内存密度10485760 bit
内存集成电路类型OTHER FIFO
内存宽度40
端子数量376
字数262144 words
字数代码256000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织256KX40
封装主体材料PLASTIC/EPOXY
封装代码BGA
封装等效代码BGA376,22X22,40
封装形状SQUARE
封装形式GRID ARRAY
峰值回流温度（摄氏度）NOT SPECIFIED
电源1.8 V
认证状态Not Qualified
最大待机电流0.12 A
最大压摆率0.2 mA
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式BALL
端子节距1 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED

文档预览

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION
5,242,880 bits
10,485,760 bits
IDT72P51767
IDT72P51777
•
FEATURES
•
•
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•
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•
•
Choose from among the following memory density options:
IDT72P51767
⎯
Total Available Memory = 5,242,880 bits
IDT72P51777
⎯
Total Available Memory = 10,485,760 bits
Configurable from 1 to 128 Queues
Multiple default configurations of symmetrical queues
Default multi-queue device configurations
– IDT72P51767: 512 x 40 x 128Q
– IDT72P51777: 1,024 x 40 x 128Q
Number of queues and queue sizes may be configured; at
master reset, though serial programming, (via the queue
address bus)
166 MHz High speed operation (6ns cycle time)
0.48ns access time
Independent Read and Write access per queue
Echo Read Clock available
Internal PLL
On-chip Output Impedance matching
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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User Selectable Bus Matching Options:
– x40 in to x40 out
– x20 in to x20 out
– x40 in to x20 out
– x20in to x40out
User selectable I/O: 1.5V HSTL or 1.8V eHSTL
100% Bus Utilization, Read and Write on every clock cycle
Selectable Back off one (BOI) or IDT standard mode of operation
Ability to operate on packet or word boundaries
Mark and Re-Write operation
Mark and Re-Read operation
Individual, Active queue flags (EF,
FF, PAE, PAF)
8 bit parallel flag status on both read and write ports
Direct or polled operation of flag status bus
Expansion of up to 256 queues
JTAG Functionality (Boundary Scan)
Available in a 376-pin BGA, 1mm pitch, 23mm x 23mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
Green parts available, seeing Ordering Information
FUNCTIONAL BLOCK DIAGRAM
10G DDR MULTI-QUEUE FLOW-CONTROL DEVICE
ECHO CLOCK
WADEN
FSTR
WRADD
8
READ CONTROL
Q127
2
RADEN
ESTR
RDADD
8
WRITE CONTROL
Q126
REN
RCLK
EREN
WEN
WCLK
Q125
OE
x40 or x20
DATA IN
FF
PAF
PAFn
Din
Qout
x40 or x20
DATA OUT
WRITE FLAGS
READ FLAGS
EF
PAE
PAEn
8
Q0
8
6724 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2009
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2009
DSC-6724/2
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Table of Contents
Features ......................................................................................................................................................................................................................... 1
Description ...................................................................................................................................................................................................................... 5
Pin configuration .............................................................................................................................................................................................................. 7
Detailed Description ......................................................................................................................................................................................................... 8
Pin Descriptions ............................................................................................................................................................................................................. 10
Pin number table ........................................................................................................................................................................................................... 15
Recommended DC operating conditions ........................................................................................................................................................................ 16
Absolute maximum ratings .............................................................................................................................................................................................. 16
DC electrical characteristics ............................................................................................................................................................................................ 17
AC electrical characteristics ............................................................................................................................................................................................ 19
Functional description .................................................................................................................................................................................................... 22
Serial Programming .............................................................................................................................................................................................. 24
Default Programming ............................................................................................................................................................................................ 27
Parallel Programming ........................................................................................................................................................................................... 27
Modes of operation ........................................................................................................................................................................................................ 29
Standard mode operation ..................................................................................................................................................................................... 29
IDT Standard mode vs. BOI mode ........................................................................................................................................................................ 29
PLL on vs PLL off modes ...................................................................................................................................................................................... 30
Read Queue Selection and Read Operation ......................................................................................................................................................... 33
Switching Queues on the Write Port ...................................................................................................................................................................... 34
Switching Queues on the Read Port ..................................................................................................................................................................... 44
Flag Description ............................................................................................................................................................................................................ 52
PAFn
Flag Bus Operation .................................................................................................................................................................................... 52
Full Flag Operation ............................................................................................................................................................................................... 52
Empty Flag Operation ........................................................................................................................................................................................... 52
Almost Full Flag .................................................................................................................................................................................................... 53
Almost Empty Flag ................................................................................................................................................................................................ 53
JTAG Interface ............................................................................................................................................................................................................... 83
JTAG AC electrical characteristics ................................................................................................................................................................................... 87
Ordering Information ...................................................................................................................................................................................................... 88
List of Tables
Table 1 — Summary of the differences between the 4M MQ and 10G MQ ........................................................................................................................ 9
Table 2 — DC and AC specifications (informative) ......................................................................................................................................................... 21
Table 3 — IDT to XGMII Interface Mapping Schema ..................................................................................................................................................... 21
Table 4 — Device programming mode comparison ........................................................................................................................................................ 22
Table 5 — Setting the queue programming mode during master reset ............................................................................................................................. 23
Table 6 — ID[2:0] and WRADD[7:5]/RDADD[7:5] Configuration .................................................................................................................................... 27
Table 7 — Parallel Programming Mode Queue Configuration Example(1) ...................................................................................................................... 28
Table 8 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 32
Table 9 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 33
Table 10 — Write Queue Switch Operation .................................................................................................................................................................... 35
Table 11 — Backup Usage when Re-entering a Queue ................................................................................................................................................. 43
Table 13 — Same Queue Switch ................................................................................................................................................................................... 45
Table 12 — Read Queue Switch Operation .................................................................................................................................................................... 45
Table 14 — Flag operation boundaries & Timing ........................................................................................................................................................... 55
Table 15 — Interface Data Rates ................................................................................................................................................................................... 57
Table 16 — Bus-Matching Configurations ...................................................................................................................................................................... 58
2
FEBRUARY 11, 2009
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
List of Figures
Figure 1. Multi-Queue Flow-Control Device Block Diagram ............................................................................................................................................. 6
Figure 2a. AC Test Load ................................................................................................................................................................................................ 18
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18
Figure 3. HSTL Termination for XGMII ........................................................................................................................................................................... 21
Figure 4. Reference Signals .......................................................................................................................................................................................... 22
Figure 5. Expansion for Unlimited Number of Multi-Queue Devices Example .................................................................................................................. 28
Figure 6. Device Programming Hierarchy ..................................................................................................................................................................... 29
Figure 7. DDR Read Operation with PLL ON ................................................................................................................................................................. 30
Figure 8. DDR Read Operation with PLL OFF ............................................................................................................................................................... 30
Figure 9. SDR Read Operation with PLL ON ................................................................................................................................................................. 31
Figure 10. SDR Read Operation with PLL OFF ............................................................................................................................................................. 31
Figure 11. Write Port Switching Queues Signal Sequence .............................................................................................................................................. 34
Figure 12. Switching Queues Bus Efficiency ................................................................................................................................................................... 34
Figure 13. Simultaneous Queue Switching ..................................................................................................................................................................... 35
Figure 14. Application: Reading words from the MQ using the EOP bit to end the read operation ..................................................................................... 36
Figure 15. Output Data during a Queue Switch (SDR w/o PLL) ...................................................................................................................................... 37
Figure 16. Output Data during a Queue Switch (SDR w/ PLL) ....................................................................................................................................... 38
Figure 17. Output Data during a Queue Switch (DDR w/ PLL) ....................................................................................................................................... 39
Figure 18. Output Data during a Queue Switch (DDR w/o PLL) ..................................................................................................................................... 40
Figure 19. Output Data during two Queue Switches (DDR w/ PLL) ................................................................................................................................ 41
Figure 20. Output Data during two Queue Switches (DDR w/o PLL) .............................................................................................................................. 42
Figure 21. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 44
Figure 22. Switching Queues Bus Efficiency ................................................................................................................................................................... 44
Figure 23. Simultaneous Queue Switching ..................................................................................................................................................................... 45
Figure 24. MARK and Re-Write Sequence .................................................................................................................................................................... 46
Figure 25. MARK and Re-Read Sequence ................................................................................................................................................................... 46
Figure 26. MARKing a Queue - Write Queue MARK ...................................................................................................................................................... 47
Figure 27. MARKing a Queue - Read Queue MARK ..................................................................................................................................................... 47
Figure 28. UN-MARKing a Queue - Write Queue UN-MARK ......................................................................................................................................... 48
Figure 29. UN-MARKing a Queue - Read Queue UN-MARK ........................................................................................................................................ 48
Figure 30. Leaving a MARK active on the Write Port ...................................................................................................................................................... 49
Figure 31. Leaving a MARK active on the Read Port ..................................................................................................................................................... 49
Figure 32. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 50
Figure 33. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 50
Figure 34. DDR Source Synchronous Center Aligned Clocking .................................................................................................................................... 57
Figure 35. SDR Edge Aligned Clocking ........................................................................................................................................................................ 57
Figure 36. Bus-Matching Byte Arrangement .................................................................................................................................................................. 59
Figure 37. Master Reset ................................................................................................................................................................................................ 60
Figure 38. Default Programming .................................................................................................................................................................................... 61
Figure 39. Write Address/Read Address Programming ................................................................................................................................................... 62
Figure 40. Serial Port Connection for Serial Programming .............................................................................................................................................. 63
Figure 41. Serial Programming (2 Device Expansion) ................................................................................................................................................... 64
Figure 42. SDR Write Queue Select, Write Operation and Full Flag Operation ................................................................................................................ 65
Figure 43. DDR Write Operation, Write Queue Select, Full Flag Operation ...................................................................................................................... 66
Figure 44. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 67
Figure 45. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 68
Figure 46. SDR Read Queue Select, Read Operation (IDT mode) ................................................................................................................................ 69
Figure 47. DDR Read Operation, Read Queue Select,
EF
&
PAE
Flag Operation ......................................................................................................... 70
Figure 48. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 71
Figure 49. Standard Mode Pointers on Queue Re-entry for DDR Read Operation ......................................................................................................... 72
Figure 50. BOI Mode Pointers on Queue Re-entry for DDR Read Operation ................................................................................................................. 72
Figure 51. Read Queue Selection with Read Operations (IDT mode) (SDR mode, PLL = OFF) ..................................................................................... 73
Figure 52. Read Queue Select, Read Operation and
OE
Timing .................................................................................................................................... 74
Figure 53. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 75
Figure 54. Almost Full Flag Timing ................................................................................................................................................................................. 75
3
FEBRUARY 11, 2009
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
List of Figures (Continued)
Figure 55. Almost Empty Flag Timing ............................................................................................................................................................................. 76
Figure 56.
PAEn
- Direct Mode - Status Word Selection ................................................................................................................................................. 77
Figure 57.
PAFn
- Direct Mode - Status Word Selection ................................................................................................................................................. 77
Figure 58.
PAEn
- Direct Mode, Flag Operation ............................................................................................................................................................. 78
Figure 59.
PAFn
- Direct Mode, Flag Operation ............................................................................................................................................................. 79
Figure 60.
PAFn
Bus - Polled Mode .............................................................................................................................................................................. 80
Figure 61. Connecting two 10G MQ 128Q devices in Expansion Mode .......................................................................................................................... 81
Figure 62. Connecting THREE or more 10G MQ 128Q in Expansion Mode Using WADDR bit 7/RDADD bit 7 ............................................................... 82
Figure 63. Boundary Scan Architecture ......................................................................................................................................................................... 83
Figure 64. TAP Controller State Diagram ....................................................................................................................................................................... 84
Figure 65. Standard JTAG Timing .................................................................................................................................................................................. 87
4
FEBRUARY 11, 2009
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION
The IDT72P51767/ IDT72P51777 multi-queue flow-control devices are
single chip solutions containing up to 128 configurable queues. All queues within
the device have a common data input bus, Din [39:0] (write port) and a common
data output bus Qout [39:0], (read port). Data written into the write port is directed
to a respective queue via an integrated de-multiplex function. Data read from
the read port is accessed from a given queue transparently via an internal
multiplex operation. Data writes and reads can be performed at high speeds
up to 166MHz DDR allowing data rates up to 10Gigabits/s (OC-192). By utilizing
high speed interfaces such as 1.5V HSTL, coupled with a x40 bit data bus and
10Mb of data storage, the 10G Multi-Queue can interface with the industry
standard 10 Gigabits/sec Media Independent Interface (XGMII) to allow high
speed data transmission over 10G Ethernet and SONET line cards. Data write
and read operations are totally independent of each other. The Write Clock and
Read Clock can operate at independent frequencies. A different queue may
be selected on the write port and read port or both ports may select the same
queue simultaneously. Multiple clocking schemes are offered for this device as
well. The user can utilize either single ended or differential clocking for DDR
read operations. DDR write operation utilize a single ended clock. SDR write
and read operations utilize a single ended clock.
The devices provide Full flag and Empty flag status for the queue selected
for write and read operations respectively. Also a Programmable Almost Full
(PAF) and Programmable Almost Empty (PAE) flag for each queue is provided.
Two 8 bit programmable flag busses (PAFn,
PAEn)
are available, providing
status of queues that are not the present queue selected for write or read
operations. When 8 or fewer queues are configured in the device, these flag
busses provide an individual flag per queue, when more than 8 queues are
used; the queue status is multiplexed through the 8 stus lines. The multiplexing
can be configured either a Polled or Direct mode of bus.
Bus Matching is available on this device; either port can be x20 bits or x40
bits wide. When Bus Matching is used the device ensures the logical transfer
of data throughput. . With a 40 data bits configuration parity checking and packet
tagging is achievable if desired. Parity checking is available through the use of
4 user selectable bits as part of the 40 bit word. The user will be able to pass
along parity bits through the Multi-Queue to use for error detection in a up/down
stream device. The Multi-Queue device does not provide parity checking
circuits.
In Back off One mode, the user can switch queues without having to read the
last pipelined data word that is stored in the output register which in IDT standard
mode is required to be read out during a queue switch . The last pipelined data
word in BOI mode is retained in the output data register until it is actively read.
A Mark and Re-write and a Mark and Re-read function are available on the
write and read ports respectively. These functions allows for a mark location to
be independently issued on the read and/or write ports, in their respective
queues. The option to reset a given queue to the mark location effectively
dropping data written into the queue or allow data to be read again from the
device.
The devices offer a default configuration upon reset, offering 128 symmetrical
queues configured at start-up, which means the user can program the number
of queues to divide the 10Mb/5Mb of memory depending on the device. The
Multi-Queues can even be programmed to support one single queue to be used
as a FIFO for high performance applications of sequential queuing. The
programmable flag positions are also user programmable. If the user does not
wish to program the multi-queue device, a default option is available that
configures the device in a predetermined manner. A Master Reset latches in
all configuration setup pins and must be performed before programming of the
device can take place.
The multi-queue flow-control devices have the capability of operating its I/O
in either 1.5V HSTL , or 1.8V eHSTL mode. The type of I/O is selected via the
IOSEL input. The core supply voltage (VCC) to the multi-queue is always 1.8V,
however the output levels can be set independently via a separate supply,
VDDQ. The package used will be a 23mm x 23mm, BB-376 BGA package for
better noise immunity and ground bounce prevention.
A JTAG test port is provided, here the multi-queue flow-control device has
a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
5
FEBRUARY 11, 2009
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与IDT72P51777L7-5BBI相近的元器件有：IDT72P51777L7-5BB、IDT72P51767L7-5BB、IDT72P51767L7-5BBI。描述及对比如下：
型号 IDT72P51777L7-5BBI IDT72P51777L7-5BB IDT72P51767L7-5BB IDT72P51767L7-5BBI
描述 FIFO, 256KX40, 3.8ns, Asynchronous, CMOS, PBGA376 FIFO, 256KX40, 3.8ns, Asynchronous, CMOS, PBGA376 FIFO, 128KX40, 3.8ns, Asynchronous, CMOS, PBGA376 FIFO, 128KX40, 3.8ns, Asynchronous, CMOS, PBGA376
是否无铅 含铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合 不符合
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99
最长访问时间 3.8 ns 3.8 ns 3.8 ns 3.8 ns
最大时钟频率 (fCLK) 133 MHz 133 MHz 133 MHz 133 MHz
JESD-30 代码 S-PBGA-B376 S-PBGA-B376 S-PBGA-B376 S-PBGA-B376
JESD-609代码 e0 e0 e0 e0
内存密度 10485760 bit 10485760 bit 5242880 bit 5242880 bit
内存集成电路类型 OTHER FIFO OTHER FIFO OTHER FIFO OTHER FIFO
内存宽度 40 40 40 40
端子数量 376 376 376 376
字数 262144 words 262144 words 131072 words 131072 words
字数代码 256000 256000 128000 128000
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
最高工作温度 85 °C 70 °C 70 °C 85 °C
组织 256KX40 256KX40 128KX40 128KX40
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA BGA BGA BGA
封装等效代码 BGA376,22X22,40 BGA376,22X22,40 BGA376,22X22,40 BGA376,22X22,40
封装形状 SQUARE SQUARE SQUARE SQUARE
封装形式 GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
电源 1.8 V 1.8 V 1.8 V 1.8 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
最大待机电流 0.12 A 0.12 A 0.12 A 0.12 A
最大压摆率 0.2 mA 0.2 mA 0.2 mA 0.2 mA
标称供电电压 (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V
表面贴装 YES YES YES YES
技术 CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 BALL BALL BALL BALL
端子节距 1 mm 1 mm 1 mm 1 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED

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器件捷径:   L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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