Dual Bootstrapped, 12 V MOSFET
Driver with Output Disable
ADP3110
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float
output per Intel® VRM 10 specification
GENERAL DESCRIPTION
The ADP3110 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two
switches in a nonisolated synchronous buck power converter.
Each of the drivers is capable of driving a 3000 pF load with a
25 ns propagation delay and a 30 ns transition time. One of the
drivers can be bootstrapped and is designed to handle the high
voltage slew rate associated with floating high-side gate drivers.
The ADP3110 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3110 is specified over the commercial temperature
range of 0°C to 85°C and is available in an 8-lead SOIC_N
package.
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
12V
VCC
4
D1
ADP3110
BST
1
C
BST2
C
BST1
IN
2
8
DRVH
R
G
Q1
R
BST
DELAY
TO
INDUCTOR
SW
7
CMP
VCC
6
CMP
1V
CONTROL
LOGIC
DRVL
5
Q2
DELAY
OD
3
PGND
05514-001
6
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
ADP3110
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Theory of Operation ........................................................................ 7
Low-Side Driver............................................................................ 7
High-Side Driver .......................................................................... 7
Overlap Protection Circuit...........................................................7
Application Information...................................................................8
Supply Capacitor Selection ..........................................................8
Bootstrap Circuit...........................................................................8
MOSFET Selection........................................................................8
PC Board Layout Considerations................................................9
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
6/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADP3110
SPECIFICATIONS
V
CC
= 12 V, BST = 4 V to 26 V, T
A
= 25°C, unless otherwise noted.
Table 1.
1
Parameter
PWM INPUT
Input Voltage High
2
Input Voltage Low
2
Input Current
2
Hysteresis
2
OD INPUT
Input Voltage High
2
Input Voltage Low
2
Input Current
2
Hysteresis
2
Propagation Delay Times
3
Symbol
Conditions
Min
2.0
−1
90
2.0
−1
90
0.8
+1
250
20
40
3.8
1.4
10
40
30
45
25
10
3.4
1.4
10
40
20
15
30
190
150
35
55
4.4
1.8
55
45
65
35
0.8
+1
250
Typ
Max
Unit
V
V
μA
mV
V
V
μA
mV
ns
ns
Ω
Ω
kΩ
ns
ns
ns
ns
kΩ
Ω
Ω
kΩ
ns
ns
ns
ns
ns
ns
V
mA
V
mV
tpdl
OD
tpdh
OD
See Figure 3
See Figure 3
BST to SW = 12 V
BST to SW = 12 V
BST to SW = 0 V
BST to SW = 12 V, C
LOAD
= 3 nF, see Figure 4
BST to SW = 12 V, C
LOAD
= 3 nF, see Figure 4
BST to SW = 12 V, C
LOAD
= 3 nF,see Figure 4
BST to SW = 12 V, C
LOAD
= 3 nF, see Figure 4
SW to PGND
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times
3
SW Pull Down Resistance
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times
3
Time-out Delay
SUPPLY
Supply Voltage Range
2
Supply Current
2
UVLO Voltage
2
Hysteresis
2
1
2
R
DRV + SW
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
R
SW − PGND
R
DRVL − PGND
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
VCC = PGND
C
LOAD
= 3 nF, see Figure 4
C
LOAD
= 3 nF, see Figure 4
C
LOAD
= 3 nF, see Figure 4
C
LOAD
= 3 nF, see Figure 4
SW = 5 V
SW = PGND
4.0
1.8
50
30
35
40
110
95
4.15
V
CC
I
SYS
BST = 12 V, IN = 0 V
VCC rising
2
1.5
350
13.2
5
3.0
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Specifications apply over the full operating temperature range T
A
= 0°C to 85°C.
3
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
Rev. 0 | Page 3 of 12
ADP3110
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
BST
BST to SW
SW
DC
<200 ns
DRVH
DC
<200 ns
DRVL
DC
<200 ns
IN, OD
θ
JA
, SOIC_N
2-Layer Board
4-Layer Board
Operating Ambient Temperature
Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
–0.3 V to +15 V
–0.3 V to VCC + 15 V
–0.3 V to +15 V
–5 V to +15 V
–10 V to +25 V
SW – 0.3 V to BST + 0.3 V
SW – 2 V to BST + 0.3 V
–0.3 V to VCC + 0.3 V
–2 V to VCC + 0.3 V
–0.3 V to 6.5 V
123°C/W
90°C/W
0°C to 85°C
0°C to 150°C
–65°C to +150°C
300°C
215°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Unless otherwise specified all other voltages
are referenced to PGND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 12
ADP3110
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST
1
IN
2
OD
3
8
DRVH
SW
05514-002
ADP3110
7
6
PGND
TOP VIEW
(Not to Scale)
5
DRVL
VCC
4
Figure 2. 8-Lead SOIC_N Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
BST
IN
OD
VCC
DRVL
PGND
SW
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET’s
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage
to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
8
DRVH
Rev. 0 | Page 5 of 12
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