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M27C256B-12XN1XTR

器件型号:M27C256B-12XN1XTR
器件类别:存储    存储   
厂商名称:ST(意法半导体)
厂商官网:http://www.st.com/
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器件描述

IC,EPROM,32KX8,CMOS,TSSOP,28PIN,PLASTIC

参数
参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称ST(意法半导体)
Reach Compliance Codenot_compliant
最长访问时间120 ns
I/O 类型COMMON
JESD-30 代码R-PDSO-G28
JESD-609代码e0
内存密度262144 bit
内存集成电路类型EEPROM CARD
内存宽度8
端子数量28
字数32768 words
字数代码32000
最高工作温度70 °C
最低工作温度
组织32KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP28,.53,22
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
编程电压2.7 V
最大待机电流0.0001 A
最大压摆率0.03 mA
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.55 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
Base Number Matches1

文档预览

M27C256B
256 Kbit (32Kb x 8) UV EPROM and OTP EPROM
s
5V
±
10% SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME: 45ns
LOW POWER CONSUMPTION:
– Active Current 30mA at 5MHz
– Standby Current 100µA
28
28
s
s
s
s
s
PROGRAMMING VOLTAGE: 12.75V
±
0.25V
PROGRAMMING TIME: 100µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
1
1
FDIP28W (F)
PDIP28 (B)
DESCRIPTION
The M27C256B is a 256 Kbit EPROM offered in
the two ranges UV (ultra violet erase) and OTP
(one time programmable). It is ideally suited for mi-
croprocessor systems and is organized as 32,768
by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C256B is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
PLCC32 (C)
TSOP28 (N)
8 x 13.4 mm
Figure 1. Logic Diagram
VCC
VPP
15
A0-A14
8
Q0-Q7
E
G
M27C256B
VSS
AI00755B
April 2001
1/16
M27C256B
Figure 2A. DIP Connections
Figure 2B. LCC Connections
AI00756
VSS
DU
Q3
Q4
Q5
AI00757
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M27C256B
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A7
A12
VPP
DU
VCC
A14
A13
1 32
A8
A9
A11
NC
G
A10
E
Q7
Q6
9
M27C256B
25
17
Q1
Q2
A0-A14
Q0-Q7
E
G
V
PP
V
CC
V
SS
NC
DU
Figure 2C. TSOP Connections
Table 1. Signal Names
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
Not Connected Internally
Don’t Use
G
A11
A9
A8
A13
A14
VCC
VPP
A12
A7
A6
A5
A4
A3
22
21
28
1
M27C256B
15
14
7
8
AI00614B
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
2/16
M27C256B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V.
E
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
A9
X
X
X
X
X
X
V
ID
V
PP
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
Q7-Q0
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
1
Q6
0
0
Q5
1
0
Q4
0
0
Q3
0
1
Q2
0
1
Q1
0
0
Q0
0
1
Hex Data
20h
8Dh
3/16
M27C256B
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
10ns
0 to 3V
1.5V
Standard
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condit ion
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27C256B are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
els except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27C256B has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C256B has a standby mode which reduc-
es the supply current from 30mA to 100µA. The
M27C256B is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
4/16
M27C256B
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
I
OL
= 2.1mA
I
OH
= –1mA
I
OH
= –100µA
3.6
V
CC
– 0.7V
Test Condition
0V
V
IN
V
CC
0V
V
OUT
V
CC
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
E = V
IH
E > V
CC
– 0.2V
V
PP
= V
CC
–0.3
2
Min
Max
±10
±10
30
1
100
100
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
M27C256B
Symbol
Alt
Parameter
Test Conditio n
-45
(3)
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to
Output Valid
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Output Hi-Z
Output Enable High
to Output Hi-Z
Address Transition to
Output Transition
E = V
IL
, G = V
IL
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
, G = V
IL
0
0
0
Max
45
45
25
25
25
0
0
0
-60
Min
Max
60
60
30
30
30
0
0
0
-70
Min
Max
70
70
35
30
30
0
0
0
-80
Min
Max
80
80
40
30
30
ns
ns
ns
ns
ns
ns
Unit
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is desired from a particular memory de-
vice.
5/16

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