ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16501
18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
•
PI74AVC
+
16501 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
•
True ±24mA Balanced Drive @ 3.3V
•
I
OFF
supports partial Power-down operation
•
3.6V I/O Tolerant inputs and outputs
•
All outputs contain noise reduction circuitry reducing
noise without speed degradation
•
Industrial operation at 40°C to +85°C
•
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC
+
series of logic circuits are
produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74AVC
+
16501 univeral bus transceiver is designed for
1.65V to 3.6V V
CC
operation.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latch Enable (LEAB and LEBA), and CLOCK (CLKAB
and CLKBA) inputs. For A-to-B data flow, the device operates in
the transparent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in the high-
impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
and CLKBA. The Output Enables are complementary (OEAB is
active HIGH and OEBA is active LOW)
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
1
PXXXX
04/24/00
ADVANCE INFORMATION
Product Pin Description
Pin Name
OE
LE
CLK
Ax
Bx
GND
V
CC
Description
Output Enable Input (Active HIGH)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16501
18-Bit Universal Bus Transceiver
Truth Table
(1)
Inputs
OEAB
L
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
H
L
A
X
L
H
L
H
X
X
Output B
Z
L
H
L
H
B0
B0§
Product Pin Configuration
H
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
56-Pin
13
A,K
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑
= LOW-to-HIGH Transition
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB is HIGH
before LEAB goes LOW.
§ Output level before the indicated steady-state input
conditions were established.
2
PXXXX
04/24/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16501
18-Bit Universal Bus Transceiver
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC ............................................................................................
0.5V to +4.6V
Input voltage range, V
I ....................................................................................................
0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, V
O(1) ............................................................
0.5V to +4.6V
Voltage range applied to any output in the
high or low state, V
O(1,2) ........................................................................................
0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................................................ 50mA
Output clamp current, I
OK
(V
O
<0) ...................................................................... 50mA
Continuous output current, I
O ......................................................................................................
±50mA
Continuous current through each V
CC
or GND ................................................. ±100mA
Package thermal impedance,
θ
JA
(3)
: package A .................................................... 64°C/W
package K ................................................... 48°C/W
Storage Temperature range, T
stg ..............................................................................
65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other con-
ditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output current rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
(1)
M in.
V
C C
Supply Voltage
O perating
Data retention only
V
C C
= 1.2V
V
IH
High- level Input Voltage
V
C C
= 1.65V to 1.95V
V
C C
= 2.3V to 2.7V
V
C C
= 3V to 3.6V
V
C C
= 1.2V
V
IL
Low- level Input Voltage
V
C C
= 1.65V to 1.95V
V
C C
= 2.3V to 2.7V
V
C C
= 3V to 3.6V
V
I
V
O
Input Voltage
O utput Voltage
Active State
3- State
V
C C
= 1.65V to 1.95V
I
OH
High- level output current
V
C C
= 2.3V to 2.7V
V
C C
= 3V to 3.6V
V
C C
= 1.65V to 1.95V
I
OL
Low- level output current
V
C C
= 2.3V to 2.7V
V
C C
= 3V to 3.6V
∆t∆
v Input transition rise or fall rate
T
A
O perating free- air temperature
V
C C
= 1.65V to 3.6V
40
0
0
0
1.65
1.2
V
C C
0.65 x V
C C
1.7
2
Gnd
0.35 x V
C C
0.7
0.8
3.6
V
C C
3.6
6
12
24
6
12
24
5
85
ns/V
°C
mA
V
M ax.
3.6
Units
Notes:
1. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
PXXXX
04/24/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16501
18-Bit Universal Bus Transceiver
DC Electrical Characteristics (Over Operating Range, T
A
= 40°C
+85°C)
Parame te rs
I
OH
=
I
OH
=
I
OH
=
I
OH
=
I
OL
=
I
OL
=
I
OL
=
I
OL
=
Control Inputs
Te s t Conditions
(1)
100
µA
6mA
12mA
24mA
100
µA
6mA
12mA
24mA
V
IH
= 1.07V
V
IH
= 1.7V
V
IH
= 2V
V
CC
1.65V to 3.6V
1.65V
2.3V
3V
1.65V to 3.6V
1.65V
2.3V
3V
3.6V
0
3.6V
3.6V
2.5V
3.3V
2.5V
3.3V
2.5V
3.3V
M in.
V
CC
0.2V
1.2
1.75
2.0
0.2
0.45
0.55
0.75
±2.5
±10
±10
40
4
4
6
6
8
8
V
M ax.
Units
V
OH
V
OL
V
IH
= 0.57V
V
IH
= 0.7V
V
IH
= 0.8V
I
I
I
OFF
I
OZ
I
CC
C
I
V
I
= V
CC
or GND
V
I
or V
O
= 3.6V
V
I
= V
CC
or GND
V
O
= V
CC
or GND
V
I
= V
CC
or GND
µA
I
O
= 0
Control Inputs
Data Inputs
C
O
O utputs
V
O
= V
CC
or GND
pF
Note:
Typical values are measured at T
A
= 25°C.
4
PXXXX
04/24/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16501
18-Bit Universal Bus Transceiver
Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
V
CC
= 1.2 V
M in. M ax.
f
clock
Clock Frequency
t
w
Pulse duration
LE High
CLK high or low
Data before CLK
↑
t
su
Setup time
Data before LE
↓
Data before CLK
↑
t
h
Hold tim
ε
Data after LE
↓
CLK High
or Low
CLK High
CLK Low
3
3
1.5
1.5
1.0
0.7
1.4
V
CC
= 1.5V
±0.1V
M in.
M ax.
V
CC
= 1.8V
±0.15V
M in.
M ax.
V
CC
= 2.5V
±0.2V
M in
180
3
3
1.2
1.2
1.0
0.7
1.2
ns
V
CC
= 3.3V
±0.3V
180
Units
MHz
M ax. M in. M ax.
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
f
max
t
pd
t
en
t
dis
t
en
t
dis
From
(Input)
A or B
LE
CLK
OEAB
OEAB
OEBA
OEBA
To
(Output)
B or A
A or B
B
B
A
A
V
CC
= 1.2V
M in.
M ax.
V
CC
= 1.5V
±0.1V
M in. M ax.
V
CC
= 1.8V
±0.15V
M in.
M ax.
V
CC
= 2.5V
±0.2V
M in. M ax.
180
3.9
4.6
4.9
4.6
5.0
5.0
4.2
V
CC
= 3.3V
±0.3V
M in. M ax.
180
2.8
3.3
3.5
3.3
3.7
3.6
3.2
Units
MHz
ns
Operating Characteristics, T
A
= 25°C
Parame te rs
Outputs
Enabled
Outputs
Disabled
Te s t Conditions
Vcc = 1.8V
±0.2V
Typical
Cpd Power
Dissipation
Capacitance
Vcc = 2.5V
±0.2V
Typical
Vcc = 3.3V
±0.3V
Typical
Units
TBD
C
L
= 0pF, f = 10 MHz
TBD
TBD
TBD
pF
TBD
TBD
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5
PXXXX
04/24/00
单片机
京公网安备 11010802033920号
Copyright © 2005-2023 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
