电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索
 

TSPC603RMG10LC

器件型号:TSPC603RMG10LC
器件类别:嵌入式处理器和控制器    微控制器和处理器   
文件大小:674KB,共58页
厂商名称:e2v technologies
下载文档

器件描述

RISC Microprocessor, 32-Bit, 233MHz, CMOS, CBGA255, 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255

参数
参数名称属性值
零件包装代码BGA
包装说明BGA,
针数255
Reach Compliance Codeunknown
ECCN代码3A001.A.2.C
地址总线宽度32
位大小32
边界扫描YES
最大时钟频率233 MHz
外部数据总线宽度64
格式FLOATING POINT
集成缓存YES
JESD-30 代码S-CBGA-B255
长度21 mm
低功率模式YES
端子数量255
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码BGA
封装形状SQUARE
封装形式GRID ARRAY
认证状态Not Qualified
座面最大高度3 mm
速度233 MHz
最大供电电压2.625 V
最小供电电压2.375 V
标称供电电压2.5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式BALL
端子节距1.27 mm
端子位置BOTTOM
宽度21 mm
uPs/uCs/外围集成电路类型MICROPROCESSOR, RISC
Base Number Matches1

文档预览

TSPC603R
PowerPC 603e RISC Microprocessor
Family PID7t-603e
Datasheet
Features
Superscalar (3 Instructions per Clock Peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On-chip Debug Support
Nap, Doze and Sleep Power Saving Modes
Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
P
D
Typically = 3.5W (266 MHz), Full Operating Conditions
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4-Gbytes Direct Addressing Range
Pipelined Single/Double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
f
INT
Max = 300 MHz
f
BUS
Max = 75 MHz
Compatible CMOS Input/TTL Output
Features Specific to Cerquad
5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
P
D
Typically = 2.5W (200 MHz), Full Operating Conditions
Visit our website: www.e2v.com
for the latest version of the datasheet
e2v semiconductors SAS 2011
0841D–HIREL–05/11
TSPC603R
1. Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power imple-
mentation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R
is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements
32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and
64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes.
This device is a superscalar processor capable of issuing and retiring as many as three instructions per
clock. Instructions can be executed in any order for increased performance, but, the 603R makes com-
pletion appear sequential. It integrates five execution units and is able to execute five instructions in
parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed
caches for instructions and data, as well as on-chip instructions, and data Memory Management Units
(MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look
aside buffers that provide support for demand-paged virtual memory address translation and vari-
able-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus.
The interface protocol allows multiple masters to compete for system resources through a central exter-
nal arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports
memory-mapped I/Os.
The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compati-
bility with TTL devices. It also integrates in-system testability and debugging features through JTAG
boundary-scan capabilities.
2. Screening/Quality/Packaging
This product is manufactured in full compliance with:
• HiTCE CBGA according to e2v Standards
• CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to e2v standards
• CBGA 255: Upscreenings based upon e2v standards
• CBGA, CI-CGA, HiTCE packages:
– Full military temperature range (T
C
= -55°C, T
j
= +125°C)
– Industrial temperature range
• Cerquad:
– Full military temperature range (T
C
= -55°C, T
c
= +125°C)
– Industrial temperature range
(T
C
= -40°C, T
c
= +110°C)
– Commercial temperature ranges (
T
C
= 0° C,
T
C
= +70° C)
• Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5%
(T
C
= -40°C, T
j
= +110°C)
2
0841D–HIREL–05/11
e2v semiconductors SAS 2011
TSPC603R
3. Block Diagram
Figure 3-1.
Block Diagram
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b Address
System Bus
64b Data
4. Overview
The 603R is a low-power implementation of the PowerPC microprocessor family of Reduced Instruction
Set Computing (RISC) microprocessors. The 603R implements the 32-bit portion of the PowerPC archi-
tecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and
floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architec-
ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the
64-bit architecture.
The 603R provides four software controllable power-saving modes. Three of the modes (nap, doze, and
sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the 603R to auto-
matically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The 603R is a superscalar processor capable of issuing and retiring as many as three instructions per
clock. Instructions can be executed in any order for increased performance, but, the 603R makes com-
pletion appear sequential.
3
0841D–HIREL–05/11
e2v semiconductors SAS 2011
TSPC603R
The 603e integrates five execution units:
• an Integer Unit (IU)
• a Floating-point Unit (FPU)
• a Branch Processing Unit (BPU)
• a Load/Store Unit (LSU)
• a System Register Unit (SRU)
The ability to execute five instructions in parallel and the use of simple instructions with rapid execution
times yield high efficiency and throughput for 603R-based systems. Most integer instructions execute in
one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every
clock cycle.
The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed
caches for instructions and data, as well as on-chip instruction and data Memory Management Units
(MMUs). The MMUs contain 64-entry, two-way set-associative, Data and Instruction Translation Looka-
side Buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation
and variable-sized block translation. The TLBs and caches use a Least Recently Used (LRU) replace-
ment algorithm. The 603R also supports block address translation through the use of two independent
Instruction and Data Block Address Translation (IBAT and DBAT) arrays of four entries each. Effective
addresses are compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array,
the BAT translation has priority.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface protocol
allows multiple masters to compete for system resources through a central external arbiter. The 603R
provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache
states. This protocol is a compatible subset of the MESI (Modified/Exclusive/Shared/Invalid) four-state
protocol and operates coherently in systems that contain four-state caches. The 603R supports sin-
gle-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains full inter-
face compatibility with TTL devices.
4
0841D–HIREL–05/11
e2v semiconductors SAS 2011
TSPC603R
5. Signal Description
Figure 5-1, Table 10-5
and
Table 10-6 on page 21
describe the signals on the TSPC603R and indicate
signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with the subset P-1149.1 of
the IEEE testability bus standard.
The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and
must be pulled up to V
DD
for normal machine operations.
Figure 5-1.
Functional Signal Groups
BR
ADDRESS
ARBITRATION
BG
ABB
1
1
1
1
1
1
DBG
DBWO
DBB
DATA
ATTRIBUTION
ADDRESS
START
TS
1
64
8
DH[0-31], DL[0-31]
DP[0-7]
DPE
DBDIS
TA
DR TR Y
TEA
INT, SMI
MCP
CKSTP_IN, CKSTP_OUT
HRESET, SRESET
RSRV
QREQ, QACK
TBEN
TLBISYNC
PROCESSOR
STATUS
INTERRUPTS
CHECKSTOPS
RESET
DATA
TERMINATION
DATA
TRANSFER
A[0-31]
ADDRESS
BUS
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
TRANSFER
ATTRIBUTE
CI
WT
CSE[0-1]
TC[0-1]
32
4
1
5
1
3
1
1
1
2
2
603r
1
1
1
1
1
2
1
2
2
1
2
1
ADDRESS
TERMINATION
AACK
ARTRY
1
1
1
5
TRST, TCK, TMS, TDI, TD0
LSSD_MODE
L1_TSTCLK, L2_TSTCLK
VDD
OVDD
GND
AVDD
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
SYSCLK
CLOCKS
CLK_OUT
PLL_CFG[0-3]
POWER SUPPLY
INDICATOR
VOLTDETGND
1
1
4
20
1
19
40
1
3
POWER SUPPLY
5
0841D–HIREL–05/11
e2v semiconductors SAS 2011
今年嵌入式的工作真难找啊。。。。。应届毕业生进来聊聊
我是应届毕业的小硕,单片机,ARM,DSP都做过应用,能设计原理图,也能做简单的板子,linux,ucos也都会,有公司实习,项目的经验,但是今年到现在找不到工作....投出去20多份简历,只有一份有回应,而且还是要做软件的。。。。郁闷...
lihui19850618 嵌入式系统
救火车和你一起学ARM系列活动
救火车和你一起学ARMi活动到此已近尾声了。在此我感谢电子工程世界的工作人员和广大的电子同行们对我们的支持。...
小志 活动列表
在虚拟机xp系统里面安装winCE4.2开发环境卡在一半了
输入序列号之后,点下一步,出现一对话框“disk space requirements”说可能持续1分钟,就卡在这一部了。我怀疑它检测的是真实硬盘 而不是虚拟机里面的磁盘。该咋办?...
smset WindowsCE
散分,公司项目流产,失业了
如T,才进去两个月,晕死了.说是有新项目招进去的,结果外包...
lxg69 嵌入式系统
为什么我的windows mobile的手机安装了一个IURamFlagLTk.cap.pkg(是一个更新程序)后,手机不能启动
为什么我的windows mobile的手机安装了一个IURamFlagLTk.cap.pkg(是一个更新程序)后,手机不能启动,重新刷机后还是不能启动。。。现在想恢复到以前状态都不行了~~~~...
nuaajiang 嵌入式系统
哪位强人能详细解释一下这个电路,做毕业论文啊.谢谢
邮箱dgy5482615@163.com...
someday 电源技术

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2023 EEWORLD.com.cn, Inc. All rights reserved