MX29LV400C T/B
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
•
Fully compatible with MX29LV400T/B device
• Fast access time: 55R/70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP (6 x 8mm)
- 48-ball CSP (4 x 6mm)
-
All Pb-free devices are RoHS Compliant
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX29LV400C T/B is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV400C T/B is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV400C T/B offers access time as
fast as 55ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV400C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV400C T/B uses a command register to manage
this functionality. The command register allows for 100%
P/N:PM1155
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV400C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
REV. 1.5, APR. 24, 2006
1
MX29LV400C T/B
PIN CONFIGURATIONS
44 SOP(500 mil)
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
PIN DESCRIPTION
SYMBOL
A0~A17
Q0~Q14
Q15/A-1
CE#
WE#
BYTE#
RESET#
OE#
RY/BY#
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15 (Word mode)/LSB addr(Byte mode)
Chip Enable Input
Write Enable Input
Word/Byte Selection input
Hardware Reset Pin/Sector Protect
Unlock
Output Enable Input
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
Pin Not Connected Internally
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
MX29LV400C T/B
MX29LV400C T/B
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REV. 1.5, APR. 24, 2006
2
MX29LV400C T/B
48-Ball CSP (Ball Pitch = 0.8 mm, Top View, Balls Facing Down, 6 x 8 mm)
6
A13
A12
A14
A15
A16
BYTE#
Q15/
A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RE-
SET#
NC
NC
Q5
Q12
VCC
Q4
3
RY/
BY#
A7
NC
NC
NC
Q2
Q10
Q11
Q3
2
A17
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE#
OE#
GND
A
B
C
D
E
F
G
H
48-Ball CSP (Balls Facing Down, 4 x 6 mm)
6
A2
A4
A6
A17
NC
NC
WE#
NC
A9
A11
5
A1
A3
A7
NC
NC
A10
A13
A14
4
A0
A5
A18
A8
A12
A15
3
CE#
Q8
Q10
Q4
Q11
A16
2
GND
OE#
Q9
NC
NC
Q5
Q6
Q7
1
Q0
Q1
Q2
Q3
VCC
Q12
Q13
Q14
Q15
GND
A
B
C
D
E
F
G
H
J
K
L
P/N:PM1155
REV. 1.5, APR. 24, 2006
3
MX29LV400C T/B
BLOCK STRUCTURE
Table 1: MX29LV400CT SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode Word Mode
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
32Kbytes
8Kbytes
8Kbytes
16Kbytes
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
16Kwords
4Kwords
4Kwords
8Kwords
Address range
Byte Mode (x8)
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-77FFF
78000-79FFF
7A000-7BFFF
7C000-7FFFF
Word Mode (x16)
00000-07FFF
08000-0FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3BFFF
3C000-3CFFF
3D000-3DFFF
3E000-3FFFF
A17 A16
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
Sector Address
A15
0
1
0
1
0
1
0
1
1
1
1
A14
X
X
X
X
X
X
X
0
1
1
1
A13
X
X
X
X
X
X
X
X
0
0
1
A12
X
X
X
X
X
X
X
X
0
1
X
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
Table 2: MX29LV400CB SECTOR ARCHITECTURE
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
Sector Size
Byte Mode Word Mode
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
8Kwords
4Kwords
4Kwords
16Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
32Kwords
Address range
Byte Mode (x8)
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
Word Mode (x16)
00000-01FFF
02000-02FFF
03000-03FFF
04000-07FFF
08000-0FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3FFFF
A17 A16
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
Sector Address
A15
0
0
0
0
1
0
1
0
1
0
1
A14
0
0
0
1
X
X
X
X
X
X
X
A13
0
1
1
X
X
X
X
X
X
X
X
A12
X
0
1
X
X
X
X
X
X
X
X
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
P/N:PM1155
REV. 1.5, APR. 24, 2006
4
MX29LV400C T/B
BLOCK DIAGRAM
CE#
OE#
WE#
RESET#
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
X-DECODER
ADDRESS
LATCH
A0-A17
AND
BUFFER
COMMAND
DATA
DECODER
Y-DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM1155
REV. 1.5, APR. 24, 2006
5
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