电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

SIT9120AI-1D1-XXE166.666666Y

产品描述-40 TO 85C, 7050, 20PPM, 2.25V-3
产品类别无源元件   
文件大小480KB,共13页
制造商SiTime
标准
下载文档 详细参数

SIT9120AI-1D1-XXE166.666666Y概述

-40 TO 85C, 7050, 20PPM, 2.25V-3

SIT9120AI-1D1-XXE166.666666Y规格参数

参数名称属性值
安装类型表面贴装
封装/外壳6-SMD,无引线
大小/尺寸0.276" 长 x 0.197" 宽(7.00mm x 5.00mm)
高度 - 安装(最大值)0.039"(1.00mm)

文档预览

下载PDF文档
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
31 standard frequencies from 25 MHz to 212.5 MHz
LVPECL and LVDS output signaling types
0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For any other frequencies between 1 to 625 MHz, refer to SiT9121
and SiT9122 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, servers
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Symbol
Vdd
Min.
2.97
2.25
2.25
Output Frequency Range
Frequency Stability
f
F_stab
25
-10
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Start-up Time
Resume Time
Duty Cycle
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
T_start
T_resume
DC
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
-2
-5
-40
-20
70%
2
45
Vdd-1.1
Vdd-1.9
1.2
Typ.
3.3
2.5
100
6
6
61
1.6
300
1.2
1.2
1.2
0.6
Max.
3.63
2.75
3.63
212.5
+10
+20
+25
+50
+2
+5
+85
+70
30%
250
10
10
55
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.85
Unit
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
ms
ms
%
mA
mA
A
A
mA
V
V
V
ps
ns
ps
ps
ps
ps
25°C
25°C
Industrial
Extended Commercial
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time ST pin crosses
50% threshold.
Contact SiTime for tighter duty cycle
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
See Figure 2
Termination schemes in Figures 1 and 2 - XX ordering code
See last page for list of standard frequencies
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
Condition
LVPECL and LVDS, Common Electrical Characteristics
LVPECL, DC and AC Characteristics
RMS Phase Jitter (random)
T_phj
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
250
47
350
55
35
450
mA
mA
mV
SiTime Corporation
Rev. 1.06
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 3, 2014

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 399  914  1300  1389  1635 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved