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ATV750L

器件型号:ATV750L
厂商名称:Atmel (Microchip)
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器件描述

High Density UV Erasable Programmable Logic Device

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Features
Third Generation Programmable Logic Structure
– High-Density Replacement for Discrete Logic
High-Speed — Plus a New, Low-Power Version
Increased Logic Flexibility
– 42 Inputs and 20 Sum Terms
Flexible Output Logic
– 20 Flip-Flops - 10 Extra
– All Can Be Individually Buried or 10 Output Directly
– Each has Individual Asynchronous Reset and Clock Terms
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Proven and Reliable High-Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
Reprogrammable
– Tested 100% for Programmability
24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages
High Density UV
Erasable
Programmable
Logic Device
ATV750
ATV750L
Logic Diagram
Description
The ATV750(L) is 100% more powerful than most other programmable logic devices
in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into
more usable gates.
Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these
can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed
back into the array independently. This flexibility allows burying all of the sum terms
and flip-flops.
There are 171 product terms available. A variable format is used to assign between
four and eight product terms per sum term. There are two sum terms per output, pro-
viding added flexibility.
(continued)
Pin Configurations
Pin Name
IN
I/O
*
VCC
Function
Logic Inputs
Bidirectional Buffers
No Internal Connection
+5V Supply
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC/LCC
(Top View)
IN
IN
IN
*
VCC
I/O
I/O
4
3
2
1
28
27
26
IN
IN
IN
*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
*
I/O
I/O
I/O
IN
IN
GND
*
IN
I/O
I/O
12
13
14
15
16
17
18
Rev. 0024E–05/98
1
The ATV750(L) has more flip-flops available than other
PLDs in this density range. Complex state machines are
easily implemented.
Product terms are available providing asynchronous
resets, flip-flop clocks, and output enables. One reset and
one clock term are provided per flip-flop, with one enable
term per output. One product term provides a global syn-
chronous preset. Register preload simplifies testing. The
device has an internal power up clear function.
Absolute Maximum Ratings
Temperature Under Bias............................... -55°C to + 125°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Note:
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Integrated UV Erase Dose.............................. 7258 W.sec/cm
2
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is Vcc + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Logic Options
Combined Terms
Separate Terms
Combined Terms
Separate Terms
Output Options
2
ATV750/L
ATV750/L
DC and AC Operating Conditions
ATV750-20
Com.
Operating Temperature (Case)
Ind.
Mil.
V
CC
Power Supply
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V
±
10%
ATV750/750L-25
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V
±
10%
DC Characteristics
Symbol
I
LI
I
LO
Parameter
Input Load
Current
Output Leakage
Current
Condition
V
IN
= -0.1V to V
CC
+ 1V
V
OUT
= -0.1V to V
CC
+ 0.1V
Com.
I
CC
Power Supply
Current
V
CC
= MAX,
V
IN
= GND,
Outputs Open
ATV750
Ind.,Mil.
Com.
ATV750L
Ind.,Mil.
I
OS(1)
V
IL
V
IH
Output Short Circuit Current
Input Low Voltage
Input High Voltage
I
OL
= 12 mA Com.,Ind.
V
OL
Output Low Voltage
V
IN
= V
IH
or V
IL
,
V
CC
= MIN
V
IN
= V
IH
or V
IL
,
V
CC
= MIN
I
OL
= 8 mA Mil.
I
OL
= 24 mA, Com.
V
OH
Note:
Output High Voltage
I
OH
= -100
µ
A
I
OH
= -4.0 mA
V
CC
- 0.3
2.4
V
OUT
= 0.5V
-0.6
2.0
1.0
15
-120
0.8
V
CC
+
0.75
0.5
0.5
1.0
mA
mA
V
V
V
V
V
V
V
1.0
140
12
mA
mA
Min
Typ
Max
10
10
120
Units
µA
µA
mA
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
AC Waveforms
(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
4
ATV750/L
ATV750/L
AC Characteristics
ATV750-20
Symbol
t
PD
t
EA
t
ER
t
CO
t
CF
t
S
t
SF
t
H
t
P
t
W
F
MAX
t
AW
t
AR
t
AP
t
SP
Parameter
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Clock to Output
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
Clock Period
Clock Width
Maximum Frequency
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Asynchronous Reset to Registered Output Reset
Setup Time, Synchronous Preset
12
15
15
20
15
5
10
5
5
18
8
55
20
20
25
Min
Max
20
20
20
20
10
5
12
7
5
22
10
45
ATV750/750L-25
Min
Max
25
25
25
22
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
Input Test Waveforms and
Measurement Levels
Output Test Loads
t
R
, t
F
< 5 ns (10% to 90%)
5

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