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CY7C4425-25JI

器件型号:CY7C4425-25JI
文件大小:410KB,共25页
厂商名称:Cypress(赛普拉斯)
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器件描述

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

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CY7C4425/4205/4215
CY7C4225/4235/4245
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64 x 18 (CY7C4425)
• 256 x 18 (CY7C4205)
• 512 x 18 (CY7C4215)
• 1K x 18 (CY7C4225)
• 2K x 18 (CY7C4235)
• 4K x 18 (CY7C4245)
• High-speed 100-MHz operation (10 ns read/write cycle
time)
• Low power (I
CC
=45 mA)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and Programmable Almost
Empty/Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP
• 68-pin PLCC
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI and RXI pins of the
first device. The FL pin of the first device is tied to V
SS
and the
FL pin of all the remaining devices should be tied to V
CC
.
The CY7C42X5 provides five status pins. These pins are de-
coded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see
Table 2).
The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to V
SS
. All configurations are fabricated
using an advanced 0.65µ N-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is prevent-
ed by the use of guard rings.
Functional Description
T
he CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to
IDT722x5. The CY7C42X5 can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134 •
408-943-2600
April 1995 - Revised August 18, 1997
CY7C4425/4205/4215
CY7C4225/4235/4245
Logic Block Diagram
D
0 – 17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
DUAL PORT
RAM ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–ST
ATE
OUTPUT REGISTER
READ
CONTROL
OE
42X5–1
Q
0 – 17
RCLK
REN
Pin Configurations
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
/SMODE
PLCC
Top View
RCLK
REN
LD
OE
RS
GND
GND
GND
Q
15
V
CC
V
CC
Q
17
Q
16
D
16
D
17
GND
RCLK
TQFP
Top View
D
15
D
16
D
17
9 8 7
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
6 5
4
3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
/SMODE
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
EF
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
2728 2930 3132 33 34 35 36 37 38 3940
PAE
FL/RT
WEN
WXI
PAF
RXI
FF
WXO/HF
RXO
WCLK
GND
V
CC
Q
0
Q
1
4142 43
V
CC
Q
2
Q
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FL/RT
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
PAE
Q
0
Q
1
GND
Q
2
42x5–2
2
Q
3
42X5–3
CY7C4425/4205/4215
CY7C4225/4235/4245
Selection Guide
CY7C42X5-10
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial
Industrial
CY7C4205
256 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
100
8
10
3
0.5
8
45
50
CY7C4215
512 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C42X5-15
66.7
10
15
4
1
10
45
50
CY7C4225
1K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C42X5-25
40
15
25
6
1
15
45
50
CY7C4235
2K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C42X5-35
28.6
20
35
7
2
20
45
50
CY7C4245
4K x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
CY7C4425
Density
Packages
64 x 18
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name
D
0–17
Q
0–17
WEN
REN
WCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I/O
I
O
I
I
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0–17
(O
0–17
) are written (read) into (from) the programma-
ble-flag-offset register.
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
Function
RCLK
Read Clock
I
WXO/HF
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
O
EF
FF
PAE
O
O
O
PAF
O
LD
FL/RT
I
I
WXI
Write Expansion
Input
I
3
CY7C4425/4205/4215
CY7C4225/4235/4245
Pin Definitions
(continued)
Signal Name
RXI
RXO
RS
OE
V
CC
/SMODE
Description
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
I/O
I
O
I
I
I
Function
Cascaded - Connected to RXO of previous device.
Not Cascaded - Tied to V
SS
.
Cascaded - Connected to RXI of next device.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags - tied to V
CC
.
Synchronous Almost Empty/Almost Full flags - tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
....................................−65
°
C to +150
°
C
Ambient Temperature with
Power Applied
.................................................−55
°
C to +125
°
C
Supply Voltage to Ground Potential..................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................−0.5V
to +7.0V
DC Input Voltage
.................................................−3.0V
to +7.0V
Operating Range
Range
Commercial
Industrial
[1]
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
7C42X5-10
Parameter
V
OH
V
OL
V
IH[3]
V
IL[3]
I
IX
I
OS[4]
I
OZL
I
OZH
I
CC2[5]
I
SB[6]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Output OFF,
High Z Current
Operating Current
Standby Current
V
CC
= Max.
V
CC
= Max.,
V
OUT
= GND
OE > V
IH
,
V
SS
< V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Ind
Com’l
Ind
Test Conditions
V
CC
= Min.,
I
OH
=
−2.0
mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
−3.0
−10
−90
−10
+10
45
50
10
15
Min.
2.4
0.4
V
CC
0.8
+10
2.2
−3.0
−10
−90
−10
+10
45
50
10
15
Max.
7C42X5-15
Min.
2.4
0.4
V
CC
0.8
+10
2.2
−3.0
−10
−90
−10
+10
45
50
10
15
Max.
7C42X5-25
Min.
2.4
0.4
V
CC
0.8
+10
2.2
−3.0
−10
−90
−10
+10
45
50
10
15
Max.
7C42X5-35
Min.
2.4
0.4
V
CC
0.8
+10
Max.
Unit
V
V
V
V
µA
mA
µA
mA
mA
mA
mA
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The V
IH
and V
IL
specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or V
SS
.
4. Test no more than one output at a time for not more than one second.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to V
CC
. All outputs are unloaded.
4
CY7C4425/4205/4215
CY7C4225/4235/4245
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
5
7
Unit
pF
pF
AC Test Loads and Waveforms
[8, 9]
R11.1K
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉ
EVENIN
OUTPUT
EQUIVALENT
410Ω
1.91V
R2
680Ω
3.0V
GND
< 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 3 ns
42X5–5
42X5–4
Switching Characteristics
Over the Operating Range
7C42X5-10
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSR
t
RSF
t
PRT
t
RTR
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[10]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z
[11]
Output Enable to Output Valid
Output Enable to Output in High Z
[11]
Write Clock to Full Flag
Read Clock to Empty Flag
12
12
0
3
3
7
7
8
8
2
10
4.5
4.5
3
0.5
3
0.5
10
8
10
15
15
0
3
3
8
8
10
10
Min.
Max.
100
8
2
15
6
6
4
1
4
1
15
10
15
25
25
0
3
3
12
12
15
15
7C42X5-15
Min.
Max.
66.7
10
2
25
10
10
6
1
6
1
25
15
25
35
35
0
3
3
15
15
20
20
7C42X5-25
Min.
Max.
40
15
2
35
14
14
7
2
7
2
35
20
35
7C42X5-35
Min.
Max. Unit
28.6
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. Tested initially and after any design or process changes that may affect these parameters.
8. C
L
= 30 pF for all AC parameters except for t
OHZ
.
9. C
L
= 5 pF for t
OHZ
.
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
5

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