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570AAA000112DG

器件型号:570AAA000112DG
器件类别:无源元件   
厂商名称:Silicon Laboratories
标准:
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器件描述

Programmable Oscillators PROGRAMABLE XO 0.3ps RMS JTR NCNR

参数
参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
Silicon Laboratories
产品种类
Product Category
Programmable Oscillators
RoHSDetails
频率
Frequency
10 MHz to 1417.5 MHz
频率稳定性
Frequency Stability
50 PPM
负载电容
Load Capacitance
15 pF
工作电源电压
Operating Supply Voltage
3.3 V
电源电压-最小
Supply Voltage - Min
2.97 V
电源电压-最大
Supply Voltage - Max
3.63 V
Output FormatLVPECL
产品
Product
XO
端接类型
Termination Style
SMD/SMT
封装 / 箱体
Package / Case
5 mm x 7 mm
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
长度
Length
7 mm
宽度
Width
5 mm
高度
Height
1.65 mm
系列
Packaging
Tray
电流额定值
Current Rating
120 mA
类型
Type
I2C Programmable
占空比 - 最大
Duty Cycle - Max
55 %
安装风格
Mounting Style
SMD/SMT
工厂包装数量
Factory Pack Quantity
50
单位重量
Unit Weight
0.006562 oz

文档预览

Si 5 7 0 / S i 5 7 1
10 MH
Z TO
1.4 G H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Features
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
Ordering Information:
SONET/SDH
xDSL
10 GbE LAN/WAN
ATE
High performance
instrumentation
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 32.
Pin Assignments:
See page 31.
(Top View)
SDA
7
NC
1
6
V
DD
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-
programmable to any output frequency from 10 to 945 MHz and select frequencies
to 1400 MHz with <1 ppb resolution. The device is programmed via an I
2
C serial
interface. Unlike traditional XO/VCXOs where a different crystal is required for
each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL
clock synthesis IC to provide any-frequency operation. This IC-based approach
allows the crystal resonator to provide exceptional frequency stability and
reliability. In addition, DSPLL clock synthesis provides superior supply noise
rejection, simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems.
OE
2
5
CLK–
GND
3
8
SCL
4
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
7
OE
Fixed
Frequency
XO
10-1400 MHz
DSPLL Clock
Synthesis
V
C
1
6
V
DD
SDA
SCL
OE
2
5
CLK–
Si571 only
ADC
GND
3
8
SCL
4
CLK+
GND
V
C
Si571
Si570/Si571
Rev. 1.5 4/14
Copyright © 2014 by Silicon Laboratories
Si570/Si571
2
Rev. 1.5
Si570/Si571
T
ABLE O F
C
ONTENTS
Section
Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. Si570 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3. Si570 Troubleshooting FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Rev. 1.5
3
Si570/Si571
1. Detailed Block Diagrams
V
DD
GND
f
XTAL
+
RFREQ
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
Frequency
Control
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 1. Si570 Detailed Block Diagram
V
DD
GND
f
XTAL
V
C
ADC
VCADC
+
RFREQ
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
Frequency
Control
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 2. Si571 Detailed Block Diagram
4
Rev. 1.5
Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V option
Supply Voltage
1
V
DD
2.5 V option
1.8 V option
Output enabled
LVPECL
CML
LVDS
CMOS
TriState mode
Output Enable (OE)
2
,
Serial Data (SDA),
Serial Clock (SCL)
Operating Temperature Range
T
A
V
IH
V
IL
2.97
2.25
1.71
0.75 x V
DD
–40
3.3
2.5
1.8
120
108
99
90
60
3.63
2.75
1.89
130
117
108
98
75
0.5
85
V
ºC
V
Supply Current
I
DD
mA
Notes:
1.
Selectable parameter specified by part number. See Section "7. Ordering Information" on page 32 for further details.
2.
OE pin includes a 17 k pullup resistor to V
DD
. See “7.Ordering Information”.
Table 2. V
C
Control Voltage Input (Si571)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Control Voltage Tuning Slope
1,2,3
K
V
V
C
10 to 90% of V
DD
33
45
90
135
180
356
±1
±5
10.0
V
DD
/2
ppm/V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
Nominal Control Voltage
5
Control Voltage Tuning Range
L
VC
BW
Z
VC
V
CNOM
V
C
BSL
Incremental
–5
–10
9.3
500
+5
+10
10.7
V
DD
%
kHz
k
V
V
@ f
O
0
Notes:
1.
Positive slope; selectable option by part number. See "7. Ordering Information" on page 32.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±10% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope is
determined with V
C
ranging from 10 to 90% of V
DD
.
5.
Nominal output frequency set by V
CNOM
= 1/2 x V
DD
.
Rev. 1.5
5
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