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SIT9120AC-2D2-33S212.500000

器件型号:SIT9120AC-2D2-33S212.500000
器件类别:无源元件    振荡器   
文件大小:419KB,共11页
厂商名称:SiTime
标准:
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器件描述

LVDS Output Clock Oscillator, 25MHz Min, 212.5MHz Max, 212.5MHz Nom, CMOS,

参数
参数名称属性值
是否Rohs认证符合
厂商名称SiTime
Reach Compliance Codecompliant
其他特性STANDBY; ENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT
最长下降时间0.6 ns
频率调整-机械NO
频率稳定性25%
JESD-609代码e4
安装特点SURFACE MOUNT
端子数量6
标称工作频率212.5 MHz
最高工作温度70 °C
最低工作温度-20 °C
振荡器类型LVDS
输出负载100 OHM
封装主体材料PLASTIC
封装等效代码DILCC6,.2
物理尺寸7mm x 5mm x 0.9mm
电源3.3 V
认证状态Not Qualified
最长上升时间0.6 ns
最大压摆率55 mA
最大供电电压3.63 V
最小供电电压2.97 V
标称供电电压3.3 V
表面贴装YES
最大对称度55/45 %
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches1

文档预览

SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Features
31 standard frequencies from 25 MHz to 212.5 MHz
LVPECL and LVDS output signaling types
0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±20 PPM
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For any other frequencies between 1 to 625 MHz, refer to SiT9121
and SiT9122 datasheet
Applications
10GB Ethernet, SONET, Synchronous Ethernet, SATA, SAS,
Fibre Channel, PCI-Express
Telecom, networking, broadband, instrumentation
Electrical Characteristics
Parameter and Conditions
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
25
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Start-up Time
Resume Time
Duty Cycle
F_aging1
F_aging10
T_use
T_start
T_resume
DC
Vdd
Supply Voltage
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
-2
-5
-40
-20
45
2.97
2.25
2.25
Vdd-1.1
Vdd-1.9
1.2
Typ.
6
6
3.3
2.5
61
1.6
300
1.2
1.2
1.2
0.6
Max.
212.5
+20
+25
+50
+2
+5
+85
+70
10
10
55
3.63
2.75
3.63
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
500
115
1.7
1.7
1.7
0.85
Unit
MHz
PPM
PPM
PPM
PPM
PPM
°C
°C
ms
ms
%
V
V
V
mA
mA
μA
μA
mA
V
V
V
ps
ns
ps
ps
ps
ps
Termination schemes in Figures 1 and 2 - XX ordering code
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1
See Figure 1
See Figure 1
20% to 80%
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
See last page for list of standard frequencies
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
25°C
25°C
Industrial
Extended Commercial
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time ST pin crosses
50% threshold.
Contact SiTime for tighter duty cycle
LVPECL and LVDS, Common AC Characteristics
LVPECL, DC and AC Characteristics
RMS Phase Jitter (random)
T_phj
LVDS, DC and AC Characteristics
Vdd
Supply Voltage
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Differential Output Voltage
Idd
I_OE
I_leak
I_std
VOD
2.97
2.25
2.25
200
3.3
2.5
47
350
3.63
2.75
3.63
55
35
1
100
500
V
V
V
mA
mA
μA
μA
mV
Contact SiTime for 1.8V option
XX ordering code
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
See Figure 4
SiTime Corporation
Rev. 1.01
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised Feb 20, 2013
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Electrical Characteristics
(continued)
Parameter and Conditions
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Symbol
ΔVOD
VOS
ΔVOS
Tr, Tf
T_oe
T_jitt
Min.
1.125
Typ.
1.2
495
1.2
1.2
1.2
0.6
Max.
50
1.375
50
600
115
1.7
1.7
1.7
0.85
Unit
mV
V
mV
ps
ns
ps
ps
ps
ps
See Figure 4
See Figure 4
See Figure 4
20% to 80%
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
RMS Phase Jitter (random)
T_phj
Pin Description
Pin
Map
OE
1
ST
Input
Input
Functionality
H or Open: specified frequency output
L: output is high impedance
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to
I_std.
Not Connect; Leave it floating or connect to GND for
better heat dissipation
VDD Power Supply Ground
Oscillator output
Complementary oscillator output
Power supply voltage
Top View
OE/ST
1
NC
2
GND
3
6
VDD
OUT-
OUT+
5
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
NA
Power
Output
Output
Power
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge (HBM)
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
Max.
150
4
2000
260
Unit
°C
V
V
°C
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 2 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Termination Diagrams
LVPECL:
VDD
OUT+
D riv e D ev ice
OUT-
Z 0 = 50
Ω
50
Ω
50
Ω
Z 0 = 50
Ω
D+
Receiver Device
D-
V T T = V D D – 2.0 V
Figure 1. LVPECL Typical Termination
VDD
OUT+
Drive Device
VDD= 3.3V => R1 = 100 to 150
Ω
VDD= 2.5V => R1 = 75
Ω
100 nF
D+
Receiver Device
100 nF
Z0 = 50
Ω
OUT-
R1
R1
Z0 = 50
Ω
50
Ω
50
Ω
D-
VTT
Figure 2. LVPECL AC Coupled Termination
VDD = 3.3V => R1 = R3 = 133
Ω
and
R2 = R4 = 82
Ω
VDD = 2.5V => R1 = R3 = 250
Ω
and
R2 = R4 = 62.5
Ω
VDD
OUT+
Drive Device
OUT-
Z0 = 50
Ω
R2
R4
D-
Z0 = 50
Ω
VDD
R1
R3
D+
Receiver
Device
Figure 3. LVPECL with Thevenin Typical Termination
Rev. 1.01
Page 3 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
LVDS:
VDD
OUT+
Drive Device
OUT-
Z0 = 50
Ω
100
Ω
Z0 = 50
Ω
D+
Receiver Device
D-
Figure 4. LVDS Single Termination (Load Terminated)
Rev. 1.01
Page 4 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[1]
3.2 x 2.5x 0.75 mm
Recommended Land Pattern (Unit: mm)
[2]
3.2±0.05
#6
#5
#4
#4
2.20
#5
#6
2 .2 5
2.5±0.05
0.7
1.6
YXXXX
0.9
#1
#2
#3
#3
#2
#1
0.6
0.75±0.05
0 .6 5
1 .0 5
5.0 x 3.2 x 0.75 mm
#6
#5
#4
#4
#5
#6
YXXXX
#1
#2
#3
#3
#2
#1
0.75±0.05
7.0 x 5.0x 0.90 mm
7.0±0.10
#6
#5
#4
#4
1.20
5.08
#5
#6
5.08
5.0±0.10
2.60
#1
#2
#3
#3
#2
#1
3.80
YXXXX
1.10
1.40
0.90 ±0.10
1.60
1. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
2. A capacitor of value 0.1
μF
between Vdd and GND is recommended.
Rev. 1.01
Page 5 of 6
1.60
1.00
www.sitime.com

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