Termination schemes in Figures 1 and 2 - XX ordering code
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1
See Figure 1
See Figure 1
20% to 80%
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
See last page for list of standard frequencies
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
25°C
25°C
Industrial
Extended Commercial
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time ST pin crosses
50% threshold.
Contact SiTime for tighter duty cycle
LVPECL and LVDS, Common AC Characteristics
LVPECL, DC and AC Characteristics
RMS Phase Jitter (random)
T_phj
LVDS, DC and AC Characteristics
Vdd
Supply Voltage
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Differential Output Voltage
Idd
I_OE
I_leak
I_std
VOD
2.97
2.25
2.25
–
–
–
–
200
3.3
2.5
–
47
–
–
–
350
3.63
2.75
3.63
55
35
1
100
500
V
V
V
mA
mA
μA
μA
mV
Contact SiTime for 1.8V option
XX ordering code
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST = Low, for all Vdds
See Figure 4
SiTime Corporation
Rev. 1.01
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised Feb 20, 2013
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Electrical Characteristics
(continued)
Parameter and Conditions
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Symbol
ΔVOD
VOS
ΔVOS
Tr, Tf
T_oe
T_jitt
Min.
–
1.125
–
–
–
–
–
–
–
Typ.
–
1.2
–
495
–
1.2
1.2
1.2
0.6
Max.
50
1.375
50
600
115
1.7
1.7
1.7
0.85
Unit
mV
V
mV
ps
ns
ps
ps
ps
ps
See Figure 4
See Figure 4
See Figure 4
20% to 80%
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Condition
RMS Phase Jitter (random)
T_phj
Pin Description
Pin
Map
OE
1
ST
Input
Input
Functionality
H or Open: specified frequency output
L: output is high impedance
H or Open: specified frequency output
L: Device goes to sleep mode. Supply current reduces to
I_std.
Not Connect; Leave it floating or connect to GND for
better heat dissipation
VDD Power Supply Ground
Oscillator output
Complementary oscillator output
Power supply voltage
Top View
OE/ST
1
NC
2
GND
3
6
VDD
OUT-
OUT+
5
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
NA
Power
Output
Output
Power
4
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge (HBM)
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 2 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Termination Diagrams
LVPECL:
VDD
OUT+
D riv e D ev ice
OUT-
Z 0 = 50
Ω
50
Ω
50
Ω
Z 0 = 50
Ω
D+
Receiver Device
D-
V T T = V D D – 2.0 V
Figure 1. LVPECL Typical Termination
VDD
OUT+
Drive Device
VDD= 3.3V => R1 = 100 to 150
Ω
VDD= 2.5V => R1 = 75
Ω
100 nF
D+
Receiver Device
100 nF
Z0 = 50
Ω
OUT-
R1
R1
Z0 = 50
Ω
50
Ω
50
Ω
D-
VTT
Figure 2. LVPECL AC Coupled Termination
VDD = 3.3V => R1 = R3 = 133
Ω
and
R2 = R4 = 82
Ω
VDD = 2.5V => R1 = R3 = 250
Ω
and
R2 = R4 = 62.5
Ω
VDD
OUT+
Drive Device
OUT-
Z0 = 50
Ω
R2
R4
D-
Z0 = 50
Ω
VDD
R1
R3
D+
Receiver
Device
Figure 3. LVPECL with Thevenin Typical Termination
Rev. 1.01
Page 3 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
LVDS:
VDD
OUT+
Drive Device
OUT-
Z0 = 50
Ω
100
Ω
Z0 = 50
Ω
D+
Receiver Device
D-
Figure 4. LVDS Single Termination (Load Terminated)
Rev. 1.01
Page 4 of 6
www.sitime.com
SiT9120
Standard Frequency Differential Oscillator
The Smart Timing Choice™
The Smart Timing Choice™
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[1]
3.2 x 2.5x 0.75 mm
Recommended Land Pattern (Unit: mm)
[2]
3.2±0.05
#6
#5
#4
#4
2.20
#5
#6
2 .2 5
2.5±0.05
0.7
1.6
YXXXX
0.9
#1
#2
#3
#3
#2
#1
0.6
0.75±0.05
0 .6 5
1 .0 5
5.0 x 3.2 x 0.75 mm
#6
#5
#4
#4
#5
#6
YXXXX
#1
#2
#3
#3
#2
#1
0.75±0.05
7.0 x 5.0x 0.90 mm
7.0±0.10
#6
#5
#4
#4
1.20
5.08
#5
#6
5.08
5.0±0.10
2.60
#1
#2
#3
#3
#2
#1
3.80
YXXXX
1.10
1.40
0.90 ±0.10
1.60
1. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
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