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M27C801-60B1TR

器件型号:M27C801-60B1TR
器件类别:存储    存储   
文件大小:127KB,共16页
厂商名称:ST(意法半导体)
厂商官网:http://www.st.com/
标准:
下载文档

器件描述

1M X 8 UVPROM, 80 ns, CDIP32

1M × 8 UVPROM, 80 ns, CDIP32

参数
参数名称属性值
是否Rohs认证符合
厂商名称ST(意法半导体)
零件包装代码DIP
包装说明0.600 INCH, LEAD FREE, PLASTIC, DIP-32
针数32
Reach Compliance Codecompli
ECCN代码EAR99
最长访问时间60 ns
JESD-30 代码R-PDIP-T32
JESD-609代码e3
长度42.035 mm
内存密度8388608 bi
内存集成电路类型OTP ROM
内存宽度8
功能数量1
端子数量32
字数1048576 words
字数代码1000000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织1MX8
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
认证状态Not Qualified
座面最大高度4.83 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层Tin (Sn)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度15.24 mm

文档预览

M27C801
8 Mbit (1Mb x 8) UV EPROM and OTP EPROM
s
5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
ACCESS TIME: 45ns
LOW POWER CONSUMPTION:
– Active Current 35mA at 5MHz
– Standby Current 100µA
1
32
s
s
32
1
s
s
s
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIME: 50µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 42h
FDIP32W (F)
PDIP32 (B)
DESCRIPTION
The M27C801 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for applica-
tions where fast turn-around and pattern experi-
mentation are important requirements and is
organized as 1,048,576 by 8 bits.
The FDIP32W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C801 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
Figure 1. Logic Diagram
VCC
20
A0-A19
8
Q0-Q7
E
GVPP
M27C801
VSS
AI01267
September 2000
1/16
M27C801
Figure 2A. DIP Connections
Figure 2B. PLCC Connections
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
32
1
31
2
30
3
29
4
28
5
27
6
26
7
25
8
M27C801
24
9
23
10
22
11
21
12
20
13
19
14
18
15
17
16
AI01268
VCC
A18
A17
A14
A13
A8
A9
A11
GVPP
A10
E
Q7
Q6
Q5
Q4
Q3
A12
A15
A16
A19
VCC
A18
A17
1 32
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
A9
A11
GVPP
A10
E
Q7
9
M27C801
25
17
Q1
Q2
VSS
Q3
Q4
Q5
Q6
AI01814
Figure 2C. TSOP Connections
Table 1. Signal Names
A0-A19
Q0-Q7
Address Inputs
Data Outputs
Chip Enable
Output Enable / Program Supply
Supply Voltage
Ground
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
A4
1
32
8
9
M27C801
(Normal)
25
24
16
17
AI01269
GVPP
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
E
GV
PP
V
CC
V
SS
2/16
M27C801
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V ± 0.5V.
E
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IL
GV
pp
V
IL
V
IH
V
PP
V
PP
X
V
IL
A9
X
X
X
X
X
V
ID
Q7-Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
0
Q6
0
1
Q5
1
0
Q4
0
0
Q3
0
0
Q2
0
0
Q1
0
1
Q0
0
0
Hex Data
20h
42h
3/16
M27C801
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
10ns
0 to 3V
1.5V
Standard
20ns (10% to 90%)
0.4 to 2.4V
0.8 and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27C801 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for GV
PP
and 12V on A9 for Elec-
tronic Signature and Margin Mode Set or Reset.
Read Mode
The M27C801 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27C801 has a standby mode which reduces
the supply current from 35mA to 100µA.
The M27C801 is placed in the standby mode by
applying a CMOS high signal to the E input. When
in the standby mode, the outputs are in a high im-
pedance state, independent of the GV
PP
input.
4/16
M27C801
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 5V ± 10%)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Output High Voltage CMOS
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
I
OL
= 2.1mA
I
OH
= –1mA
I
OH
= –100µA
3.6
V
CC
– 0.7
Test Condition
0V
V
IN
V
CC
0V
V
OUT
V
CC
E = V
IL
, GV
PP
= V
IL
,
I
OUT
= 0mA, f = 5MHz
E = V
IH
E > V
CC
– 0.2V
V
PP
= V
CC
–0.3
2
Min
Max
±10
±10
35
1
100
10
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 5V ± 10%)
M27C801
Symbol
Alt
Parameter
Test
Condition
-45
(3)
Min
t
AVQV
t
ELQV
t
GLQV
t
EHQZ (2)
t
GHQZ (2)
t
AXQX
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
E = V
IL
,
GV
PP
= V
IL
GV
PP
= V
IL
E = V
IL
GV
PP
= V
IL
E = V
IL
E = V
IL
,
GV
PP
= V
IL
0
0
0
Max
45
45
25
25
25
0
0
0
Min
-60
Max
60
60
30
25
25
0
0
0
Min
-70
Max
70
70
35
30
30
ns
ns
ns
ns
ns
ns
Unit
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
5/16
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