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Z86L73

器件型号:Z86L73
厂商名称:Zilog, Inc.
厂商官网:https://www.zilog.com/
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器件描述

INFRARED REMOTE CONTROLLERS

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CP95LVO0801  
PRELIMINARY  
CUSTOMER PROCUREMENT SPECIFICATION  
Z86E73/E74 32K OTP  
Z86L73/L74 32K ROM  
INFRARED REMOTE CONTROLLERS  
FEATURES  
ROM  
RAM*  
One-Time  
Speed  
Expanded Register Files (ERF)  
Part  
(Kbyte) (Kbyte) Programmable (MHz)  
Z86E73  
Z86L73  
Z86E74  
Z86L74  
32  
32  
32  
32  
1004  
492  
1004  
1004  
Yes  
No  
Yes  
No  
8
8
8
8
31 Input/Output Lines (E73/L73)  
51 Input/Output Lines (E74/L74*)  
*Note: With Auto Latch on Port 4, 5 and 6.  
*
General-Purpose  
Five Prioritized Interrupts with Programmable Polarity  
Two Comparators  
40-Pin DIP, 44-Pin PLCC/QFP Packages (E73/L73)  
4-Pin DIP, 68-Pin PLCC Packages (E74/L74)  
6
8-Bit Counter/Timer with Two Capture Registers and  
16-Bit Counter/Timer with One Capture Register  
2.0V to 3.9V Operating Range (L73/L74)  
.5V to 5.5V Operating Range (E73/E74)  
4
Watch-Dog Timer (WDT)/Power-On Reset (POR)  
Low-Power Consumption  
(
(
Typical: 40 mw for L73/L74)  
Typical: 60 mw for E73/E74)  
On-Chip Oscillator that Accepts a Crystal, Ceramic  
Resonator, LC, RC, or External Clock Drive  
0°C to +70°C Temperature Range  
Low-Voltage Detection and Protection  
32-KHz Mask Option to Disable Internal Feedback  
Resistor (L73/L74)  
GENERAL DESCRIPTION  
The Z86E73/L73/E74/L74 are ROM-based members of  
Zilog's Z8 single-chip microcontroller family of infrared  
Two on-chip counter/timers, with a large number of  
selectable modes, offload the system of administering  
re a l-time ta s ks s uc h a s c ounting /timing a nd I/O  
datacommunications.  
®
(IR) consumer controller processors featuring fast and  
flexible code execution. The Z86E73/E74 devices offer a  
one-time programmable (OTP) option.  
Notes:  
For applications demanding powerful I/O capabilities, the  
Z86E73/L73's dedicated inputand outputlines are grouped  
into four ports, and into seven ports for the Z86E74/L74.  
They are configurable under software control to provide  
timing, status signals, or parallel I/O.  
All Signals with a preceding front slash, "/", are active Low, e.g.,  
B//W (WORD is active Low); /B/W (BYTE is active Low, only).  
Power connections follow conventional descriptions below:  
Connection  
Circuit  
Device  
Power  
Ground  
V
GND  
V
Four address spaces, the Program Memory, Register File,  
Data Memory, and Expanded Register File (ERF) support  
a wide range of memory configurations. Through the ERF  
the designerhas access to three additionalcontrolregisters  
thatprovide extra peripheraldevices, I/O ports, and register  
addresses.  
CC  
DD  
V
SS  
CP95LVO0801  
1
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
GENERAL DESCRIPTION (Continued)  
P00  
P01  
P02  
P03  
Register File  
512 or 1K x 8-bit  
P31  
P32  
P33  
4
4
Port 0  
Port 1  
Port 2  
Port 3  
P34  
P35  
P36  
P37  
P04  
P05  
P06  
P07  
Register Bus  
ROM  
Internal  
Address Bus  
Z8 Core  
16K/32K x 8  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
P17  
Internal Data Bus  
XTAL  
/AS  
8
Machine  
Timing  
&
Instruction  
Control  
Extended  
Register Bus  
Extended  
Register  
File  
/
DS  
R/W  
RESET  
/
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
VDD  
VSS  
Power  
Counter/Timer 8  
Counter/Timer 16  
16-Bit  
8
-Bit  
I/O Bit  
Programmable  
Port 4  
Port 5  
Port 6  
8
Z86E74/L74  
version only  
8
4
Functional Block Diagram  
2
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
PIN DESCRIPTION  
P56  
1
64  
R//RL  
P54  
P53  
/DS  
R//W  
P25  
P26  
P27  
P04  
P05  
P06  
1
2
3
4
5
6
7
8
9
40  
39  
38  
/DS  
R/W  
P25  
P26  
2
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
P24  
P23  
P22  
P21  
P20  
P03  
P13  
P12  
VSS  
P02  
P11  
3
4
37  
36  
35  
34  
P27  
P04  
P05  
P06  
P14  
P15  
P07  
VDD  
VDD  
P40  
P41  
P42  
P43  
P44  
P45  
P16  
P17  
XTAL2  
XTAL1  
P31  
P32  
P33  
P34  
P60  
P61  
5
P51  
P50  
P24  
P23  
P22  
P21  
P20  
P03  
P13  
P12  
VSS  
VSS  
P52  
P57  
P02  
P46  
P47  
P11  
6
7
8
9
P14  
P15  
33  
32  
31  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Z86E73/L73  
DIP  
P07  
10  
11  
3
0
9
VDD  
P16  
2
12  
13  
14  
15  
16  
17  
18  
19  
P17  
28  
27  
P10  
P01  
P00  
Pref1  
P36  
P37  
P35  
/RESET  
Z86E74/L74  
DIP  
XTAL2  
26  
25  
24  
XTAL1  
P31  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
P32  
P33  
23  
P10  
P01  
P00  
PREF1  
P36  
P37  
P35  
/RESET  
VSS  
P62  
2
2
1
P34  
2
2
0
/
AS  
Z86E73 (Standard Mode)  
Z86L73 40-Pin DIP  
Pin Assignments  
/
AS  
P63  
P55  
Z86E74 (Standard Mode)  
Z86L74 64-Pin DIP  
Pin Assignments  
3
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
PIN DESCRIPTION  
6
5
4
3
2
1 44 43 42 41 40  
P21  
P22  
P23  
P24  
7
39  
38  
37  
36  
35  
34  
33  
Pref1  
P36  
8
9
P37  
10  
11  
12  
13  
14  
15  
16  
17  
P35  
/
DS  
/RESET  
VSS  
/AS  
Z86E73/L73  
PLCC  
R//RL  
R//W  
P25  
32  
31  
30  
29  
P34  
P26  
P33  
P32  
P31  
P27  
P04  
18 19 20 21 22 23 24 25 26 27 28  
Z86E73 (Standard Mode)  
Z86L73 44-Pin PLCC  
Pin Assignments  
33 32 31 30 29 28 27 26 25 24 23  
P21  
P22  
P23  
P24  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
2
2
2
1
1
1
1
1
1
1
1
2
Pref1  
1
0
9
8
7
6
5
4
3
2
P36  
P37  
P35  
/
DS  
/RESET  
VSS  
/AS  
Z86E73/L73  
QFP  
R//RL  
R//W  
P25  
P34  
P26  
P33  
P27  
P32  
P04  
P31  
1
2 3 4 5 6 7 8 9 10 11  
Z86E73 (Standard Mode)  
Z86L73 44-Pin QFP  
Pin Assignments  
4
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
PIN DESCRIPTION (Continued)  
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61  
P21  
P22  
P23  
P24  
P50  
P51  
10  
11  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
PREF1  
P36  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
P37  
P35  
/RESET  
VSS  
P62  
/
DS  
P53  
P54  
P55  
Z86E74/L74  
PLCC  
N/C  
R//RL  
P56  
P63  
/AS  
P61  
P60  
P34  
P33  
P32  
P31  
R//W  
N/C  
P25  
P26  
P27  
P04  
27  
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
Z86E74 (Standard Mode)  
Z86L74 68-Pin PLCC Pin Assignments  
5
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
ABSOLUTE MAXIMUM RATINGS  
Stresses greater than those listed under Absolute Maxi-  
mum Ratings may cause permanent damage to the de-  
vice. This is a stress rating only; operation of the device at  
any condition above those indicated in the operational  
sections of these specifications is not implied. Exposure to  
absolute maximum rating conditions for an extended  
period may affect device reliability.  
Symbol Description  
Supply Voltage (*)  
Min  
Max  
Units  
V
–0.3  
–65°  
+7.0  
+150°  
V
C
C
CC  
TSTG  
TA  
Storage Temp.  
Oper. Ambient Temp.  
Notes:  
*
Voltage on all pins with respect to GND.  
See Ordering Information.  
STANDARD TEST CONDITIONS  
The characteristics listed below apply for standard test  
conditions as noted. All voltages are referenced to GND.  
Positive current flows into the referenced pin (Test Load).  
From Output  
Under Test  
I
150 pF  
Test Load Diagram  
CAPACITANCE  
T = 25°C, V = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.  
A
CC  
Parameter  
Max  
Input capacitance  
Output capacitance  
I/O capacitance  
12 pF  
12 pF  
12 pF  
6
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
DC CHARACTERISTICS (Z86E73/E74)  
T = 0°C to +70°C Typ @  
A
Sym Parameter  
VCC  
Min  
Max  
25°C  
Units  
Conditions  
Notes [3]  
Max Input Voltage  
4.0V  
7
7
V
V
V
I 250 µA  
IN  
5.5V  
I 250 µA  
IN  
V
Clock Input  
High Voltage  
4.0V  
0.9 V  
V + 0.3  
Driven by External  
Clock Generator  
Driven by External  
Clock Generator  
CH  
CC  
CC  
5.5V  
0.9 V  
V + 0.3  
V
CC  
CC  
V
Clock Input  
Low Voltage  
40V  
.5V  
V – 0.3  
0.2 V  
V
V
Driven by External  
Clock Generator  
Driven by External  
Clock Generator  
CL  
SS  
CC  
5
V – 0.3  
0.2 V  
SS  
CC  
V
Input High Voltage  
Input Low Voltage  
4.0V  
.5V  
4.0V  
.5V  
0.7 V  
V + 0.3  
1.3  
2.5  
0.5  
0.9  
V
V
V
V
IH  
CC  
CC  
5
0.7 V  
V + 0.3  
CC  
CC  
V
V – 0.3  
0.2 V  
IL  
SS  
CC  
5
V – 0.3  
0.2 V  
SS  
CC  
V
Output High Voltage  
Output High Voltage  
4.0V  
.5V  
4.0V  
5.5V  
V – 0.4  
1.7  
3.7  
V
V
V
V
I = –0.5 mA  
OH1  
CC  
OH  
5
V – 0.4  
I = –0.5 mA  
CC  
OH  
V
0.7  
0.7  
I = –7 mA  
[10]  
[10]  
OH2  
OH  
(P36, P37)  
I ,= –7 mA  
OH  
V
Output Low Voltage  
Output Low Voltage  
4.0V  
0.4  
0.4  
0.8  
0.2  
0.1  
0.3  
V
V
V
I = 1.0 mA  
OL1  
OL  
5.5V  
I = 4.0 mA  
OL  
V
4.0V  
I = 2.0 mA  
OL2  
OL  
3
Pin Max  
5
.5V  
0.8  
0.8  
0.8  
0.5  
0.3  
0.5  
V
V
V
I = 8.0 mA  
OL  
3
Pin Max  
V
Output Low Voltage  
4.0V  
5.5V  
I = 10 mA  
[9]  
[9]  
OL2  
OL  
(P20-P22, P36,  
P00, P01, P07)  
I = 10 mA  
OL  
2
O/P only  
V
Reset Input  
High Voltage  
Reset Input  
Low Voltage  
Comparator Input  
Offset Voltage  
4.0V  
5.5V  
4.0V  
5.5V  
4.0V  
5.5V  
0.8 V  
V
1.5  
3.0  
0.5  
0.9  
10  
V
V
RH  
CC  
CC  
0.8 V  
V
CC  
CC  
V
V – 0.3  
0.2 V  
0.2 V  
25  
25  
Rl  
SS  
CC  
V – 0.3  
SS  
CC  
V
mV  
mV  
OFFSET  
10  
I
Input Leakage  
4.0V  
–1  
–1  
–1  
–1  
1
1
1
1
< 1  
< 1  
< 1  
< 1  
µA  
µA  
µA  
µA  
V = OV, V  
IL  
IN  
CC  
5
.5V  
4.0V  
.5V  
V = OV, V  
IN  
CC  
I
Output Leakage  
V = OV, V  
OL  
IN  
CC  
5
V = OV, V  
IN  
CC  
I
Reset Input Current  
Supply Current  
4.0V  
.5V  
4.0V  
.5V  
.0V  
.5V  
–45  
–55  
10  
15  
100  
300  
–20  
–30  
4
10  
10  
10  
µA  
µA  
mA  
mA  
µA  
µA  
IR  
5
I
@ 8.0 MHz  
@ 8.0 MHz  
@ 32 kHz  
@ 32 kHz  
[4, 5]  
[4, 5]  
[4, 5,11]  
[4, 5,11]  
CC  
5
4
5
7
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
DC CHARACTERISTICS (Z86E73/E74) (Continued)  
T = 0°C to +70°C Typ @  
A
Sym Parameter  
Standby Current  
VCC  
Min  
Max  
25°C  
Units  
Conditions  
Notes [3]  
I
4.0V  
3
1
mA  
HALT Mode  
V = OV, V  
[4,5]  
CC1  
IN  
CC  
@
8.0 MHz  
5.5V  
5
4
mA  
HALT Mode  
V = OV, V  
[4,5]  
IN  
CC  
@
8.0 MHz  
4
.0V  
2
4
0.8  
2.5  
mA  
mA  
Clock Divide-by-16  
8.0 MHz  
Clock Divide-by-16  
8.0 MHz  
[4,5]  
[4,5]  
@
5.5V  
@
I
Standby Current  
4.0V  
8
2
µA  
µA  
µA  
µA  
STOP Mode  
V = OV, V  
WDT is not Running  
[6,8]  
[6,8]  
[6,8]  
[6,8]  
CC2  
IN  
CC  
5.5V  
10  
3
STOP Mode  
V = OV, V  
IN  
CC  
WDT is not Running  
STOP Mode  
4.0V  
500  
800  
310  
600  
V = OV, V  
IN  
CC  
WDT is Running  
STOP Mode  
V = OV, V  
5.5V  
IN  
CC  
WDT is Running  
T
Power-On Reset  
4.0V  
.5V  
15  
5
75  
20  
3.3  
13  
7
2.75  
ms  
ms  
V
POR  
5
V
V Low Voltage Protection  
8 MHz max  
[7]  
LV  
CC  
Ext. CLK Freq.  
Notes:  
[1] ICC1  
Typ  
Max  
Unit  
Frequency  
Crystal/Resonator  
External Clock Drive  
3.0 mA  
0.3 mA  
5
5
mA  
mA  
8.0 MHz  
8.0 MHz  
[
[
[
[
[
[
[
[
[
[
2] GND = 0V.  
3] 4.0V to 5.5V.  
4] All outputs unloaded, I/O pins floating, inputs at rail.  
5] CL1 = CL2 = 100 pF.  
6] Same as note [4] except inputs at VCC.  
7] The V increases as the temperature decreases.  
LV  
8] Oscillator stopped.  
9] Two outputs at a time, independent to other outputs.  
10] One at a time.  
11] 32 kHz clock driver input.  
8
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
DC CHARACTERISTICS (Z86L73/L74)  
T = 0°C to +70°C Typ @  
A
Sym Parameter  
VCC  
Min  
Max  
25°C  
Units  
Conditions  
Notes [3]  
Max Input Voltage  
2.0V  
7
7
V
V
V
I 250 µA  
IN  
3.9V  
I 250 µA  
IN  
V
Clock Input  
High Voltage  
2.0V  
0.9 V  
V + 0.3  
Driven by External  
Clock Generator  
Driven by External  
Clock Generator  
CH  
CC  
CC  
3.9V  
0.9 V  
V + 0.3  
V
CC  
CC  
V
Clock Input  
Low Voltage  
2.0V  
.9V  
V – 0.3  
0.2 V  
V
V
Driven by External  
Clock Generator  
Driven by External  
Clock Generator  
CL  
SS  
CC  
3
V – 0.3  
0.2 V  
SS  
CC  
V
Input High Voltage  
Input Low Voltage  
2.0V  
.9V  
2.0V  
.9V  
0.7 V  
V + 0.3  
1.3  
2.5  
0.5  
0.9  
V
V
V
V
IH  
CC  
CC  
3
0.7 V  
V + 0.3  
CC  
CC  
V
V – 0.3  
0.2 V  
IL  
SS  
CC  
3
V – 0.3  
0.2 V  
SS  
CC  
V
Output High Voltage  
Output High Voltage  
2.0V  
.9V  
2.0V  
3.9V  
V – 0.4  
1.7  
3.7  
V
V
V
V
I = –0.5 mA  
OH1  
CC  
OH  
3
V – 0.4  
I = –0.5 mA  
CC  
OH  
V
0.7  
0.7  
I = –7 mA  
[10]  
[10]  
OH2  
OH  
(P36, P37)  
I ,= –7 mA  
OH  
V
Output Low Voltage  
Output Low Voltage  
2.0V  
0.4  
0.4  
0.8  
0.2  
0.1  
0.3  
V
V
V
I = 1.0 mA  
OL1  
OL  
3.9V  
I = 4.0 mA  
OL  
V
2.0V  
I = 2.0 mA  
OL2  
OL  
3
Pin Max  
3
.9V  
0.8  
0.8  
0.8  
0.5  
0.3  
0.5  
V
V
V
I = 8.0 mA  
OL  
3
Pin Max  
V
Output Low Voltage  
2.0V  
3.9V  
I = 10 mA  
[9]  
[9]  
OL2  
OL  
(P20-P22, P36,  
P00, P01, P07)  
I = 10 mA  
OL  
2
O/P only  
V
Reset Input  
High Voltage  
Reset Input  
Low Voltage  
Comparator Input  
Offset Voltage  
2.0V  
3.9V  
2.0V  
3.9V  
2.0V  
3.9V  
0.8 V  
V
1.5  
3.0  
0.5  
0.9  
10  
V
V
RH  
CC  
CC  
0.8 V  
V
CC  
CC  
V
V – 0.3  
0.2 V  
0.2 V  
25  
25  
Rl  
SS  
CC  
V – 0.3  
SS  
CC  
V
mV  
mV  
OFFSET  
10  
I
Input Leakage  
2.0V  
–1  
2.0V  
–1  
1
–1  
–1  
1
< 1  
1
< 1  
µA  
< 1  
< 1  
µA  
V = OV, V  
V = OV, V  
IL  
IN  
CC  
3.9V  
IN  
CC  
I
Output Leakage  
µA  
µA  
V = OV, V  
OL  
IN  
CC  
3.9V  
1
V = OV, V  
IN  
CC  
I
Reset Input Current  
Supply Current  
2.0V  
–45  
–55  
10  
15  
100  
300  
–20  
–30  
4
10  
10  
10  
µA  
µA  
mA  
mA  
µA  
µA  
IR  
3
.9V  
2.0V  
.9V  
.0V  
.9V  
I
@ 8.0 MHz  
@ 8.0 MHz  
@ 32 kHz  
@ 32 kHz  
[4, 5]  
[4, 5]  
[4, 5,11]  
[4, 5,11]  
CC  
3
2
3
9
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
DC CHARACTERISTICS (Z86L73/L74) (Continued)  
T = 0°C to +70°C Typ @  
A
Sym Parameter  
Standby Current  
VCC  
Min  
Max  
25°C  
Units  
Conditions  
Notes [3]  
I
2.0V  
3
1
mA  
HALT Mode  
V = OV, V  
[4,5]  
CC1  
IN  
CC  
@
8.0 MHz  
3.9V  
5
4
mA  
HALT Mode  
V = OV, V  
[4,5]  
IN  
CC  
@
8.0 MHz  
2
.0V  
2
4
0.8  
2.5  
mA  
mA  
Clock Divide-by-16  
8.0 MHz  
Clock Divide-by-16  
8.0 MHz  
[4,5]  
[4,5]  
@
3.9V  
@
I
Standby Current  
2.0V  
8
2
µA  
µA  
µA  
µA  
STOP Mode  
V = OV, V  
WDT is not Running  
[6,8]  
[6,8]  
[6,8]  
[6,8]  
CC2  
IN  
CC  
3.9V  
10  
3
STOP Mode  
V = OV, V  
IN  
CC  
WDT is not Running  
STOP Mode  
2.0V  
500  
800  
310  
600  
V = OV, V  
IN  
CC  
WDT is Running  
STOP Mode  
V = OV, V  
3.9V  
IN  
CC  
WDT is Running  
T
Power-On Reset  
2.0V  
.9V  
15  
5
75  
20  
2.15  
13  
7
1.7  
ms  
ms  
V
POR  
3
V
V Low Voltage Protection  
8 MHz max  
[7]  
LV  
CC  
Ext. CLK Freq.  
Notes:  
1] ICC1  
Crystal/Resonator  
External Clock Drive  
2] GND = 0V.  
3] 2.0V to 3.9V.  
4] All outputs unloaded, I/O pins floating, inputs at rail.  
5] CL1 = CL2 = 100 pF.  
6] Same as note [4] except inputs at VCC.  
[
Typ  
Max  
Unit  
Frequency  
3.0 mA  
0.3 mA  
5
5
mA  
mA  
8.0 MHz  
8.0 MHz  
[
[
[
[
[
[
[
[
[
[
7] The V increases as the temperature decreases.  
LV  
8] Oscillator stopped.  
9] Two outputs at a time, independent to other outputs.  
10] One at a time.  
11] 32 kHz clock driver input.  
10  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS  
External I/O or Memory Read and Write Timing Diagram  
R//W  
1
3
12  
19  
Port 0, /DM  
16  
20  
8
3
Port 1  
A7 - A0  
D7 - D0 IN  
1
2
9
/
AS  
8
11  
4
5
6
/
DS  
(
Read)  
17  
10  
Port 1  
A7 - A0  
D7 - D0 OUT  
14  
15  
7
/
DS  
(
Write)  
External I/O or Memory Read/Write Timing  
11  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86E73/E74)  
External I/O or Memory Read and Write Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
CC  
No.  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Units  
Notes  
1
TdA(AS)  
Address Valid to  
4.0V  
5.5V  
2.0V  
5.5V  
55  
55  
70  
70  
ns  
ns  
ns  
ns  
[2]  
/
AS Rising Delay  
2
TdAS(A)  
/AS Rising to Address  
Float Delay  
[2]  
3
4
TdAS(DR)  
TwAS  
/AS Rising to Read  
Data Required Valid  
/AS Low Width  
4.0V  
5.5V  
4.0V  
400  
400  
ns  
ns  
ns  
ns  
[1, 2]  
[2]  
80  
80  
5.5V  
5
6
Td  
Address Float to  
4.0V  
5.5V  
4.0V  
0
0
300  
300  
ns  
ns  
ns  
ns  
/
DS Falling  
TwDSR  
/DS (Read) Low Width  
[1, 2]  
5.5V  
7
8
TwDSW  
/DS (Write) Low Width  
4.0V  
165  
165  
ns  
ns  
ns  
ns  
[1, 2]  
[1, 2]  
5.5V  
TdDSR(DR)  
/DS Falling to Read  
Data Required Valid  
4.0V  
5.5V  
260  
260  
9
ThDR(DS)  
TdDS(A)  
Read Data to  
4.0V  
5.5V  
4.0V  
5.5V  
0
0
85  
95  
ns  
ns  
ns  
ns  
[2]  
[2]  
/
DS Rising Hold Time  
10  
/DS Rising to Address  
Active Delay  
1
1
TdDS(AS)  
/DS Rising to /AS  
Falling Delay  
R//W Valid to /AS  
Rising Delay  
4.0V  
5.5V  
4.0V  
5.5V  
60  
70  
70  
70  
ns  
ns  
ns  
ns  
[2]  
[2]  
12  
TdR/W(AS)  
1
3
TdDS(R/W)  
/DS Rising to  
R//W Not Valid  
Write Data Valid to /DS  
Falling (Write) Delay  
4.0V  
5.5V  
4.0V  
5.5V  
70  
70  
80  
80  
ns  
ns  
ns  
ns  
[2]  
[2]  
14  
TdDW(DSW)  
1
5
TdDS(DW)  
TdA(DR)  
/DS Rising to Write  
Data Not Valid Delay  
Address Valid to Read  
Data Required Valid  
4.0V  
5.5V  
4.0V  
5.5V  
70  
80  
ns  
ns  
ns  
ns  
[2]  
16  
475  
475  
[1, 2]  
1
7
TdAS(DS)  
TdDM(AS)  
/AS Rising to  
4.0V  
5.5V  
4.0V  
5.5V  
100  
100  
55  
ns  
ns  
ns  
ns  
[2]  
[2]  
/
DS Falling Delay  
18  
/DM Valid to /AS  
Falling Delay  
55  
1
9
TdDS(DM)  
ThDS(A)  
/DS Rise to  
4.0V  
5.5V  
4.0V  
5.5V  
70  
70  
70  
70  
ns  
ns  
ns  
ns  
/
DM Valid Delay  
20  
/DS Rise to Address  
Valid Hold Time  
Notes:  
[1] When using extended memory timing add 2 TpC.  
[2] Timing numbers given are for minimum TpC.  
[3] 4.0V to 5.5V.  
Standard Test Load.  
All timing references use 0.9 V for a logic 1 and 0.1 V for a logic 0.  
CC  
CC  
12  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86L73/L74)  
External I/O or Memory Read and Write Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
CC  
No.  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Units  
Notes  
1
TdA(AS)  
Address Valid to  
2.0V  
3.9V  
2.0V  
3.9V  
55  
55  
70  
70  
ns  
ns  
ns  
ns  
[2]  
/
AS Rising Delay  
2
TdAS(A)  
/AS Rising to Address  
Float Delay  
[2]  
3
4
TdAS(DR)  
TwAS  
/AS Rising to Read  
Data Required Valid  
/AS Low Width  
2.0V  
3.9V  
2.0V  
400  
400  
ns  
ns  
ns  
ns  
[1, 2]  
[2]  
80  
80  
3.9V  
5
6
Td  
Address Float to  
2.0V  
3.9V  
2.0V  
0
0
300  
300  
ns  
ns  
ns  
ns  
/
DS Falling  
TwDSR  
/DS (Read) Low Width  
[1, 2]  
3.9V  
7
8
TwDSW  
/DS (Write) Low Width  
2.0V  
165  
165  
ns  
ns  
ns  
ns  
[1, 2]  
[1, 2]  
3.9V  
TdDSR(DR)  
/DS Falling to Read  
Data Required Valid  
2.0V  
3.9V  
260  
260  
9
ThDR(DS)  
TdDS(A)  
Read Data to  
2.0V  
3.9V  
2.0V  
3.9V  
0
0
85  
95  
ns  
ns  
ns  
ns  
[2]  
[2]  
/
DS Rising Hold Time  
10  
/DS Rising to Address  
Active Delay  
1
1
TdDS(AS)  
/DS Rising to /AS  
Falling Delay  
R//W Valid to /AS  
Rising Delay  
2.0V  
3.9V  
2.0V  
3.9V  
60  
70  
70  
70  
ns  
ns  
ns  
ns  
[2]  
[2]  
12  
TdR/W(AS)  
1
3
TdDS(R/W)  
/DS Rising to  
R//W Not Valid  
Write Data Valid to /DS  
Falling (Write) Delay  
2.0V  
3.9V  
2.0V  
3.9V  
70  
70  
80  
80  
ns  
ns  
ns  
ns  
[2]  
[2]  
14  
TdDW(DSW)  
1
5
TdDS(DW)  
TdA(DR)  
/DS Rising to Write  
Data Not Valid Delay  
Address Valid to Read  
Data Required Valid  
2.0V  
3.9V  
2.0V  
3.9V  
70  
80  
ns  
ns  
ns  
ns  
[2]  
16  
475  
475  
[1, 2]  
1
7
TdAS(DS)  
TdDM(AS)  
/AS Rising to  
2.0V  
3.9V  
2.0V  
3.9V  
100  
100  
55  
ns  
ns  
ns  
ns  
[2]  
[2]  
/
DS Falling Delay  
18  
/DM Valid to /AS  
Falling Delay  
55  
1
9
TdDS(DM)  
ThDS(A)  
/DS Rise to  
2.0V  
3.9V  
2.0V  
3.9V  
70  
70  
70  
70  
ns  
ns  
ns  
ns  
/
DM Valid Delay  
20  
/DS Rise to Address  
Valid Hold Time  
Notes:  
[1] When using extended memory timing add 2 TpC.  
[2] Timing numbers given are for minimum TpC.  
[3] 2.0V to 3.9V.  
Standard Test Load.  
All timing references use 0.9 V for a logic 1 and 0.1 V for a logic 0.  
CC  
CC  
13  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS  
Additional Timing Diagram  
1
3
Clock  
2
2
3
7
7
T
IN  
4
5
6
IRQ  
N
8
9
Clock  
Setup  
11  
Stop  
Mode  
Recovery  
Source  
10  
Additional Timing  
14  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86E73/E74)  
Additional Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
CC  
No  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Units  
Notes  
1
TpC  
Input Clock Period  
4.0V  
121  
121  
DC  
DC  
25  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1]  
[1]  
5.5V  
2
TrC,TfC  
Clock Input Rise  
and Fall Times  
4.0V  
5.5V  
25  
3
4
TwC  
Input Clock Width  
4.0V  
37  
37  
100  
70  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1]  
[1]  
5.5V  
TwTinL  
Timer Input  
Low Width  
4.0V  
5.5V  
5
6
TwTinH  
TpTin  
Timer Input  
High Width  
Timer Input Period  
4.0V  
5.5V  
4.0V  
3TpC  
3TpC  
8TpC  
8TpC  
[1]  
[1]  
[1]  
[1]  
5.5V  
7
TrTin,TfTin Timer Input Rise  
and Fall Timers  
4.0V  
5.5V  
4.0V  
5.5V  
100  
100  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1, 2]  
[1, 2]  
8A  
TwIL  
Interrupt Request  
Low Time  
100  
70  
8
B
TwIL  
TwIH  
Int. Request  
Low Time  
Interrupt Request  
Input High Time  
4.0V  
5.5V  
4.0V  
5.5V  
3TpC  
3TpC  
3TpC  
3TpC  
[1, 3]  
[1, 3]  
[1, 2]  
[1, 2]  
9
10  
Twsm  
Stop-Mode Recovery  
Width Spec  
4.0V  
5.5V  
12  
12  
5TpC  
5TpC  
ns  
ns  
[8]  
[8]  
[7]  
[7]  
4.0V  
5.5V  
1
1
Tost  
Oscillator  
Start-up Time  
Watch-Dog Timer (5 ms)  
Delay Time  
4.0V  
5.5V  
4.0V  
5.5V  
4.0V  
5TpC  
5TpC  
75  
20  
150  
40  
300  
80  
1200  
320  
[4]  
[4]  
12  
Twdt  
12  
5
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
D0 = 0 [5]  
D1 = 0 [5]  
D0 = 1 [5]  
D1 = 0 [5]  
D0 = 0 [5]  
D1 = 1 [5]  
D0 = 1 [5]  
D1 = 1 [5]  
(
10 ms)  
20 ms)  
80 ms)  
25  
10  
50  
20  
225  
80  
5
.5V  
4.0V  
.5V  
4.0V  
.5V  
(
5
(
5
Notes:  
[
[
[
[
[
[
[
[
1] Timing Reference uses 0.9 V for a logic 1 and 0.1 V for a logic 0.  
2] Interrupt request through Port 3 (P33-P31).  
3] Interrupt request through Port 3 (P30).  
4] SMR – D5 = 0.  
5] Reg. WDTMR.  
6] 4.0V to 5.5V.  
7] Reg. SMR – D5 = 0.  
8] Reg. SMR – D5 = 1.  
C
C
C
C
15  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86L73/L74)  
Additional Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
CC  
No  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Units  
Notes  
1
TpC  
Input Clock Period  
2.0V  
121  
121  
DC  
DC  
25  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1]  
[1]  
3.9V  
2
TrC,TfC  
Clock Input Rise  
and Fall Times  
2.0V  
3.9V  
25  
3
4
TwC  
Input Clock Width  
2.0V  
37  
37  
100  
70  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1]  
[1]  
3.9V  
TwTinL  
Timer Input  
Low Width  
2.0V  
3.9V  
5
6
TwTinH  
TpTin  
Timer Input  
High Width  
Timer Input Period  
2.0V  
3.9V  
2.0V  
3TpC  
3TpC  
8TpC  
8TpC  
[1]  
[1]  
[1]  
[1]  
3.9V  
7
TrTin,TfTin Timer Input Rise  
and Fall Timers  
2.0V  
3.9V  
2.0V  
3.9V  
100  
100  
ns  
ns  
ns  
ns  
[1]  
[1]  
[1, 2]  
[1, 2]  
8A  
TwIL  
Interrupt Request  
Low Time  
100  
70  
8
B
TwIL  
TwIH  
Int. Request  
Low Time  
Interrupt Request  
Input High Time  
2.0V  
3.9V  
2.0V  
3.9V  
3TpC  
3TpC  
3TpC  
3TpC  
[1, 3]  
[1, 3]  
[1, 2]  
[1, 2]  
9
10  
Twsm  
Stop-Mode Recovery  
Width Spec  
2.0V  
3.9V  
12  
12  
5TpC  
5TpC  
ns  
ns  
[8]  
[8]  
[7]  
[7]  
2.0V  
3.9V  
1
1
Tost  
Oscillator  
Start-up Time  
Watch-Dog Timer (5 ms)  
Delay Time  
2.0V  
3.9V  
2.0V  
3.9V  
2.0V  
5TpC  
5TpC  
75  
20  
150  
40  
300  
80  
1200  
320  
[4]  
[4]  
12  
Twdt  
12  
5
ms  
ms  
ms  
ms  
ms  
ms  
ms  
ms  
D0 = 0 [5]  
D1 = 0 [5]  
D0 = 1 [5]  
D1 = 0 [5]  
D0 = 0 [5]  
D1 = 1 [5]  
D0 = 1 [5]  
D1 = 1 [5]  
(
10 ms)  
20 ms)  
80 ms)  
25  
10  
50  
20  
225  
80  
3
.9V  
2.0V  
.9V  
2.0V  
.9V  
(
3
(
3
Notes:  
[
[
[
[
[
[
[
[
1] Timing Reference uses 0.9 V for a logic 1 and 0.1 V for a logic 0.  
2] Interrupt request through Port 3 (P33-P31).  
3] Interrupt request through Port 3 (P30).  
4] SMR – D5 = 0.  
5] Reg. WDTMR.  
6] 2.0V to 3.9V.  
7] Reg. SMR – D5 = 0.  
8] Reg. SMR – D5 = 1.  
C
C
C
C
16  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS  
Handshake Timing Diagrams  
Data In  
Data In Valid  
Next Data In Valid  
1
2
3
/
DAV  
Delayed DAV  
(
Input)  
4
5
6
RDY  
Output)  
Delayed RDY  
(
Input Handshake Timing  
Data Out  
Data Out Valid  
Next Data Out Valid  
7
/
DAV  
Delayed DAV  
(
Output)  
8
9
11  
10  
RDY  
Input)  
Delayed RDY  
(
Output Handshake Timing  
17  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86E73/E74)  
Handshake Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
Data  
CC  
No  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Direction  
1
TsDI(DAV)  
Data In Setup Time  
4.0V  
0
0
160  
115  
IN  
IN  
IN  
IN  
5
.5V  
4.0V  
.5V  
2
ThDI(DAV)  
Data In Hold Time  
5
3
4
TwDAV  
Data Available Width  
4.0V  
.5V  
4.0V  
5.5V  
155  
110  
IN  
IN  
IN  
IN  
5
TdDAVI(RDY)  
DAV Falling to RDY  
Falling Delay  
160  
115  
5
6
TdDAVId(RDY)  
TdRDYO(DAV)  
DAV Rising to RDY  
Falling Delay  
RDY Rising to DAV  
Falling Delay  
4.0V  
5.5V  
4.0V  
5.5V  
120  
80  
IN  
IN  
IN  
IN  
0
0
7
8
TdDO(DAV)  
Data Out to DAV  
Falling Delay  
DAV Falling to RDY  
Falling Delay  
4.0V  
5.5V  
4.0V  
5.5V  
63  
63  
0
OUT  
OUT  
OUT  
OUT  
TdDAV0(RDY)  
0
9
TdRDY0(DAV)  
TwRDY  
RDY Falling to DAV  
Rising Delay  
RDY Width  
4.0V  
5.5V  
4.0V  
160  
115  
OUT  
OUT  
OUT  
OUT  
10  
110  
80  
5.5V  
11  
TdRDY0d(DAV)  
RDY Rising to DAV  
Falling Delay  
4.0V  
5.5V  
110  
80  
OUT  
OUT  
Note:  
3] 4.0V to 5.5V.  
[
18  
Z86E73/E74/L73/L74  
CP95LVO0801  
P R E L I M I N A R Y  
AC CHARACTERISTICS (Z86L73/L74)  
Handshake Timing Table  
T = 0°C to +70°C  
A
V
8.0 MHz  
Data  
CC  
No  
Symbol  
Parameter  
Note [3]  
Min  
Max  
Direction  
1
TsDI(DAV)  
Data In Setup Time  
2.0V  
0
0
160  
115  
IN  
IN  
IN  
IN  
3
.9V  
2.0V  
.9V  
2
ThDI(DAV)  
Data In Hold Time  
3
3
4
TwDAV  
Data Available Width  
2.0V  
.9V  
2.0V  
3.9V  
155  
110  
IN  
IN  
IN  
IN  
3
TdDAVI(RDY)  
DAV Falling to RDY  
Falling Delay  
160  
115  
5
6
TdDAVId(RDY)  
TdRDYO(DAV)  
DAV Rising to RDY  
Falling Delay  
RDY Rising to DAV  
Falling Delay  
2.0V  
3.9V  
2.0V  
3.9V  
120  
80  
IN  
IN  
IN  
IN  
0
0
7
8
TdDO(DAV)  
Data Out to DAV  
Falling Delay  
DAV Falling to RDY  
Falling Delay  
2.0V  
3.9V  
2.0V  
3.9V  
63  
63  
0
OUT  
OUT  
OUT  
OUT  
TdDAV0(RDY)  
0
9
TdRDY0(DAV)  
TwRDY  
RDY Falling to DAV  
Rising Delay  
RDY Width  
2.0V  
3.9V  
2.0V  
160  
115  
OUT  
OUT  
OUT  
OUT  
10  
110  
80  
3.9V  
11  
TdRDY0d(DAV)  
RDY Rising to DAV  
Falling Delay  
2.0V  
3.9V  
110  
80  
OUT  
OUT  
Note:  
3] 2.0V to 3.9V.  
[
19  
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