ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)
If the user-programmable, dual-function DIN pin on the
Connecting the Spartan device with the PROM:
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan family takes care of this automatically with an on-
chip default pull-up resistor.
The DATA output of the PROM drives the DIN input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
Programming the FPGA With Counters
Unchanged Upon Completion
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a VCC glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal power-
on-reset is always in step with the FPGAs internal
power-on-reset, which is not a safe assumption.
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
This method fails if a user applies RESET during the
Spartan device configuration process. The Spartan device
aborts the configuration and then restarts a new
configuration, as intended, but the PROM does not reset its
address counter, since it never saw a High level on its OE
input. The new configuration, therefore, reads the remaining
data in the PROM and interprets it as preamble, length
count etc. Since the Spartan device is the Master, it issues
the necessary number of CCLK pulses, up to 16 million
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
2 ) and DONE goes High. However, the Spartan device
The I/O and logic functions of the Configurable Logic Block
configuration will be completely wrong, with potential
contentions inside the Spartan device and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
Spartan FPGA PROM has been designed for compatibility
with the Master Serial mode.
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is
Low. Data is read from the PROM sequentially on a single
data line. Synchronization is provided by the rising edge
of the temporary signal CCLK, which is generated during
Programming the Spartan Family
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
control lines are required to configure the Spartan device.
Data from the PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
DS030 (v1.12) June 20, 2008