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XCS10XL-5PC208I

器件型号:XCS10XL-5PC208I
器件类别:半导体    可编程逻辑器件   
厂商名称:XILINX
厂商官网:https://www.xilinx.com/
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器件描述

FPGA, 784 CLBS, 13000 GATES, 250 MHz, PQFP208

参数
XCS10XL-5PC208I功能数量 1
XCS10XL-5PC208I端子数量 208
XCS10XL-5PC208I最大工作温度 85 Cel
XCS10XL-5PC208I最小工作温度 0.0 Cel
XCS10XL-5PC208I最大供电/工作电压 3.6 V
XCS10XL-5PC208I最小供电/工作电压 3 V
XCS10XL-5PC208I额定供电电压 3.3 V
XCS10XL-5PC208I加工封装描述 塑料, 方型扁平式封装-208
XCS10XL-5PC208I状态 DISCONTINUED
XCS10XL-5PC208I工艺 CMOS
XCS10XL-5PC208I包装形状 SQUARE
XCS10XL-5PC208I包装尺寸 FLATPACK, FINE PITCH
XCS10XL-5PC208I表面贴装 Yes
XCS10XL-5PC208I端子形式 GULL WING
XCS10XL-5PC208I端子间距 0.5000 mm
XCS10XL-5PC208I端子涂层 锡 铅
XCS10XL-5PC208I端子位置
XCS10XL-5PC208I包装材料 塑料/环氧树脂
XCS10XL-5PC208I温度等级 其他
XCS10XL-5PC208I组织 784 CLBS, 13000 门
XCS10XL-5PC208I最大FCLK时钟频率 250 MHz
XCS10XL-5PC208I可配置逻辑模块数量 784
XCS10XL-5PC208I可编程逻辑类型 FIELD PROGRAMMABLE GATE 阵列
XCS10XL-5PC208I等效门电路数量 13000
XCS10XL-5PC208I一个CLB模块最大延时 1 ns

文档预览

Product Obsolete or Under Obsolescence  
X-Ref Target - Figure 0  
R
Spartan/XL Family One-Time Programmable  
Configuration PROMs (XC17S00/XL)  
DS030 (v1.12) June 20, 2008  
Product Specification  
Features  
Configuration one-time programmable (OTP) read-only  
memory designed to store configuration bitstreams for  
Spartan , and Spartan-XL FPGAs  
Available in compact plastic 8-pin DIP, 8-pin VOIC, or  
20-pin SOIC packages  
®
Programming support by leading programmer  
manufacturers  
Simple interface to the Spartan device requires only  
one user I/O pin  
Lead-free (RoHS-compliant) packaging available  
Programmable reset polarity (active High or active Low)  
Low-power CMOS floating-gate process  
Available in 5V and 3.3V versions  
®
Design support using the Xilinx Alliance and  
Foundation™ series software packages  
Guaranteed 20 year life data retention  
Introduction  
The Spartan family of PROMs provides an easy-to-use,  
cost-effective method for storing Spartan device  
configuration bitstreams.  
complete the configuration. Once configured, it disables the  
PROM. When a Spartan device is in Slave Serial mode, the  
PROM and the Spartan device must both be clocked by an  
incoming signal.  
When the Spartan device is in Master Serial mode, it  
generates a configuration clock that drives the Spartan  
FPGA PROM. A short access time after the rising clock  
edge, data appears on the PROM DATA output pin that is  
connected to the Spartan device DIN pin. The Spartan  
device generates the appropriate number of clock pulses to  
For device programming, either the Xilinx Alliance or the  
Foundation series development systems compiles the  
Spartan device design file into a standard HEX format which  
is then transferred to most commercial PROM programmers.  
Spartan FPGA  
XCS05  
Configuration Bits  
53,984  
Compatible Spartan PROM  
XC17S05  
XC17S05XL  
XC17S10  
XCS05XL  
XCS10  
54,544  
95,008  
XCS10XL  
XCS20  
95,752  
XC17S10XL  
XC17S20  
178,144  
179,160  
247,968  
249,168  
329,312  
330,696  
559,200  
781,216  
1,040,096  
XCS20XL  
XCS30  
XC17S20XL  
XC17S30  
XCS30XL  
XCS40  
XC17S30XL  
XC17S40  
XCS40XL  
XC2S50(1)  
XC2S100(1)  
XC2S150(1)  
XC17S40XL  
XC17S50XL  
XC17S100XL  
XC17S150XL  
Notes:  
1
.
For new Spartan-II FPGA designs, it is recommended to use the 17S00A family.  
©
Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. All other trademarks are the property of their respective owners.  
DS030 (v1.12) June 20, 2008  
Product Specification  
1
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
Pin Description  
Pins not listed are in Table 1 are "no connects."  
Table 1: Spartan PROM Pinouts  
8
-pin  
20-pin  
SOIC  
(SO20)  
Pin Name  
PDIP (PD8) and  
Pin Description  
VOIC/TSOP (VO8)  
Data output, High-Z state when either CE or OE are inactive. During  
programming, the DATA pin is I/O. Note that OE can be programmed to be either  
active High or active Low.  
DATA  
CLK  
1
2
1
3
Each rising edge on the CLK input increments the internal address counter, if both  
CE and OE are active.  
When High, this input holds the address counter reset and puts the DATA output  
in a high-impedance state. The polarity of this input pin is programmable as either  
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin  
as RESET/OE, although the opposite polarity is possible on all devices. When  
RESET is active, the address counter is held at zero, and the DATA output is in a  
high-impedance state. The polarity of this input is programmable. The default is  
active High RESET, but the preferred option is active Low RESET, because it can  
be driven by the FPGAs INIT pin.  
RESET/OE  
OE/RESET)  
3
8
(
The polarity of this pin is controlled in the programmer interface. This input pin is  
easily inverted using the Xilinx HW-130 programmer software. Third-party  
programmers have different methods to invert this pin.  
When High, this pin disables the internal address counter, puts the DATA output  
in a high-impedance state, and forces the device into low-ICC standby mode.  
CE  
4
10  
GND  
VCC  
5
11  
GND is the ground connection.  
7, 8  
18, 20  
The VCC pins are to be connected to the positive voltage supply.  
Pinout Diagrams  
DATA(D0)  
NC  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
VCC  
NC  
VCC  
NC  
NC  
NC  
NC  
NC  
NC  
DATA(D0)  
CLK  
1
2
3
4
8
7
6
5
VCC  
VCC  
CLK  
NC  
NC  
NC  
PD8/PDG8  
SOG8  
VO8/VOG8  
Top View  
SO20 16  
OE/RESET  
CE  
NC  
Top  
15  
NC  
OE/RESET  
NC  
View 14  
GND  
13  
12  
11  
9
10  
DS030_05_060508  
CE  
GND  
DS030_04_110102  
DS030 (v1.12) June 20, 2008  
Product Specification  
2
 
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
If the user-programmable, dual-function DIN pin on the  
Controlling PROMs  
Connecting the Spartan device with the PROM:  
Spartan device is used only for configuration, it must still be  
held at a defined level during normal operation. The  
Spartan family takes care of this automatically with an on-  
chip default pull-up resistor.  
The DATA output of the PROM drives the DIN input of  
the lead Spartan device.  
The Master Spartan device CCLK output drives the  
CLK input of the PROM.  
Programming the FPGA With Counters  
Unchanged Upon Completion  
The RESET/OE input of the PROM is driven by the  
INIT output of the Spartan device. This connection  
assures that the PROM address counter is reset before  
the start of any (re)configuration, even when a  
reconfiguration is initiated by a VCC glitch. Other  
methods—such as driving RESET/OE from LDC or  
system reset—assume that the PROM internal power-  
on-reset is always in step with the FPGAs internal  
power-on-reset, which is not a safe assumption.  
When multiple-configurations for a single Spartan device  
are stored in a PROM, the OE pin should be tied Low. Upon  
power-up, the internal address counters are reset and  
configuration begins with the first program stored in  
memory. Since the OE pin is held Low, the address  
counters are left unchanged after configuration is complete.  
Therefore, to reprogram the FPGA with another program,  
the DONE line is pulled Low and configuration begins at the  
last value of the address counters.  
The CE input of the PROM is driven by the DONE  
output of the Spartan device, provided that DONE is  
not permanently grounded. Otherwise, LDC can be  
used to drive CE, but must then be unconditionally  
High during user operation. CE can also be  
This method fails if a user applies RESET during the  
Spartan device configuration process. The Spartan device  
aborts the configuration and then restarts a new  
configuration, as intended, but the PROM does not reset its  
address counter, since it never saw a High level on its OE  
input. The new configuration, therefore, reads the remaining  
data in the PROM and interprets it as preamble, length  
count etc. Since the Spartan device is the Master, it issues  
the necessary number of CCLK pulses, up to 16 million  
permanently tied Low, but this keeps the DATA output  
active and causes an unnecessary supply current of  
10 mA maximum.  
FPGA Master Serial Mode Summary  
2
4
(
2 ) and DONE goes High. However, the Spartan device  
The I/O and logic functions of the Configurable Logic Block  
configuration will be completely wrong, with potential  
contentions inside the Spartan device and on its output  
pins. This method must, therefore, never be used when  
there is any chance of external reset during configuration.  
(CLB) and their associated interconnections are established  
by a configuration program. The program is loaded either  
automatically upon power up, or on command, depending  
on the state of the Spartan device MODE pin. In Master  
Serial mode, the Spartan device automatically loads the  
configuration program from an external memory. The  
Spartan FPGA PROM has been designed for compatibility  
with the Master Serial mode.  
Standby Mode  
The PROM enters a low-power standby mode whenever CE  
is asserted High. The output remains in a high-impedance  
state regardless of the state of the OE input.  
Upon power-up or reconfiguration, the Spartan device  
enters the Master Serial mode when the MODE pin is  
Low. Data is read from the PROM sequentially on a single  
data line. Synchronization is provided by the rising edge  
of the temporary signal CCLK, which is generated during  
configuration.  
Programming the Spartan Family  
PROMs  
The devices can be programmed on programmers supplied  
by Xilinx or qualified third-party vendors. The user must  
ensure that the appropriate programming algorithm and the  
latest version of the programmer software are used. The  
wrong choice can permanently damage the device.  
Master Serial mode provides a simple configuration  
interface (Figure 1, page 4). Only a serial data line and two  
control lines are required to configure the Spartan device.  
Data from the PROM is read sequentially, accessed via the  
internal address and bit counters which are incremented on  
every valid rising edge of CCLK.  
DS030 (v1.12) June 20, 2008  
Product Specification  
3
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
X-Ref Target - Figure 1  
Spartan  
Master Serial  
3.3V  
V
CC  
CC  
MODE  
4.7K  
V
V
CC  
D
IN  
DATA  
CLK  
CCLK  
DONE  
INIT  
Spartan  
PROM  
CE  
OE/RESET  
(Low Resets the Address Pointer)  
CCLK  
Output)  
(
D
IN  
D
OUT  
(Output)  
DS030_01_101001  
Figure 1: Master Serial Mode  
Note: The one-time-programmable Spartan PROM supports automatic loading of configuration programs. An early DONE inhibits the  
PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.  
DS030 (v1.12) June 20, 2008  
Product Specification  
4
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
X-Ref Target - Figure 2  
V
CC  
GND  
RESET/  
CE  
OE  
or  
OE/  
RESET  
Address Counter  
CLK  
TC  
EPROM  
Cell  
OE  
Output  
DATA  
Matrix  
DS030_02_011300  
Figure 2: Simplified Block Diagram (Does not Show Programming Circuit)  
Caution! Always tie the two VCC pins together in the application.  
Table 2: Truth Table for XC17S00 Control Inputs  
Control Inputs  
Outputs  
Internal Address(2)  
RESET(1)  
CE  
DATA  
ICC  
If address < TC: increment  
If address > TC: don’t change  
Active  
High-Z  
Active  
Reduced  
Inactive  
Low  
Active  
Inactive  
Active  
Low  
High  
High  
Held reset  
Not changing  
Held reset  
High-Z  
High-Z(3)  
High-Z(3)  
Active  
Standby  
Standby  
Notes:  
1
2
3
.
.
.
The XC17S00 RESET input has programmable polarity.  
TC = Terminal Count = highest address value. TC + 1 = address 0.  
Pull DATA pin to GND or VCC to meet ICCS standby current.  
DS030 (v1.12) June 20, 2008  
Product Specification  
5
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
XC17S05, XC17S10, XC17S20, XC17S30, XC17S40  
Absolute Maximum Ratings(1)  
Symbol  
VCC  
VIN  
Description  
Value  
–0.5 to +7.0  
–0.5 to VCC +0.5  
–0.5 to VCC +0.5  
–65 to +150  
+125  
Units  
V
Supply voltage relative to GND  
Input voltage relative to GND  
Voltage applied to High-Z output  
Storage temperature (ambient)  
Junction temperature  
V
VTS  
V
TSTG  
TJ  
°C  
°C  
Notes:  
1
.
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only,  
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.  
Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.  
Operating Conditions(1)  
Symbol  
Description  
Commercial  
Industrial  
Conditions  
Supply voltage relative to GND (T = 0°C to +70°C)  
Min  
4.75  
4.50  
Max  
5.25  
5.50  
Units  
V
V
A
VCC  
Supply voltage relative to GND (T = –40°C to +85°C)  
A
Notes:  
During normal read operation both VCC pins must be connected together.  
1
.
DC Characteristics Over Operating Condition  
Symbol  
VIH  
Description  
Min  
2.0  
0
Max  
VCC  
0.8  
Units  
High-level input voltage  
Low-level input voltage  
V
V
V
V
V
V
VIL  
VOH  
VOL  
High-level output voltage (IOH = –4 mA)  
Low-level output voltage (IOL = +4 mA)  
High-level output voltage (IOH = –4 mA)  
Low-level output voltage (IOL = +4 mA)  
3.86  
Commercial  
Industrial  
0.32  
VOH  
VOL  
3.76  
0.37  
XC17S05, XC17S10, XC17S20,  
XC17S30  
1
0
mA  
mA  
μA  
Supply current, active mode  
ICCA  
(
at maximum frequency)  
XC17S40  
20  
XC17S05, XC17S10, XC17S20,  
XC17S30  
50(1)  
ICCS  
Supply current, standby mode  
XC17S40  
–10  
100(1)  
10  
μA  
μA  
pF  
pF  
IL  
Input or output leakage current  
CIN  
Input Capacitance (VIN = GND, f = 1.0 MHz)  
Output Capacitance (VIN = GND, f = 1.0 MHz)  
10  
COUT  
10  
Notes:  
ICCS standby current is specified for DATA pin that is pulled to VCC or GND.  
1
.
DS030 (v1.12) June 20, 2008  
Product Specification  
6
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL, XC17S50XL,  
XC17S100XL, XC17S150XL  
Absolute Maximum Ratings(1)  
Symbol  
VCC  
Description  
Value  
Units  
V
Supply voltage relative to GND  
Input voltage with respect to GND  
Voltage applied to High-Z output  
Storage temperature (ambient)  
–0.5 to +4.0  
VIN  
–0.5 to VCC +0.5  
–0.5 to VCC +0.5  
–65 to +150  
V
VTS  
V
TSTG  
°C  
Notes:  
1
.
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only,  
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.  
Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.  
Operating Conditions(1)  
Symbol  
Description  
Commercial  
Industrial  
Min  
3.0  
3.0  
Max  
3.6  
Units  
Supply voltage relative to GND (T = 0°C to +70°C)  
V
V
A
VCC  
Supply voltage relative to GND (T = –40°C to +85°C)  
3.6  
A
Notes:  
During normal read operation both VCC pins must be connected together.  
1
.
DC Characteristics Over Operating Condition  
Symbol  
VIH  
Description  
Min  
2.0  
0
Max  
VCC  
0.8  
Units  
V
High-level input voltage  
Low-level input voltage  
VIL  
V
VOH  
VOL  
ICCA  
ICCS  
IL  
High-level output voltage (IOH = –3 mA)  
Low-level output voltage (IOL = +3 mA)  
Supply current, active mode (at maximum frequency)  
Supply current, standby mode  
2.4  
V
0.4  
5
V
mA  
μA  
μA  
pF  
pF  
50(1)  
10  
Input or output leakage current  
–10  
CIN  
Input Capacitance (VIN = GND, f = 1.0 MHz)  
Output Capacitance (VIN = GND, f = 1.0 MHz)  
10  
COUT  
10  
Notes:  
ICCS standby current is specified for DATA pin that is pulled to VCC or GND.  
1
.
DS030 (v1.12) June 20, 2008  
Product Specification  
7
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
AC Characteristics over Operating Condition(1)  
CE  
T
T
T
HCE  
SCE  
SCE  
RESET/OE  
CLK  
T
HOE  
T
T
HC  
LC  
T
CYC  
T
T
DF  
OE  
T
T
CAC  
OH  
T
CE  
DATA  
T
OH  
DS0306_03_011300  
Symbol  
Description  
Min  
Max  
45  
60  
80  
Units  
TOE  
TCE  
RESET/OE to Data Delay  
CE to Data Delay  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCAC  
TOH  
CLK to Data Delay  
Data Hold From CE, RESET/OE, or CLK(2)  
CE or RESET/OE to Data Float Delay(2,3)  
Clock Periods  
0
TDF  
50  
TCYC  
TLC  
100  
50  
50  
25  
0
CLK Low Time(2)  
THC  
CLK High Time(2)  
TSCE  
THCE  
THOE  
CE Setup Time to CLK (to guarantee proper counting)  
CE Hold Time to CLK (to guarantee proper counting)  
RESET/OE Hold Time (guarantees counters are reset)  
25  
Notes:  
1
2
3
4
.
.
.
.
AC test load = 50 pF.  
Guaranteed by design, not tested.  
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.  
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.  
DS030 (v1.12) June 20, 2008  
Product Specification  
8
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
Ordering Information  
XC17S20XL VO8 C  
Device Number  
Operating Range/Processing  
XC17S05  
C = Commercial (T = 0°C to +70°C)  
A
XC17S05XL  
XC17S10  
I = Industrial (T = –40°C to +85°C)  
A
XC17S10XL  
XC17S20  
XC17S20XL  
XC17S30  
XC17S30XL  
XC17S40  
Package Type(1)  
PD8/PDG08 = 8-pin Plastic DIP  
VO8/VOG8 = 8-pin Plastic Small-Outline Thin Package  
SOG8 = 8-pin Plastic Small-Outline Package  
SO20 = 20-pin Plastic Small-Outline Package  
XC17S40XL  
XC17S50XL  
XC17S100XL  
XC17S150XL  
Notes:  
1
.
G in the package-type codes designates Lead-free packaging.  
Spartan 5V Valid Ordering Combinations (XC17S00)  
XC17S05PD8C  
XC17S05VO8C  
XC17S05PD8I  
XC17S05VO8I  
XC17S10PD8C  
XC17S10VO8C  
XC17S10VOG8C  
XC17S10PD8I  
XC17S10VO8I  
XC17S20PD8C  
XC17S20VO8C  
XC17S20PD8I  
XC17S20VO8I  
XC17S30PD8C  
XC17S30VO8C  
XC17S30PD8I  
XC17S30VO8I  
XC17S30SOG8I  
XC17S40PD8C  
XC17S40SO20C  
XC17S40PD8I  
XC17S40SO20I  
Spartan 3.3V Valid Ordering Combinations (XC17S00XL)  
XC17S05XLPD8C  
XC17S05XLVO8C  
XC17S05XLPD8I  
XC17S05XLVO8I  
XC17S10XLPD8C  
XC17S10XLPDG8C  
XC17S10XLVO8C  
XC17S10XLVOG8C  
XC17S10XLPD8I  
XC17S10XLVO8I  
XC17S10XLVOG8I  
XC17S100XLPD8C  
XC17S100XLSO20C  
XC17S100XLPD8I  
XC17S100XLSO20I  
XC17S150XLPD8C  
XC17S150XLSO20C  
XC17S150XLPD8I  
XC17S150XLSO20I  
XC17S20XLPD8C  
XC17S20XLVO8C  
XC17S20XLVOG8C  
XC17S20XLPD8I  
XC17S20XLVO8I  
XC17S30XLPD8C  
XC17S30XLPDG8C  
XC17S30XLVO8C  
XC17S30XLVOG8C  
XC17S30XLPD8I  
XC17S30XLVO8I  
XC17S30XLVOG8I  
XC17S40XLPD8C  
XC17S40XLPDG8C  
XC17S40XLSO20C  
XC17S40XLPD8I  
XC17S40XLSO20I  
XC17S50XLPD8C  
XC17S50XLSO20C  
XC17S50XLPD8I  
XC17S50XLSO20I  
DS030 (v1.12) June 20, 2008  
Product Specification  
9
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
Marking Information  
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC  
prefix is deleted and the package code is simplified. Device marking is as follows.  
17S20L V C  
Device Number  
Operating Range/Processing  
1
1
1
1
1
1
1
1
1
1
1
1
1
7S05  
7S05L  
7S10  
7S10L  
7S20  
7S20L  
7S30  
7S30L  
7S40  
7S40L  
7S50L  
7S100L  
7S150L  
C = Commercial (T = 0°C to +70°C)  
A
I = Industrial (T = –40°C to +85°C)  
A
Package Mark  
O = 8-pin Plastic Small-Outline Package, Lead-Free  
P = 8-pin Plastic DIP  
H = 8-pin Plastic DIP, Lead-Free  
V = 8-pin Plastic Small-Outline Thin Package  
G = 8-pin Plastic Small-Outline Thin Package, Lead-Free  
S = 20-pin Plastic Small-Outline Package  
Note: When marking the device number on the XL parts, an L is used in place of an XL.  
Revision History  
The following table shows the revision history for this document.  
Date  
Revision  
1.1  
Revision  
0
0
7/14/98  
9/08/98  
Cosmetic edits for pages 1, 2, and 4.  
1.2  
Clarified the SPARTAN FPGA and PROM interface by removing references to CEO pin. Removed the ESD  
notation in Absolute Maximum table since it is now included in Xilinx’s Reliability Monitor Report.  
0
0
0
0
0
1
1
1
1/20/00  
2/18/00  
4/04/00  
8/06/00  
4/07/01  
0/10/01  
1/04/02  
1/18/02  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
1.10  
Added additional Spartan-XL parts, changed SPROM to PROM.  
Changed device ordering numbers, added 4.7K resistor to OE/RESET in Figure 1.  
Added XC17S200XL PROM for Spartan XC2S200.  
Updated format.  
Added to features: “Guaranteed 20 year life data retention.”  
Updated Table 1, page 2. Updated the template. Added "Pinout Diagrams," page 2.  
Modified document title.  
DS030 (v1.12) June 20, 2008  
Product Specification  
10  
R
ProduScptarOtabn/XsLoFlaemtiely Oonre-UTimnedPerorgrOambmsaobleleCsoncfiegunractieon PROMs (XC17S00/XL)  
0
7/09/07  
1.11  
 Updated document format.  
Added Lead-free (RoHS-compliant) packages PDG8 and VOG8 to "Ordering Information," page 9.  
Added new Lead-free package types G and H to "Marking Information," page 10.  
0
6/20/08  
1.12  
 Updated document template.  
Added junction temperature to "Absolute Maximum Ratings(1)," page 6.  
Added support for XC17S30SOG8I.  
Notice of Disclaimer  
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND  
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED  
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE  
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.  
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE  
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES  
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO  
APPLICABLE LAWS AND REGULATIONS.  
DS030 (v1.12) June 20, 2008  
Product Specification  
11  
 
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