The Western Design Center, Inc. W65C02S Data Sheet
February 2004
W65C02S
Microprocessor
DATA SHEET
WDC
The Western Design Center, Inc., 2003. All rights reserved
The Western Design Center, Inc. W65C02S Data Sheet
February 2004
WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible
product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been
made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to
particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each
application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing
contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of
third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of
which are available upon request.
Copyright 1981-2004 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole, or
in part, in any form.
The Western Design Center, Inc. W65C02S Data Sheet 2
The Western Design Center, Inc.
W65C02S Data Sheet
TABLE OF CONTENTS
1 INTRODUCTION................................................................................................................................................................................5
1.1 FEATURES OF THE W65C02S ..................................................................................................................................................... 5
2 FUNCTIONAL DESCRIPTION......................................................................................................................................................6
2.1 INSTRUCTION REGISTER (IR) AND DECODE ........................................................................................................................... 6
2.2 TIMING CONTROL UNIT (TCU) ................................................................................................................................................. 6
2.3 ARITHMETIC AND LOGIC UNIT (ALU) ..................................................................................................................................... 6
2.4 ACCUMULATOR REGISTER (A)................................................................................................................................................... 6
2.5 INDEX REGISTERS (X AND Y)...................................................................................................................................................... 6
2.6 PROCESSOR STATUS REGISTER (P) ........................................................................................................................................... 6
2.7 PROGRAM COUNTER REGISTER (PC)....................................................................................................................................... 6
2.8 STACK POINTER REGISTER (S) .................................................................................................................................................. 7
3 PIN FUNCTION DESCRIP TION ...................................................................................................................................................9
3.1 ADDRESS BUS (A0-A15)............................................................................................................................................................... 9
3.2 BUS ENABLE (BE).......................................................................................................................................................................... 9
3.3 DATA BUS (D0-D7)........................................................................................................................................................................ 9
3.4 INTERRUPT REQUEST (IRQB).................................................................................................................................................... 9
3.5 MEMORY LOCK (MLB) ............................................................................................................................................................... 9
3.6 NON-MASKABLE INTERRUPT (NMIB)...................................................................................................................................... 9
3.7 NO CONNECT (NC) ..................................................................................................................................................................... 10
3.8 PHASE 2 IN (PHI2), PHASE 2 OUT (PHI2O) AND PHASE 1 OUT (PHI1O) ...................................................................... 10
3.9 READ/WRITE (RWB) ................................................................................................................................................................. 10
3.10 READY (RDY) .............................................................................................................................................................................. 10
3.11 RESET (RESB) ............................................................................................................................................................................. 11
3.12 SET OVERFLOW (SOB).............................................................................................................................................................. 11
3.13 SYNCHRONIZE WITH OPCODE FETCH (SYNC)................................................................................................................... 11
3.14 POWER (VDD) AND GROUND (VSS)........................................................................................................................................ 11
3.15 VECTOR PULL (VPB) ................................................................................................................................................................. 11
4 ADDRESSING MODES ...................................................................................................................................................................16
4.1 ABSOLUTE A.................................................................................................................................................................................. 16
4.2 ABSOLUTE INDEXED INDIRECT (A,X) ...................................................................................................................................... 16
4.3 ABSOLUTE INDEXED WITH X A,X............................................................................................................................................. 16
4.4 ABSOLUTE INDEXED WITH Y A, Y ............................................................................................................................................ 17
4.5 ABSOLUTE INDIRECT (A)............................................................................................................................................................ 17
4.6 ACCUMULATOR A ....................................................................................................................................................................... 17
4.7 IMMEDIATE ADDRESSING #....................................................................................................................................................... 17
4.8 IMPLIED I....................................................................................................................................................................................... 17
4.9 PROGRAM COUNTER RELATIVE R........................................................................................................................................... 18
4.10 STACK S ......................................................................................................................................................................................... 18
4.11 ZERO PAGE ZP.............................................................................................................................................................................. 18
4.12 ZERO PAGE INDEXED INDIRECT (ZP,X) .................................................................................................................................. 18
4.13 ZERO PAGE INDEXED WITH X ZP,X......................................................................................................................................... 19
4.14 ZERO PAGE INDEXED WITH Y ZP, Y ........................................................................................................................................ 19
4.15 ZERO PAGE INDIRECT (ZP)........................................................................................................................................................ 19
4.16 ZERO PAGE INDIRECT INDEXED WITH Y (ZP), Y .................................................................................................................. 19
5 OPERATION TABLES ....................................................................................................................................................................21
6 DC, AC AND TIMING CHARACTERISTICS .........................................................................................................................23
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6.1 DC CHARACTERISTICS TA = -40C TO +85C (PLCC, QFP) TA= 0C TO 70C (DIP) .......................................... 24
6.2 AC CHARACTERISTICS TA = -40C TO +85C (PLCC, QFP) TA= 0C TO 70C (DIP) .......................................... 25
7 CAVEATS ............................................................................................................................................................................................36
8 W65C02DB DEVELOPER BOARD AND .................................................................................................................................37
IN-CIRCUIT EMULATOR (ICE)..........................................................................................................................................................37
8.1 FEATURES :.................................................................................................................................................................................... 38
8.2 MEMORY MAP:............................................................................................................................................................................. 38
8.3 CROSS-DEBUGGING MONITOR PROGRAM............................................................................................................................. 38
8.4 BUILDING................................................................................................................................................................................... 38
9 HARD CORE MODEL .....................................................................................................................................................................39
9.1 FEATURES OF THE W65C02S HARD CORE MODEL................................................................................................................. 39
10 SOFT CORE RTL MODEL ........................................................................................................................................................39
10.1 W65C02 SYNTHESIZABLE RTL-CODE IN VERILOG HDL................................................................................................. 39
TABLE OF TABLES
TABLE 3 -1 VECTOR LOCATIONS....................................................................................................................................................12
TABLE 3 -2 PIN FUNCTION TABLE..................................................................................................................................................12
TABLE 4 -1 ADDRESSING MODE TABLE ......................................................................................................................................20
TABLE 5 -1 INSTRUCTION SET TABLE .........................................................................................................................................21
TABLE 5 -2 W65C02S OPCODE MATRIX ........................................................................................................................................22
TABLE 6 -1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................23
TABLE 6 -2 DC CHARACTERISTICS................................................................................................................................................24
TABLE 6 -3 AC CHARACTERISTICS ..............................................................................................................................................25
TABLE 6 -4 OPERATION, OPERATION CODES AND STATUS REGISTER.....................................................................28
TABLE 6 -5 INSTRUCTION TIMING CHART ...............................................................................................................................32
TABLE 7 -1 MICROPROCESSOR OPERATIONAL ENHANCEMENTS ..............................................................................36
TABLE OF FIGURES
FIGURE 2-1 W65C02S INTERNAL ARCHITECTURE SIMPLIFIED BLOCK DIAGRAM.............................................7
FIGURE 2-2 W65C02S MICROPROCESSOR PROGRAMMING MODEL ............................................................................8
FIGURE 3-1 W65C02S 40 PIN PDIP PINOUT .................................................................................................................................13
FIGURE 3-2 W65C02S 44 PIN PLCC PINOUT ...............................................................................................................................14
FIGURE 3-3 W65C02S 44 PIN QFP PINOUT ..................................................................................................................................15
FIGURE 6-1 IDD VS VDD .....................................................................................................................................................................24
FIGURE 6-2 F MAX VS VDD...............................................................................................................................................................24
FIGURE 6-3 GENERAL TIMING DIAGRAM ................................................................................................................................26
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The Western Design Center, Inc. W65C02S Data Sheet
1 INTRODUCTION
The W65C02S is a low power cost sensitive 8-bit microprocessor. The W65C02S is a fully static core and the PHI2 clock
can be stopped when it is in the high (logic 1) or low (logic 0) state. The variable length instruction set and manually
optimized core size makes the W65C02S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog
RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for
evaluation or volume production. To aid in system development, WDC provides a Development System that includes a
W65C02DB Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see
www.westerndesigncenter.com for more information.
1.1 Features of the W65C02S
8-bit data bus
16-bit address bus provides access to 65,536 bytes of memory space
8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register
16-bit Program Counter
69 instructions
16 addressing modes
212 Operation Codes (OpCodes)
Vector Pull (VPB) output indicates when interrupt vectors are being addressed
WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and
provide synchronization with external events
Variable length instruction set provides for lower power and smaller code optimization over fixed length instruction
set processors
Fully static circuitry
Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified
Low Power consumption, 150uA@1MHz
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2 FUNCTIONAL DESCRIPTION
The internal organization of the W65C02S is divided into two parts: 1) Register Section and 2) Control Section.
Instructions obtained from program memory are executed by implementing a series of data transfers within the
Register Section. Signals that cause data transfers are generated within the Control Section.
2.1 Instruction Register (IR) and Decode
The Operation Code (OpCode) portion of the instruction is loaded into the Instruction Register from the Data Bus
and is latched during the OpCode fetch cycle. The OpCode is then decoded, along with timing and interrupt signals,
to generate various control signals for program execution.
2.2 Timing Control Unit (TCU)
The Timing Control Unit (TCU) provides timing for each instruction cycle that is executed. The TCU is set to zero for each
instruction fetch, and is advanced at the beginning of each cycle for as many cycles as is required to complete the instruction.
Data transfers between registers depend upon decoding the contents of both the IR and the TCU.
2.3 Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the ALU. In addition to data operations, the ALU also
calculates the effective address for relative and indexed addressing modes. The result of a data operation is stored in
either memory or an internal register. Carry, Negative, Overflow and Zero flags are updated following the ALU data
operation.
2.4 Accumulator Register (A)
The Accumulator Register (A) is an 8-bit general purpose register which holds one of the operands and the result of
arithmetic and logical operations. Reconfigured versions of this processor family could have additional
accumulators.
2.5 Index Registers (X and Y)
There are two 8-bit Index Registers (X and Y) which may be used as general purpose registers or to provide an index
value for calculation of the effective address. When executing an instruction with indexed addressing, the
microprocessor fetches the OpCode and the base address, and then modifies the address by adding the Index
Register contents to the address prior to performing the desired operation.
2.6 Processor Status Register (P)
The 8-bit Processor Status Register (P) contains status flags and mode select bits. The Carry (C), Negative (N),
Overflow (V) and Zero (Z) status flags serve to report the status of ALU operations. These status flags are tested
with Conditional Branch instructions. The Decimal (D) and IRQB disable (I) are used as mode select flags. These
flags are set by the program to change microprocessor operations. Bit 5 is available for a user status or mode bit.
2.7 Program Counter Register (PC)
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The 16-bit Program Counter Register (PC) provides the addresses which are used to step the microprocessor through
sequential program instructions. This register is incremented each time an instruction or operand is fetched from
program memory.
2.8 Stack Pointer Register (S)
The Stack Pointer Register (S) is an 8-bit register which is used to indicate the next available location in the stack
memory area. It serves as the effective address in stack addressing modes as well as subroutine and interrupt
processing.
A0-A15 ADDRESS BUFFER INTERNAL ADDRESS BUS (16 BITS) INDEX X INTERNAL DATA BUS (8 BITS) INTERRUPT IRQB
D0-D7 (8 BITS) LOGIC NMIB
RESB
INDEX Y TIMING
(8 BITS) CONTROL PHI2
STACK POINTER
BE (S) (8 BITS) INSTRUCTION
ALU DECODE
DATA BUS BUFFER (8 BITS) BE
BE SYSTEM RWB
ACCUMULATOR CONTROL RDY
(A) ( 8BITS) VPB
INSTRUCTION REGISTER SYNC
PROG. COUNTER (8 BITS)
(PC) (16 BITS)
PROCESSOR
STATUS
(P) 8 BITS
DATA
LATCH
Figure 2-1 W65C02S Internal Architecture Simplified Block Diagram
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7 W65C02S Data Sheet
A 0
Accumulator A
7
0
Y Index Register Y
7 0
Index Register X
X
0
15 7 Program Counter PC
PCH PCL 0
Stack Pointer S
87
1 S
N V 1 B D I Z C Processor Status Register "P"
Carry 1 = true
Zero 1 = result
IRQB disable 1 = disable
Decimal mode 1= true
BRK command 1 = BRK, 0 = IRQB
Overflow 1 = true
Negative 1 = neg.
Figure 2-2 W65C02S Microprocessor Programming Model
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3 PIN FUNCTION DESCRIPTION
3.1 Address Bus (A0-A15)
The sixteen bit Address Bus formed by A0-A15, address memory and I/O registers that exchange data on the Data
Bus. The address lines can be set to the high impedance state by the Bus Enable (BE) signal.
3.2 Bus Enable (BE)
The Bus Enable (BE) input signal provides external control of the Address, Data and the RWB buffers. When Bus
Enable is high, the Address, Data and RWB buffers are active. When BE is low, these buffers are set to the high
impedance status. Bus Enable is an asynchronous signal.
3.3 Data Bus (D0-D7)
The eight Data Bus lines D0-D7 are used to provide instructions, data and addresses to the microprocessor and
exchange data with memory and I/O registers. These lines may be set to the high impedance state by the Bus Enable
(BE) signal.
3.4 Interrupt Request (IRQB)
The Interrupt Request (IRQB) input signal is used to request that an interrupt sequence be initiated. The program
counter (PC) and Processor Status Register (P) are pushed onto the stack and the IRQB disable (I) flag is set to a "1"
disabling further interrupts before jumping to the interrupt handler. These values are used to return the processor to
its original state prior to the IRQB interrupt. The IRQB low level should be held until the interrupt handler clears
the interrupt request source. When Return from Interrupt (RTI) is executed the (I) flag is restored and a new
interrupt can be handled. If the (I) flag is cleared in an interrupt handler, nested interrupts can occur. The Wait-for-
Interrupt (WAI) instruction may be used to reduce power and synchronize with, as an example timer interrupt
requests.
3.5 Memory Lock (MLB)
The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in a
multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB is low.
Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
referencing instructions.
3.6 Non-Maskable Interrupt (NMIB)
A negative transition on the Non-Maskable Interrupt (NMIB) input initiates an interrupt sequence after the current
instruction is completed. Since NMIB is an edge-sensitive input, an interrupt will occur if there is a negative
transition while servicing a previous interrupt. Also, after the edge interrupt occurs no further interrupts will occur if
NMIB remains low. The NMIB signal going low causes the Program Counter (PC) and Processor Status Register
information to be pushed onto the stack before jumping to the interrupt handler. These values are used to return the
processor to it's original state prior to the NMIB interrupt.
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3.7 No Connect (NC)
The No Connect (NC) pins are not connected internally and should not be connected externally.
3.8 Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O)
Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby
Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers since the
microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from PHI2. Phase 1 Out
(PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for driving PHI2 and used for the main
system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for
system timing and internal oscillators when an external crystal was used.
3.9 Read/Write (RWB)
The Read/Write (RWB) output signal is used to control data transfer. When in the high state, the microprocessor is
reading data from memory or I/O. When in the low state, the Data Bus contains valid data to be written from the
microprocessor and stored at the addressed memory or I/O location. The RWB signal is set to the high impedance
state when Bus Enable (BE) is low.
3.10 Ready (RDY)
A low input logic level on the Ready (RDY) will halt the microprocessor in its current state. Returning RDY to the
high state allows the microprocessor to continue operation following the next PHI2 negative transition. This bi-
directional signal allows the user to single -cycle the microprocessor on all cycles including write cycles. A negative
transition to the low state prior to the falling edge of PHI2 will halt the microprocessor with the output address lines
reflecting the current address being fetched. This assumes the processor setup time is met. This condition will
remain through a subsequent PHI2 in which the ready signal is low. This feature allows microprocessor interfacing
with low-speed memory as well as direct memory access (DMA). The WAI instruction pulls RDY low signaling the
WAit-for-Interrupt condition, thus RDY is a bi-directional pin. On the W65C02 hard core there is a WAIT output
signal that can be used in ASIC's thus removing the bi-directional signal and RDY becomes only the input. In such
a situation the WAI instruction will pull WAIT low and must be used external of the core to pull RDY low or the
processor will continue as if the WAI never happened. The microprocessor will be released when RDY is high and
a falling edge of PHI2 occurs. This again assumes the processor control setup time is met. The RDY pin has an
active pull-up, when outputting a low level, the pull-up is disabled. The RDY pin can still be wire ORed.
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3.11 Reset (RESB)
The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB signal must
be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect while
RESB is being held low. All Registers are initialized by software except the Decimal and Interrupt disable mode
select bits of the Processor Status Register (P) are initialized by hardware. When a positive edge is detected, there
will be a reset sequence lasting seven clock cycles. The program counter is loaded with the reset vector from
locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. RESB should be
held high after reset for normal operation.
Processor Status Register (P)
7 6 5 4 3 2 1 0
* * 1 1 0 1 * *
NV B DI Z C
*=software initialized
3.12 Set Overflow (SOB)
A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The signal is
sampled on the rising edge of PHI2. SOB was originally intended for fast input recognition because it can be tested
with a branch instruction; however, it is not recommended in new system design and was seldom used in the past.
3.13 SYNChronize with OpCode fetch (SYNC)
The OpCode fetch cycle of the microprocessor instruction is indicated with SYNC high. The SYNC output is
provided to identify those cycles during which the microprocessor is fetching an OpCode. The SYNC line goes high
during the clock cycle of an OpCode fetch and stays high for the entire cycle. If the RDY line is pulled low during
the clock cycle in which SYNC went high, the processor will stop in its current state and will remain in the state
until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause single
instruction execution.
3.14 Power (VDD) and Ground (VSS)
VDD is the positive power supply voltage and VSS is system logic ground.
3.15 Vector Pull (VPB)
The Vector Pull (VPB) output indicates that a vector location is being addressed during an interrupt sequence. VPB
is low during the last interrupt sequence cycles, during which time the processor reads the interrupt vector. The
VPB signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses.
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Table 3-1 Vector Locations
FFFE, F BRK/IRQB Software/Hardware
FFFC, D RESB Hardware
FFFA, B NMIB Hardware
Table 3-2 Pin Function Table
Pin Description
A0-A15 Address Bus
BE Bus Enable
D0-D7 Data Bus
IRQB Interrupt Request
MLB Memory Lock
NC No Connection
NMIB Non-Maskable Interrupt
PHI1O Phase 1 Out Clock
PHI2 Phase 2 In Clock
PHI2O Phase 2 Out Clock
RDY Ready
RESB Reset
RWB Read/Write
SOB Set Overflow
SYNC Synchronize
VDD Positive Power Supply
VPB Vector Pull
VSS Internal Logic Ground
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VPB 1 40 RESB
RDY 2 39 PHI2C
PHI1O 3 38 SOB
IRQB 4 37 PHI2
MLB 5 36 BE
NMIB 6 35 NC
SYNC 7 34 RWB
VDD 8 33 D0
32 D1
A0 9 31 D2
A1 10 30 D3
A2 11 29 D4
A3 12 28 D5
A4 13 27 D6
A5 14 26 D7
A6 15 25 A15
A7 16 24 A14
A8 17 23 A13
A9 18 22 A12
A10 19 21 VSS
A11 20
Figure 3-1 W65C02S 40 Pin PDIP Pinout
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MLB IRQB PHI1O RDY VPB VSS RESB PHI2O SOB PHI2 BE
6 5 4 3 2 1 44 43 42 41 40
NMIB 7 39 NC
SYNC 8 RWB
38 VDD
VDD 9 D0
A0 10 37 D1
A1 11 D2
NC 12 36 D3
A2 13 D4
A3 14 35 D5
A4 15 D6
A5 16 W65C02 34 D7
A6 17
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
A7 A8 A9 A10 A11 VSS VSS A12 A13 A14 A15
Figure 3-2 W65C02S 44 Pin PLCC Pinout
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MLB IRQB PHI1O RDY VPB VSS RESB PHI2O SOB PHI2 BE
44 43 42 41 40 39 38 37 36 35 34
NMIB 1 33 NC
RWB
SYNC 2 32 VDD
D0
VDD 3 31 D1
D2
A0 4 30 D3
D4
A1 5 29 D5
D6
NC 6 28 D7
A2 7 27
A3 8 26
A4 9 25
A5 10 24
A6 11 23
12 13 14 15 16 17 18 19 20 21 22
A7 A8 A9 A10 A11 VSS VSS A12 A13 A14 A15
Figure 3-3 W65C02S 44 Pin QFP Pinout
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4 ADDRESSING MODES
The W65C02S is capable of directly addressing 65,536 bytes of memory. The Program Address and Data Address space is
contiguous throughout the 65,536 byte address space. Words, arrays, records, or any data structures may span the 65,536
byte address space. The following addressing mode descriptions provide additional detail as to how effective addresses are
calculated. Sixteen addressing modes are available for the W65C02S. This address space has special significance within
certain addressing modes.
4.1 Absolute a
With Absolute addressing the second and third bytes of the instruction form the 16-bit address.
Byte: 2 1 0
Instruction: ADH ADL OpCode
Operand Address: ADH ADL
4.2 Absolute Indexed Indirect (a,x)
With the Absolute Indexed Indirect addressing mode, the X Index Register is added to the second and third byes of the
instruction to form an address to a pointer. This address mode is only used with the JMP instruction and the program
Counter is loaded with the first and second bytes at this pointer.
Byte: 2 1 0
Instruction: ADH ADL OpCode
Indirect Base address: ADH ADL
Indirect address: + X
New PC value:
effective address
indirect address
4.3 Absolute Indexed with X a,x
With the Absolute Indexed with X addressing mode, the X Index Register is added to the second and third bytes of the
instruction to form the 16-bits of the effective address.
Byte: 2 1 0
Instruction: ADH ADL OpCode
ADH ADL
+ X
Operand address: effective address
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4.4 Absolute Indexed with Y a, y
With the Absolute Indexed with Y addressing mode, the Y Index Register is added to the second and third bytes of the
instruction to form the 16-bit effective address.
Byte: 2 1 0
Instruction: ADH ADL OpCode
ADH ADL
+ Y
Operand address: effective address
4.5 Absolute Indirect (a)
With the Absolute Indirect addressing mode, the second and third bytes of the instruction form an address to a pointer. This
address mode is only used with the JMP instruction and the Program Counter is loaded with the first and second bytes at this
pointer.
Byte: 2 1 0
Instruction: ADH ADL OpCode
Indirect address: ADH ADL
New PC value: indirect address
4.6 Accumulator A
With Accumulator addressing the operand is implied as the Accumulator and therefore only a single byte forms the
instruction..
Byte: 2 1 0
Instruction:
OpCode
Operand: accumulator
4.7 Immediate Addressing #
With Immediate Addressing the operand is the second byte of the instruction.
Byte: 2 1 0
Instruction:
Operand OpCode
Operand: Operand
4.8 Implied i
Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction.
Byte: 2 1 0
Instruction:
OpCode
Operand address: implied
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4.9 Program Counter Relative r
The Program Counter relative addressing mode, sometimes referred to as Relative Addressing, is used with the Branch
instructions. If the condition being tested is met, the second byte of the instruction is added to the Program Counter and
program control is transferred to this new memory location.
Byte: 2 1 0
Instruction:
offset OpCode
PCH PCL
+ offset
New PC value effective address
4.10 Stack s
The Stack may use memory from 0100 to 01FF and the effective address of the Stack address mode will always be within
this range. Stack addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to
Subroutine, Return from Subroutine, Interrupts and Return from Interrupt.
Byte: 2 1 0
Instruction:
OpCode
Operand address: 1 S
4.11 Zero Page zp
With Zero Page (zp) addressing the second byte of the instruction is the address of the operand in page zero.
Byte: 2 1 0
Instruction:
zp OpCode
Operand address: 0 zp
4.12 Zero Page Indexed Indirect (zp,x)
The Zero Page Indexed Indirect addressing mode is often referred to as Indirect,X. The second byte of the instruction is the
zero page address to which the X Index Register is added and the result points to the low byte of the indirect address.
Byte: 2 1 0
Instru ction:
zp OpCode
Base Address: + zp
Indirect Address: 0 X
address
Operand address: indirect address
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4.13 Zero Page Indexed with X zp,x
With Zero Page Indexed with X addressing mode, the X Index Register is added to the second byte of instruction to form the
effective address.
Byte: 2 1 0
Instruction: OpCode
zp
Base Address: + zp
Operand Address: 0 X
effective address
4.14 Zero Page Indexed with Y zp, y
With Zero Page Indexed with Y addressing, the second byte of the instruction is the zero page address to which the Y Index
Register is added to form the page zero effective address.
Byte: 2 1 0
Instruction: OpCode
zp
Base Address: + zp
Operand Address: 0 Y
effective address
4.15 Zero Page Indirect (zp)
With Zero Page Indirect addressing mode, the second byte of the instruction is a zero page indirect address that points to the
low byte of a two byte effective address.
Byte: 2 1 0
Instruction:
zp OpCode
Indirect Address: 0 zp
Operand Address: indirect address
4.16 Zero Page Indirect Indexed with Y (zp), y
The Zero Page Indirect Indexed with Y addressing mode is often referred to as Indirect Y. The second byte of the instruction
points to the low byte of a two byte (16-bit) base address in page zero. Y Index Register is added to the base address to form
the effective address.
Byte: 2 1 0
Instruction:
zp OpCode
Indirect Base Address: 0 zp
indirect base address
+ Y
Operand Address: effective address
The Western Design Center, Inc. W65C02S Data Sheet 19
The Western Design Center, Inc.
W65C02S Data Sheet
Table 4-1 Addressing Mode Table
Address Mode Instruction Times in Memory Memory Utilization in Number of
Cycle Program Sequence Bytes
1. Absolute a
2. Absolute Indexed Indirect (a,x) Original W65C02S Original W65C02S
3. Absolute Indexed with X a,x NMOS 6502 NMOS 6502
4. Absolute Indexed with Y a,y
5. Absolute Indirect (a) 4 (3) 4 (3) 3 3
6. Accumulator A
7. Immediate # 5 5 3 3
8. Implied i
9. Program Counter Relative r 4 (1,3) 4 (1,3) 3 3
10. Stack s
11. Zero Page zp 4 (1) 4 (1) 3 3
12. Zero Page Indexed Indirect (zp,x)
13. Zero Page Indexed with X zp,x 4 (3) 4 (3) 3 3
14. Zero Page Indexed with Y zp,y
15. Zero Page Indirect (zp) 2 2 1 1
16. Zero Page Indirect Indexed with Y (zp),y
2 2 2 2
2 2 1 1
2 (2) 2 (2) 2 2
3-7 3-7 1-3 1-4
3 (3) 3 (3) 2 2
6 6 2 2
4 (3) 4 (3) 2 2
4 4 2 2
- 5 - 2
5 5 2 2
Notes: (indicated in parenthesis)
1. Page boundary, add 1 cycle if page boundary is crossed when forming address
2. Branch taken, add 1 cycle if branch is taken
3. Read-Modify-Write, add 2 cycles
The Western Design Center, Inc. W65C02S Data Sheet 20
The Western Design Center, Inc.
W65C02S Data Sheet
5 OPERATION TABLES
Table 5-1 Instruction Set Table
1. ADC ADd memory to accumulator with Carry 53. SED SEt Decimal mode
2. AND "AND" memory with accumulator 54. SEI SEt Interrupt disable status
3. ASL Arithmetic Shift one bit Left, memory or 55. SMB Set Memory Bit
accumulator 56. STA STore Accumulator in memory
4. BBR Branch on Bit Reset 57. STP SToP mode
5. BBS Branch of Bit Set 58. STX STore the X register in memory
6. BCC Branch on Carry Clear (Pc=0) 59. STY STore the Y register in memory
7. BCS Branch on Carry Set (Pc=1) 60. STZ STore Zero in memory
8. BEQ Branch if EQual (Pz=1) 61. TAX Transfer the Accumulator to the X register
9. BIT BIt Test 62. TAY Transfer the Accumulator to the Y register
10. BMI Branch if result MInus (Pn=1) 63. TRB Test and Reset memory Bit
11. BNE Branch if Not Equal (Pz=0) 64. TSB Test and Set memory Bit
12. BPL Branch if result PLus (Pn=0) 65. TSX Transfer the Stack pointer to the X register
13. BRA BRanch Always 66. TXA Transfer the X register to the Accumulator
14. BRK BReaK instruction 67. TXS Transfer the X register to the Stack pointer register
15. BVC Branch on oVerflow Clear (Pv=0) 68. TYA Transfer Y register to the Accumulator
16. BVS Branch on oVerflow Set (Pv=1) 69. WAI WAit for Interrupt
17. CLC CLear Cary flag Note: =New Instruction
18. CLD CLear Decimal mode
19. CLI CLear Interrupt disable bit
20. CLV CLear oVerflow flag
21. CMP CoMPare memory and accumulator
22. CPX ComPare memory and X register
23. CPY ComPare memory and Y register
24. DEC DECrement memory or accumulate by one
25. DEX DEcrement X by one
26. DEY DEcrement Y by one
27. EOR "Exclusive OR" memory with accumulate
28. INC INCrement memory or accumulate by one
29. INX INcrement X register by one
30. INY INcrement Y register by one
31. JMP JuMP to new location
32. JSR Jump to new location Saving Return (Jump to
SubRoutine)
33. LDA LoaD Accumulator with memory
34. LDX LoaD the X register with memory
35. LDY LoaD the Y register with memory
36. LSR Logical Shift one bit Right memory or accumulator
37. NOP No OPeration
38. ORA "OR" memory with Accumulator
39. PHA PusH Accumulator on stack
40. PHP PusH Processor status on stack
41. PHX PusH X register on stack
42. PHY PusH Y register on stack
43. PLA PuLl Accumulator from stack
44. PLP PuLl Processor status from stack
45. PLX PuLl X register from stack
46. PLY PuLl Y register from stack
47. RMB Reset Memory Bit
48. ROL ROtate one bit Left memory or accumulator
49. ROR ROtate one bit Right memory or accumulator
50. RTI ReTurn from Interrupt
51. RTS ReTurn from Subroutine
52. SBC SuBtract memory from accumulator with borrow
(Carry bit)
The Western Design Center, Inc. W65C02S Data Sheet 21
The Western Design Center, Inc., M M The Western Design Center, Inc.
S S Table 5-2 W65C02S OpCode Matrix
D W65C02S OpCode Matrix D
0 1 23 4 5 6 7 8 9 A B C D E F
0 BRK s ORA (zp,x) TSB zp ORA zp ASL zp RMB0 zp PHP s ORA # ASL A TSB a ORA a ASL a BBR0 r
6,3 5,3 0
7,1 6,2 5,2 3,2 5,2 5,2 3,1 2,2 2,1 6,3 4,3
1 BPL r ORA (zp),y ORA (zp) TRB zp ORA zp,x ASL zp,x RMB1 zp CLC i ORA a,y INC A TRB a ORA a,x ASL a,x BBR1 r
6,3 5,3 1
2,2 5,2 5,2 * 5,2 4,2 6,2 5,2 2,1 4,3 2,1 * 6,3 4,3
2 JSR a AND (zp,x) BIT zp AND zp ROL zp RMB2 zp PLP s AND # ROL A BIT a AND a ROL a BBR2 r
3,2 6,3 5,3 2
6,3 6,2 3,2 5,2 5,2 4,1 2,2 2,1 4,3 4,3
3 BMI r AND (zp),y AND (zp) BIT zp,x AND zp,x ROL zp,x RMB3 zp SEC i AND a,y DEC A BIT a,x AND a,x ROL a,x BBR3 r
6,3 5,3 3
2,2 5,2 5,2 * 4,2 * 4,2 6,2 5,2 2,1 4,3 2,1 * 4,3 * 4,3
4 RTI s EOR (zp,x) EOR zp LSR zp RMB4 zp PHA s EOR # LSR A JMP a EOR a LSR a BBR4 r
W65C02S Datasheet 3,2 6,3 5,3 4
6,1 6,2 5,2 5,2 3,1 2,2 2,1 3,3 4,3
5 BVC r EOR (zp),y EOR (zp) EOR zp,x LSR zp,x RMB5 zp CLI i EOR a,y PHY s EOR a,x LSR a,x BBR5 r
6,3 5,3 5
2,2 5,2 5,2 * 4,2 6,2 5,2 2,1 4,3 3,1 4,3
6 RTS s ADC (zp,x) STZ zp ADC zp ROR zp RMB6 zp PLA s ADC # ROR A JMP (a) ADC a ROR a BBR6 r
6,3 5,3 6
6,1 6,2 3,2 3,2 5,2 5,2 4,1 2,2 2,1 6,3 4,3
7 BVS r ADC (zp),y ADC (zp) STZ zp,x ADC zp,x ROR zp,x RMB7 zp SEI i ADC a,y PLY s JMP (a,x) ADC a,x ROR a,x BBR7 r
5,3 7
2,2 5,2 5,2 * 4,2 4,2 6,2 5,2 2,1 4,3 4,1 6,3 * 4,3 6,3
8 BRA r STA (zp,x) STY zp STA zp STX zp SMB0 zp DEY i BIT # TXA i STY a STA a STX a BBS0 r
3,2 3,2 2,1 4,3 5,3 8
3,2 6,2 3,2 5,2 2,1 2,2 4,3 4,3
9 BCC r STA (zp),y STA (zp) STY zp,x STA zp,x STX zp,y SMB1 zp TYA i STA a,y TXS i STZ a STA a,x STZ a,x BBS1 r
5,3 5,3 9
2,2 6,2 5,2 * 4,2 4,2 4,2 5,2 2,1 5,3 2,1 4,3 4,3
A LDY # LDA (zp,x) LDX # LDY zp LDA zp LDX zp SMB2 zp TAY i LDA # TAX i LDY a LDA a LDX a BBS2 r
2,1 4,3
2,2 6,2 2,2 3,2 3,2 3,2 5,2 2,1 2,2 4,3 4,3 5,3 A
TSX i LDX a,y
B BCS r LDA (zp),y LDA (zp) LDY zp,x LDA zp,x LDX zp,y SMB3 zp CLV i LDA a,y 2,1 LDY a,x LDA a,x 4,3 BBS3 r
2,2 5,2 5,2 * 4,2 4,2 4,2 5,2 2,1 4,3 4,3 4,3 5,3 B
C CPY # CMP (zp,x) CPY zp CMP zp DEC zp SMB4 zp INY i CMP # DEX i WAI i CPY a CMP a DEC a BBS4 r
3,2 3,2 5,2 6,3 5,3 C
2,2 6,2 5,2 2,1 2,2 2,1 3,1 4,3 4,3
CMP zp,x DEC zp,x
BNE r CMP (zp),y CMP (zp) 4,2 6,2 SMB5 zp CLD i CMP a,y PHX s STP i CMP a,x DEC a,x BBS5 r
D 6,3 5,3 D
2,2 5,2 5,2 * 5,2 2,1 4,3 3,1 3,1 4,3 W65C02S Datasheet
E CPX # SBC (zp,x) CPX zp SBC zp INC zp SMB6 zp INX i SBC # NOP i CPX a SBC a INC a BBS6 r
3,2 3,2 6,3 5,3 E
2,2 6,2 5,2 5,2 2,1 2,2 2,1 4,3 4,3
F BEQ r SBC (zp),y SBC (zp) SBC zp,x INC zp,x SMB7 zp SED i SBC a,y PLX s SBC a,x INC a,x BBS7 r
6,3 5,3 F
2,2 5,2 5,2 * 4,2 6,2 5,2 2,1 4,3 4,1 4,3
0 1 23 4 5 6 7 8 9 A B C D E F
22
* = Old instruction with new addressing modes
= New Instruction
The Western Design Center, Inc. W65C02S Datasheet
6 DC, AC AND TIMING CHARACTERISTICS
Table 6-1 Absolute Maximum Ratings
Rating Symbol Value
Supply Voltage VDD -0.3 to +7.0V
Input Voltage VIN -0.3 to VDD +0.3V
Storage Temperature TS -55C to +150C
This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken
to avoid application of voltages higher than the maximum rating.
Note: Exceeding these ratings may result in permanent damage. Functional operation under these conditions is not implied.
The Western Design Center, Inc. W65C02S Datasheet 23
The Western Design Center, Inc.
W65C02S Datasheet
6.1 DC Characteristics TA = -40C to +85C (PLCC, QFP) TA= 0C to 70C (DIP)
Table 6-2 DC Characteristics
Symbol 5.0 +/ - 5% 3.3 +/ - 10% 3.0 +/- 5% 2.5 +/ - 5% 1.8 +/ - 5% Units
V
Min Max Min Max Min Max Min Max Min Max
VDD Supply Voltage 4.75 5.25 3.0 3.6 2.85 3.15 2.37 2.63 1.71 1.89
Vih
Input High Voltage (1) VDDx0.7 VDD+0.3 VDDx0.7 VDD+0.3 VDDx0.7 VDD+0.3 VDDx0.7 VDD+0.3 VDDx0.7 VDD+0.3 V
Vil BE, D0-D7, RDY, SOB VDD-0.4 VDD+0.3 VDD-0.4 VDD+0.3 VDD-0.4 VDD+0.3 VDD-0.4 VDD+0.3 VDD-0.4
Iin IRQB, NMIB, PHI2, RESB VDD+0.3
Ipup Input Low Voltage (1) VSS-0.3 VDDx0.3 VSS-0.3
BE, D0-D7, RDY, SOB, VSS-0.3 VDDx0.3 VSS-0.3 VDDx0.3 VSS-0.3 VSS+0.4 VSS-0.3 VDDx0.3 VSS-0.3 VDDx0.3 V
IRQB, NMIB, PHI2, RESB VSS+0.4 VSS-0.3 VSS+0.4 VSS-0.3 VSS-0.3 VSS+0.4
Input Leakage Current (Vin=0.4 to 2.4, VDD=max) -20 20 -20 VSS+0.1
BE, IRQB, NMIB, PHI2, RESB, SOB 20 -20 20 -20 -20 20
-1 -10 20 nA
RDY Input Pull-UP Current (Vin=VDD-0.4V (min)
Vin=0.4(max)) -20 -1 -20 -1 -1 -10 -0.25 -2.0 A
-20
Iin D0-D7 (off state) -20 20 -20 20 -20 20 -20 20 20 nA
Output High current (Voh=VDD-.4, VDD=min)
Ioh A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB, SYNC, 700 - 350 - 300 - 200 - 100 - uA
VPB
Output Low current (Vol=0.4, VDD=min)
Iol A0-A15, D0-D7, MLB, PHI1O, PHI2O, RWB, SYNC, 1.6 - 1.6 - 1.6 - 1.0 - 0.5 - mA
VPB
Idd Supply Current (with Tester Loading) - 1.5 - 1.0 - 1.0 - 0.75 - 0.5 mA/
Supply Current (Core)
- 0.5 - 0.3 - 0.25 - 0.2 - 0.15 MHz
Isby Standby Current Outputs Unloaded - 1 - 1 - 1 - 1 - 1 uA
BE, IRQB, NMIB, PHI2, SOB=VDD
*Capacitance (Vin=0V, TA=25C, f-1MHz)
Cin BE, IRQB, NMIB, PHI2, RESB, RDY, SOB - 5 - 5 - 5 - 5 - 5 pF
Cts A0-A15, D0-D7, RWB
*Not insp ected during production test; verified on a sample basis.
(1) For high speed tests, Vih and Vil are set for VDD-.2v and VSS+.2V. The input "1" and "0" thresholds are tested at 1 MHz.
1.2 6.0
1.1 1 MHz Operation@85C 5.5
5.0 Typical 0.6u processed device @85C
1.0 Typical 0.6u processed device
Idd (mA)
Vdd (VOLTS)
0.9 (With tester loading) 4.5
0.8 (CORE power only)
4.0
0.7 3.5
0.6 3.0
2.5
0.5
0.4 2.0
0.3 1.5
0.2 1.0
0.1 0.0
0 2 4 6 8 10 12 14 16 18 20
0.0 1 2 4
0 3 5 6 F Max (MHz)
Vdd (VOLTS)
Figure 6-1 Idd vs Vdd Figure 6-2 F Max vs Vdd
The Western Design Center, Inc. W65C02S Datasheet 24
The Western Design Center, Inc.
W65C02S Datasheet
6.2 AC Characteristics TA = -40C to +85C (PLCC, QFP) TA= 0C to 70C (DIP)
Table 6-3 AC Characteristics
Symbol Parameter 5.0 +/-5% 3.3 +/-10% 3.0 +/-5% 2.5 +/-5% 1.8 +/-5% Units
14MHz 8MHz 8MHz 4MHz 2MHz
VDD Supply Voltage Min Max V
tACC Access Time Min Max Min Max Min Max Min Max nS
tAH Address Hold Time 4.75 5.25 nS
tADS Address Setup Time 3.0 3.6 2.85 3.15 2.375 2.675 1.71 1.89 nS
tBVD BE to Valid Data (1) nS
CEXT Capacitive Load (2) 30 - 70 - 70 - 145 - 290 - pF
tPWH Clock Pulse Width High nS
tPWL Clock Pulse Width Low 10 - 10 - 10 - 10 - 10 - nS
tCYC Cycle Time (3) nS
t F,tR Fall Time, Rise Time - 30 - 40 - 40 - 75 - 150 nS
tPCH Processor Control Hold Time nS
tPCS Processor Control Setup Time - 25 - 30 - 30 - 30 - 30 nS
tDHR Read Data Hold Time nS
tDSR Read Data Setup Time - 35 - 35 - 35 - 35 - 35 nS
tMDS Write Data Delay Time nS
tDHW Write Data Hold Time 35 - 62 - 62 - 125 - 250 - nS
35 - 63 - 63 - 125 - 250 -
70 - 125 - 125 - 250 - 500 -
- 5 - 5 - 5 - 5 - 5
10 - 10 - 10 - 10 - 10 -
10 - 15 - 15 - 30 - 60 -
10 - 10 - 10 - 10 - 10 -
10 - 15 - 15 - 30 - 60 -
- 25 - 40 - 40 - 70 - 140
10 - 10 - 10 - 10 - 10 -
1. BE to High Impedance State is not testable but should be the same amount of time as BE to Valid Data
2. ATE or loading on all outputs
3. Since this is a static design, the maximum cycle time could be infinite.
The Western Design Center, Inc., W65C02S Datasheet 25
The Western Design Center, Inc.
W65C02S Datasheet
tF tR
PHI2
tPWL tPWH
tAH tAH
tADS
see note 1
A0-A15. MLB,
R/W, SYNC, VPB
tACC tDSR
Read Data tDHR tMDS tDHR
Write Data tDHW tDHW
SOB Write Data
IRQB, NMIB tPCS
RDY, RESB
tPCH
tPCH
tPCS
SOB
DATA
tBVD
Figure 6-3 General Timing Diagram
Timing Notes:
1. Timing measurement points are 50% VDD.
2. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for system time base and PHI2
processor input clock.
The Western Design Center, Inc. W65C02S Datasheet 26
The Western Design Center, Inc. W65C02S Datasheet
The page left blank intentionally
The Western Design Center, Inc. W65C02S Datasheet 27
The Western Design Center, Inc.
Table 6-4 Operation, Operation Codes and Status Register
MnemomicOperation
a# Immediate Data
(a,x)~ NOT
a,x^ AND
a,yv OR
(a)v Exclusive OR
AA+M+CA
#A^MA
iC 7 6 5 4 3 2 1 0 0
rBranch on bit 0 reset
sBranch on bit 1 reset
zpBranch on bit 2 reset
(zp,x)Branch on bit 3 reset
zp,xBranch on bit 4 reset
zp,yBranch on bit 5 reset
(zp)Branch on bit 6 reset
(zp),yBranch on bit 7 reset
Branch on bit 0 set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Branch on bit 1 set
ADC Branch on bit 2 set 6D 7D 79 69 65 61 75 72 71
AND Branch on bit 3 set 25 21 35 32 31
ASL Branch on bit 4 set 2D 3D 39 29
BBR0 Branch on bit 5 set
BBR1 Branch on bit 6 set 0E 1E 0A 06 16
BBR2 Branch on bit 7 set
BBR3 Branch C = 0 0F
BBR4 Branch if C = 1 1F
BBR5 Branch if Z = 1
BBR6 A^M 2F
BBR7 Branch if N = 0
BBS0 Branch if Z = 0 3F
BBS1 Branch if N = 0 4F
BBS2 Branch Always
BBS3 5F
BBS4
BBS5 6F
BBS6 7F
BBS7
BCC 8F
BCS
BEQ 9F
BIT AF
BMI
BNE BF
BPL
BRA CF
DF
EF
FF
90
B0
F0
2C 3C 89 24 34
30
D0
10
80
The Western Design Center, Inc. W65C02S Datasheet
The Western Design Center, Inc.
MnemomicOperation
a# Immediate Data
(a,x)~ NOT
a,x^ AND
a,yv OR
(a)v Exclusive OR
ABreak
#Branch if V = 0
iBranch if V = 1
r
sC0
zp0 D
(zp,x)01
zp,x0V
zp,yA-M
(zp)X-M
(zp).yY-M
Decrement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BRK X-1 A 00
BVC Y-1 Y 50
BVS
CLC AvM A 70
CLD
CLI Increments 18
CLV
CMP X+1 X D8
CPX Y+1 Y
CPY Jump to new location 58
DEC Jump to Subroutine
DEX B8
DEY MA
EOR M X CD DD D9 C9 C5 C1 D5 D2 D1
INC MY
INX 07 6 5 4 3 2 1 0C EC E0 E4
INY No Operation
JMP CC C0 C4
JSR
LDA CE DE 3A C6 D6
LDX
LDY CA
LSR
NOP 88
4D 5D 59 49 45 41 55 52 51
EE FE 1A E6 F6
E8
C8
4C 7C 6C
20
AD BD B9 A9 A5 A1 B5 B2 B1
AE BE A2 A6 B6
AC BC A0 A4 B4
4E 5E 4A 46 56
EA
The Western Design Center, Inc. W65C02S Datasheet
The Western Design Center, Inc.
MnemomicOperat ion
a# Immediate Data
(a,x)~ NOT
a,x^ AND
a,yv OR
(a)v Exclusiv e OR
A
#A V MA
iA Ms, S -1 S
rP Ms, S-1 S
sX Ms, S -1 S
zpY Ms, S -1 S
(zp,x)S + 1 S, Ms A
zp,xS + 1 S, Ms P
zp,yS + 1 S, Ms X
(zp)S + 1 S, Ms Y
(zp),yReset Memory Bit 0
Reset Memory Bit 1 1 2 34 5 678 9 10 11 12 13 14 15 16
Reset Memory Bit 2
ORA Reset Memory Bit 3 0D 1D 19 09 05 01 15 12 11
PHA Reset Memory Bit 4
PHP Reset Memory Bit 5 48
PHX Reset Memory Bit 6
PHY Reset Memory Bit 7 08
PLA C7 6 5 4 3 2 1 0 C
PLP C7 6 5 4 3 2 1 0 C DA
PLX Return from Interrupt
PLY Return from Subroutine 5A
RMB0 A - M - (~C) A
RMB1 1C 68
RMB2 1D
RMB3 28
RMB4
RMB5 FA
RMB6
RMB7 7A
ROL
2E 3E 2A 26 36
ROR
RTI 6E 7E 6A 66 76
RTS
SBC 40
SEC
SED 60
ED FD F9 E9 E5 E1 F5 F2 F1
38
F8
The Western Design Center, Inc. W65C02S Datasheet
The Western Design Center, Inc.
MnemomicOperation
# Immediate Data
a~ NOT
(a,x)^ AND
a,xv OR
a,yv Exclusive OR
(a)
A1I
#
iSet Memory Bit 0
rSet Memory Bit 1
sSet Memory Bit 2
zpSet Memory Bit 3
(zp,x)Set Memory Bit 4
zp,xSet Memory Bit 5
zp,ySet Memory Bit 6
(zp)Set Memory Bit 7
(zp),y
AM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
STOP (1 PHI2)
SEI X M 78
SMB0 YM 87
SMB1 00 M
SMB2 AY 97
SMB3 AX
SMB4 ~A^M M A7
SMB5 AVM M
SMB6 S X B7
SMB7 X A
STA X S C7
STP YA
STX 0 RDY D7
STY
STZ E7
TAX
TAY F7
TRB
TSB 8D 9D 99 85 81 95 92 91
TSX
TXA DB
TXS
TYA 8E 86 96
WAI
8C 84 94
9C 9E 64 74
AA
AB
1C 14
0C 04
BA
8A
9A
98
CB
The Western Design Center, Inc. W65C02S Datasheet
The Western Design Center, Inc.
W65C02S Datasheet
Table 6-5 Instruction Timing Chart
Address Mode Note Cycle VPB MLB SYNC Address Bus Data Bus RWB
1a. Absolute a
ADC, AND, BIT, CMP, CPX, CPY, EOR, 1 1 1 1 PC OpCode 1
LDA, LDX, LDY, ORA, SBC, STA, STX, PC+1 AAL 1
STY, STZ (6) 2 1 1 0 PC+2 AAH 1
16 OpCodes, 3 bytes, 4&5 cycles AA Data 1/0
1b. Absolute (R-M-W) a 3 1 1 0
ASL, DEC, INC, LSR, ROL, ROR, TRB, OpCode 1
TSB 4 1 1 0 AAL 1
8 OpCodes, 3 bytes, 6 cycles AAH 1
1 1 1 1 PC Data 1
1c. Absolute (JUMP) a PC+1 IO 1
JMP (4C) 2 1 1 0 PC+2 Data 0
1 OpCode, 3 bytes, 3 cycles AA
3 1 1 0 AA OpCode 1
1d. Absolute (JUMP to subroutine) a AA New PCL 1
JSR (20) 4 1 0 0 New PCH 1
1 OpCode, 3 bytes, 3 cycles PC New OpCode 1
(different order from N6502) 5 1 0 0 PC+1
PC+2 OpCode 1
2. Absolute Indexed Indirect (a, x) 6 1 0 0 New PC New PCL 1
JMP (7C) IO 1
1 OpCode, 3 bytes, 6 cycles 1 1 1 1 PC PCH 0
PC+1 PCL 0
3a. Absolute , X a, x 2 1 1 0 S New PCH 1
ADC, AND, BIT, CMP, EOR, LDA, LDY, S New OpCode 1
ORA, SBC, STA, STZ 3 1 1 0 S+1 OpCode 1
11 OpCodes, 3 bytes, 4,5 and 6 cycles PC+2 AAL 1
3b. Absolute, X(R-M-W) a, x 1 1 1 1 New PC AAH 1
ASL, DEC, INC, LSR, ROL, ROR PC IO 1
6 OpCodes, 3 bytes, 7 cycles 1 1 1 1 PC+1 New PCL 1
PC+2 New PCH 1
4. Absolute, Y a, y 2 1 1 0 PC+2 OpCode 1
ADC, AND, CMP, EOR, LDA, LDX, ORA, AA+X
SBC, STA 3 1 1 0 AA+X+1 OpCode 1
9 OpCodes, 3 bytes, 4,5 and 6 cycles New PC AAL 1
5. Absolute Indirect (a) 4 1 1 0 AAH 1
JMP (6C) PC Data 1/0
1 OpCode, 3 bytes, 6 cycles 5 1 1 0 PC+1
PC+2 OpCode 1
6. Accumulator A 6 1 1 0 AA+X AAL 1
ASL, DEC, INC, LSR, ROL, ROR AAH 1
6 OpCodes, 1 byte, 2 cycles 1 1 1 1 PC IO 1
7. Immediate # PC+1 Data 1
ADC, AND, BIT, CLR, CMP, CPY, CPX, 1 1 1 1 PC+2 IO 1
EOR, LDA, LDX, LDY, ORA, SBC AAH,AAL+X Data 0
13 OpCodes, 2 bytes, 2 and 5 cycles 2 1 1 0 AA+X OpCode 1
8a. Implied i AA+X+1 AAL 1
CLC, CLD, CLI, CLV, DEX, DEY, INX, (1) 3 1 1 0 AA+X AAH 1
INY, NOP, SEC, SED, SEI, TAX. TAY, PC Data 1/0
TXA. TSX. TXS, TYA 4 1 1 0 PC+1 OpCode 1
18 OpCodes, 1 byte, 2 cycles PC+2 AAL 1
5 1 1 0 AA+Y AAH 1
PC IO 1
6 1 1 0 PC+1 New PCL 1
PC+2 New PCH 1
1 1 1 1 PC+2 OpCode 1
0,AA
1 1 1 1 0,AA+1 OpCode 1
New PC IO 1
2 1 1 0
PC OpCode 1
(1) 3 1 1 0 PC+1 ID 1
(6) 4 1 1 0
(1) 1 1 1 1
2 1 1 0
3 1 1 0
4 1 1 0
5 1 0 0
6 1 0 0
7 1 0 0
1 1 1 1
(1) 2 1 1 0
(6) 3 1 1 0
4 1 1 0
1 1 1 1
2 1 1 0
3 1 1 0
4 1 1 0
5 1 1 0
6 1 1 0
1 1 1 1
1 1 1 1
2 1 1 0
1 1 1 1 PC
PC+1
(6) 2 1 1 0
1 1 1 1 PC OpCode 1
PC+1
2 1 1 0 IO 1
The Western Design Center, Inc. W65C02S Datasheet 32
The Western Design Center, Inc.
W65C02S Datasheet
Address Mode Note Cycle VPB MLB SYNC Address Bus Data Bus RWB
8b. Stop the Clock i 1 1 1 1 PC OpCode 1
STP 1 0 PC+1 IO 1
1 OpCode, 1 byte, 3 cycles 2 1 1 0 PC+1 IO 1
1 0 PC+1 RES(BRK) 1
3 1 1 0 PC+1 RES(BRK) 1
1 0 PC+1 RES(BRK) 1
RESB=1 1c 1 1 1 PC+1 BEGIN 1
RESB=0
1b 1 1 1 PC OpCode 1
RESB=0 1 0 PC+1 IO 1
RESB=1 1a 1 1 0 PC+1 IO 1
1 1 PC+1 IRQ(BRK) 1
1 1
1 1 PC OpCode 1
8c. Wait for Interrupt i 1 1 1 0 PC+1 Offset 1
1 1 New PC OpCode 1
WAI (4) 2 1
1 1 PC OpCode 1
1 OpCode, 1 byte, 3 cycles 3 1 1 0 PC+1 zp 1
1 0 0,zp Data 1
IRQB NMIB 1 1 1 0 PC+2 Offset 1
1 0 PC+Offset New OpCode 1
9a. Relative r 1 1 1 1 PC not used 1
BCC, BCS, BEQ, BMI, BNE, BPL, 1 0 PC not used 1
(2) 2 1 1 0 01,S Return PCH 0
BRA, BVC, BVS 1 0 01,S-1 Return PCL 0
9 OpCodes, 2 bytes, 2,3 and 4 cycles (3) 1 1 1 0 01,S-2 Return P 0
1 0 VA New PCL 1
9b. Relative Bit Branch r (2) 1 1 1 0 VA+1 New PCH 1
1 1 New PC New OpCode 1
BBRx, BBSx (3) 2 1 1 1 PC OpCode 1
1 0 PC+1 not used 1
16 OpCodes, 3 bytes, 5,6 and 7 cycles 3 1 1 0 S Return PCH 0
1 0 S-1 Return PCL+2 0
4 1 1 0 S-2 Return P 0
1 0 VA New PCL 1
5 1 1 1 VA+1 New PCH 1
New PC New OpCode 1
10a. Stack s 1 1 1 1 PC OpCode 1
1 0 PC+1 Not Used 1
ABORTB, IRQB, NMIB, RESB 2 1 1 0 S+1 Return P 1
1 0 S+2 Return PCL 1
4 hardware interrupts, 0 bytes, 7 cycles 3 1 1 0 S+3 Return PCH 1
1 0 PC+1 IO 1
(5) 4 1 1 1 Return PC New OpCode 1
5 1 1 1 PC OpCode 1
1 0 PC+1 not used 1
6 0 1 0 PC+1 not used 1
1 0 S+1 Return PCL 1
7 0 1 0 S+2 Return PCH 1
1 0 PC+1 IO 1
1 1 1 1 Return PC New OpCode 1
1 1 PC OpCode 1
10b. Stack (Software Interrupts) s 1 1 1 0 PC+1 not used 1
1 0 S Register Value 0
BRK 2 1 1 1 PC+1 New OpCode 1
1 1 PC OpCode 1
1 OpCode, 2 bytes, 7 cycles 3 1 1 0 PC+1 not used 1
1 0 PC+1 not used 1
4 1 1 0 S+1 Register Value 1
1 1 PC+1 New OpCode 1
5 1
1 1 PC OpCode 1
6 0 1 0 PC+1 zp 1
1 0 0,zp Data 1/0
7 1 1 1 PC+2 New OpCode 1
1
10c. Stack (Return from interrupt) s 1 1
RTI 2 1
1 OpCode, 1 byte, 6 cycles 3 1
4 1
5 1
6 1
1 1
10d. Stack (Return from subroutine) s 1 1
RTS
1 OpCode, 1 byte, 6 cycles 2 1
10e. Stack s 3 1
PHA, PHP, PHX, PHY
4 OpCodes, 1 byte, 3 cycles 4 1
10f. Stack s 5 1
PLA, PLP, PLX, PLY
4 OpCodes, 1 byte, 4 cycles 6 1
1 1
1 1
2 1
3 1
1 1
1 1
2 1
3 1
4 1
1 1
11a. Zero Page zp 1 1
ADC, AND, BIT, CMP, CPX, CPY,
EOR, LDA, LDX, LDY, ORA, SBC, 2 1
STA, STX, STY, STZ
16 OpCodes, 2 bytes, 3 and 4 cycles 3 1
1 1
The Western Design Center, Inc. W65C02S Datasheet 33
The Western Design Center, Inc.
W65C02S Datasheet
Address Mode Note Cycle VPB MLB SYNC Address Bus Data Bus RWB
11b. Zero Page zp 1 1 1 1 PC OpCode 1
1 0 PC+1 zp 1
ASL, DEC, INC, ROL, ROR, TRB, TSB 2 1 0 0 PC+1 Data 1
7 OpCodes 0 0 zp not used 1
3 1 0 0 zp Data 0
1 1 PC+2 New OpCode 1
4 1 1 1 PC OpCode 1
1 0 PC+1 zp 1
5 1 1 0 zp Data 1
1 0 zp not used 1
1 1 1 0 zp Data 0
11c. Zero Page zp 1 1 1 1 PC OpCode 1
1 0 PC+1 zp 1
RMBx, SMBx 2 1 1 0 zp Data 1
16 OpCodes, 2 bytes, 5 cycles 1 0 PC+2 Offset 1
3 1 1 0 PC+3 not used 1
1 1 PC+2+0Offset New OpCode 1
4 1
1 1 PC OpCode 1
5 1 1 0 PC+1 zp 1
1 0 PC+1 not used 1
11d. Zero Page zp 1 1 1 0 0,zp+X Indirect address 1
BBRx, BBSx 1 0 Indirect address Data 1
2 1 1 1 PC+1 New OpCode 1
16 OpCodes, 3 bytes, 5 cycles 3 1 1 1 PC OpCode 1
1 0 PC+1 zp 1
4 1 1 0 PC+1 not used 1
1 0 0,zp+X Data 1/0
5 1 1 1 PC+1 New OpCode 1
1 1 PC OpCode 1
1 1 1 0 PC+1 zp 1
1 0 PC+1 not used 1
12. Zero Page Indexed Indirect (zp,x) 1 1 0 0 0,zp+X Data 1
ADC, AND, CMP, EOR, LDA, ORA, 0 0 0,zp+X not used 1
SBC, STA 2 1 0 0 0,zp+X Data 0
1 1 PC+1 New OpCode 1
3 1
1 1 PC OpCode 1
8 OpCodes, 1 byte, 5 cycles 4 1 1 0 PC+1 zp 1
1 0 PC+1 not used 1
5 1 1 0 0,zp+Y Data 1/0
1 1 PC+1 New OpCode 1
1 1 1 1 PC OpCode 1
1 0 PC+1 zp 1
13a. Zero Page Indexed with X zp,x 1 1 1 0 0,zp Indirect address 1
ADC, AND, BIT, CMP, EOR, LDA, 1 0 Indirect address Data 1/0
ORA, LDY, SBC, STA, STY, STZ 2 1 1 1 PC+1 New OpCode 1
12 OpCodes, 1 byte, 4 cycles 1 1 PC OpCode 1
3 1 1 0 PC+1 zp 1
1 0 0,zp Indirect address HIGH 1
4 1 1 0 0,zp+1 Indirect address LOW 1
1 0 Indirect address+y Data 1/0
1 1 1 0 PC+2 New OpCode I
13b. Zerp Page Indexed with X zp,x 1 1
ASL, DEC, INC, LSR, ROL, ROR
6 OpCodes, 1 byte, 6 cycles 2 1
3 1
4 1
5 1
6 1
1 1
14. Zero Page Indexed with Y zp,y 1 1
ADC, AND, CMP, EOR, LDA, LDX,
ORA, SBC, STA, STX 2 1
10 OpCodes, 1 byte, 4 cycles
3 1
4 1
1 1
15. Zero Page Indirect (zp) 1 1
ADC, AND, CMP, EOR, LDA, ORA,
2 1
SBC, STA 3 1
8 OpCodes, 1 byte, 4 cycles
4 1
1 1
16.. Zero Page Indirect Indexed with y 1 1
(zp),y 2 1
ADC, AND, CMP, EOR, LDA, ORA, 3 1
SBC, STA (6) 4 1
8 OpCodes, 1 byte, 4, 5 and 6 cycles (1) 5 1
5a 1
The Western Design Center, Inc. W65C02S Datasheet 34
The Western Design Center, Inc.
W65C02S Datasheet
Notes:
1. Add 1 cycle for indexing across page boundaries, or write. This cycle contains invalid addresses.
2. Add 1 cycle if branch is taken.
3. Add 1 cycle if branch is taken across page boundaries.
4. Wait at cycle 2 for 2 cycles after NMIB or IRQB active input.
5. RWB remains high during Reset.
6. Add 1 cycle for decimal mode
AAH Absolute Address PC Program Counter
AAH Absolute Address High PCH Program Counter High
AAL Absolute Address Low PCL Program Counter Low
AAVH Absolute Address Vector High R-M -W Read-Modify -Write
AAVL Absolute Address Vector Low REG Register
C Accumulator S Stack Address
DEST Destination SRC Source
ID Immediate Data SO Stack Offset
IO Internal Operation V Vector Address
P Status Register x,y Index Register
zp Zero Page Address
The Western Design Center, Inc. W65C02S Datasheet 35
The Western Design Center, Inc. W65C02S Datasheet
7 CAVEATS
Table 7-1 Microprocessor Operational Enhancements
Function NMOS 6502 W65C02S
Indexed addressing across page Extra read of invalid address. Extra read of last instruction byte.
boundary
Execution of invalid OpCodes. Some terminate only by reset. All are NOP's (reserved for future use).
Results are undefined.
Jump indirect, operand = XXFF. OpCode Bytes Cycles
Page address does not increment.
Read/Modify/Write instruction at One read and two write cycles. 02,22,42,62,82 2 2
effective address.
Decimal flag. C2, E2
Flags after decimal operation. X3,OB-BB,EB,FB 1 1
Interrupt after fetch of BRK
instruction 44 2 3
Ready.
Read/Modify/Write instructions 54,D4,F4 2 4
absolute indexed in same page.
Oscillator. 5C 3 8
Assertion of Ready (RDY) during DC,FC 3 4
write operations.
Clock inputs. Page address increments, one additional
Unused input-only pins. cycle.
Two read and one write cycle.
Indeterminate after reset. Initialized to binary mode (D=0) after reset
and interrupts.
Invalid N, V and Z flags.
Interrupt vector is loaded; BRK Valid flags. One additional cycle.
vector is ignored.
Input. BRK is executed, and then interrupt is
Seven cycles. executed.
Bi-directional, WAI instruction pulls low.
Six cycles.
Requires external active components. Crystal or RC network will oscillate when
connected between PHI2 and PHI10.
Ignored. Stops processor during PHI2, and WAI
instruction pulls RDY low.
PHI2 is the only required clock. PHI2 is the only required clock.
Must be tied to VDD. Must be tied to VDD.
The BRK instruction for both the NMOS 6502 and 65C02 is a 2 byte instruction. The NMOS and CMOS devices
simply skips the second byte (i.e. doesn't care about the second byte) by incrementing the program counter twice.
It is important to realize that if a return from interrupt is used it will return to the location after the second or
signature byte.
The Western Design Center, Inc. W65C02S Datasheet 36
The Western Design Center, Inc. W65C02S Datasheet
8 W65C02DB DEVELOPER BOARD AND
IN-CIRCUIT EMULATOR (ICE)
MEMORY BUS
EPROM
CONTROL BUS
ADDRESS BUSS
DATA BUSS
CHIP SET
PHI2 RAM
OSCILLATOR I/O PORTS
MPU PC
PARALLEL PORT
RESET RESB
CIRCUIT
JTAG PLD I/O MATRIX
I/O
PROGRAMABLE I/O BUSS
The W65C02DB is used for W65C02 core microprocessor System-Chip Development, W65C02S (chip) System
Development, or Embedded W65C02DB (board) Development.
The Western Design Center, Inc. W65C02S Datasheet 37
The Western Design Center, Inc.
W65C02S Datasheet
8.1 Features:
W65C02S 8-bit MPU, total access to all control lines, Memory Bus, Programmable I/O Bus, PC Interface, 20 I/O lines, easy
oscillator change, 32K SRAM, 32K EPROM, W65C22S Versatile Interface Adapter VIA peripheral chip, on-board matrix,
CPLD for Memory map decoding, hardware breakpoints and ASIC design.
The CPLD chip is a XILINX XC95108 for changing the chip select and I/O functions if required. To change the CPLD chip
to suit your own setup, you need XILINX Data Manager for the XC95108 CPLD chip. The W65C02DB includes an on-
board programming header for JTAG configuration. For more details refer to the circuit diagram. The on-board W65C02S
and the W65C22S devices have measurement points for core power consumption. Power input is provided by an optional
power board which plugs into the 10 pin power header.
An EPROM programmer or an EPROM emulator is required to reprogram the EPROM. WDC's (W65SDS) Software
Development System includes a W65C02S Assembler and Linker, W65C02S C-Compiler and Optimizer, and W65C02S
Simulator/Debugger. WDC's PC IO daughter board can be used to connect the Developer Board to the parallel port of a PC
for In-Circuit Debugging.
8.2 Memory map:
CS1B: 8000-FFFF EPROM (27C256)
CS3B: SRAM (62C256)
CS2B: 0000-00EF & 0100-7FFF VIA(W65C22S)
00F0-00FF
8.3 Cross-Debugging Monitor Program
The Cross-Debugging Monitor Programs of the Developer Boards are located in the directory
:\WDC_SDS\DEBUG\WDCMON\
This directory contains the source and the batch files for all of the monitor programs. These programs can be burned into an
EPROM and used with the WDC evaluation boards (Developer Boards) and the WDC IO (or ZIO-1) daughter board to
interface to the parallel port of a PC. Then, the WDCDB.EXE debugger can be used to download programs, single step, set
breakpoints, examine memory, etc for In-Circuit Debugging (ICD).
The monitors have been designed to run correctly with a W65C02 MPU (WDCMON_1), W65C816 MPU (WDCMON_2),
W65C134 MCU (WDC134), or W65C265 MCU (WDC265). It detects the appropriate CPU type on RESET and operates
accordingly.
8.4 BUILDING
The batch files assemble the program and link it producing Motorola S-Record output. This can be changed by using a
different option with the WDCLN linker
The Western Design Center, Inc. W65C02S Datasheet 38
The Western Design Center, Inc. W65C02S Datasheet
9 HARD CORE MODEL
9.1 Features of the W65C02S Hard Core Model
The W65C02S core uses the same instruction set as the W65C02S.
The only functional difference between the W65C02S and W65C02S core is the RDY pin. The W65C02S RDY pin is
bi-directional utilizing an active pull-up. The W65C02S core RDY function is split into 2 pins, RDY, WAITN and
WAITP. The WAITN output goes low and WAITP goes high when a WAI instruction is executed.
The ESD and latch-up buffers have been removed.
The output from the core is the buffer N-channel and the P-channel transistor drivers.
The following inputs, if not used, must be pulled to the high state: RDY, IRQB, NMIB, BE and SOB.
The timing of the W65C02S core is the same as the W65C02S.
10 SOFT CORE RTL MODEL
10.1 W65C02 Synthesizable RTL-Code in Verilog HDL
The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model is equivalent to
the original W65C02S hardcore. The W65C02 RTL-Code is available as the core model and the W65C02S standard chip
model. The standard chip model includes the soft-core and the buffer ring in RTL-Code.
The Western Design Center, Inc. W65C02S Datasheet 39
The Western Design Center, Inc. W65C02S Datasheet
ORDERING INFORMATION
W65C02S6PL-14
Description W65C
W65C = standard product
Product Identification Number 02S
Foundry Process 6
Blank = 1.2u
8=.8u, 6=.6u
Package PL
P = Plastic Dual-In-Line, 40 pins
PL = Plastic Leaded Chip Carrier, 44 pins
Q = Quad Flat Pack, 44 pins
Temperature/Processing
Blank = -40C to + 85C (PLCC and QFP) 0C to 70C (DIP)
Speed Designator -14
-14 = 14MHz
____________________________________________________________________________________
To receive general sales or technical support on standard product or information about our module library licenses,
contact us at:
The Western Design Center, Inc.
2166 East Brown Road
Mesa, Arizona 85213 USA
Phone: 480-962-4545 Fax: 480-835-6442
information@westerndesigncenter.com
www.westerndesignc enter.com
_______________________________________________________________________________________
WARNING: MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE
Internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge
build-ups. Industry established recommendations for handling MOS circuits include:
1. Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in
non-conductive plastic containers or non-conductive plastic foam material.
2. Handle MOS parts only at conductive work stations.
3. Ground all assembly and repair tools.
The Western Design Center, Inc. W65C02S Datasheet 40
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