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TPS7A4001EVM-709

器件型号:TPS7A4001EVM-709
器件类别:嵌入式解决方案;工程工具
文件大小:1965.48KB,共10页
厂商名称:TI [Texas Instruments]
厂商官网:http://www.ti.com/
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器件描述

power management IC development tools tps7a4001 eval

参数

Manufacturer: Texas Instruments
Product Category: Power Management IC Development Tools
RoHS: No
Brand: Texas Instruments
Product: Evaluation Boards
Type: PMIC Solutions
Tool Is For Evaluation Of: TPS7A4001
Factory Pack Quantity: 1

TPS7A4001EVM-709相关参考设计

Reference Designs for: Part TPS7A4001EVM-709

TPS7A4001EVM-709器件文档内容

                                                                                                           User's Guide

                                                                                                                  SLVU448 March 2011

                                                                                        TPS7A4001EVM-709

This User's Guide describes operational use of the TPS7A4001EVM-709 Evaluation Module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7A4001, low dropout linear
regulator (LDO). Included in this user's guide are setup instructions, a schematic diagram, layout and
thermal guidelines, a bill of materials, and test results.

                                                                         Contents

1 Introduction .................................................................................................................. 1
2 Setup ......................................................................................................................... 2
3 Operation ..................................................................................................................... 2
4 Test Results ................................................................................................................. 3
5 Thermal Guidelines and Layout Recommendations ................................................................... 4
6 Board Layout ................................................................................................................ 5
7 Schematic and Bill of Materials ........................................................................................... 7

                                                List of Figures

1  Turnon Sequence: C1 EN - Turnon to 4.5V, C4 VOUT 5V Turnon Ramp Characteristic....................... 3

2  Step Load and Output Voltage Transient Response: C1 Full Load Current Step, C2 VOUT Output
   Voltage Transient Response .............................................................................................. 3

3 Assembly Layer ............................................................................................................. 5

4 Top Layer Routing .......................................................................................................... 5

5 Bottom Layer Routing ...................................................................................................... 6

6 Schematic .................................................................................................................... 7

                                                                     List of Tables

1 Thermal Resistance, JA , and Maximum Power Dissipation.......................................................... 4
2 TPS7A4100EVM-709 Bill of Materials ................................................................................... 8

1 Introduction

         The Texas Instruments TPS7A4001EVM-709 EVM helps design engineers to evaluate the operation and
         performance of the TPS7A4001 linear regulator for possible use in their own circuit application. This
         particular EVM configuration contains a single linear regulator with internal thermal and current limit
         shutdowns, and enable (disable) circuitry in a 3mm x 5mm, MSOP-8, thermally enhanced PowerPadTM
         package. The regulator, including external components, is capable of delivering up to 50mA to the load,
         depending on the input-output power dissapation, at an operating input voltage of up to 100V. The EVM
         output voltage is adjustable by an external resistor divider from 1.2V to 35V, but this is limited by the
         working voltage of the output capacitor. The LDO supports output voltages to 90V. The resistor divider is
         preset to provide VOUT equal to 5V.

PowerPad is a trademark of Texas Instruments.                                          TPS7A4001EVM-709            1

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Setup                                                                                                   www.ti.com

2 Setup

         This section describes the jumpers and connectors on the EVM as well as how to properly connect, setup
         and use the TPS7A4001EVM.

2.1 Input/Output Connector and Jumper Descriptions

          J1-EN: Output enable. To enable the output, connect a jumper to short ON (pin 1) to EN (center pin 2).
             To disable the output, connect a jumper to short EN (pin 2) to OFF (pin 3).

          J2 VIN: Input power supply voltage connector. The positive input lead and ground return lead from
             the input power supply should be twisted and kept as short as possible to minimize EMI transmission.
             Additional bulk capacitance should be added between J2 and J4 if the supply leads are greater than
             six inches. For example, an additional 47F electrolytic capacitor connected from J2 to ground can
             improve the transient response of the TPS7A4001 while eliminating unwanted ringing on the input due
             to long wire connections

          J4 GND: Ground-return connector for the input power supply

          J3 VOUT: Regulated output voltage connector.

          J5 GND: Output ground-return connector.

2.2 Soldering Guidelines

         Any solder re-work to modify the EVM for the purpose of repair or other application reasons must be
         performed using a hot-air system to avoid damaging the integrated circuit IC especially.

2.3 Equipment Interconnect

          Turn off the input power supply after verifying that its output voltage is set to the desired supply voltage
             (less than 100V) and the current limit is set to approximately 100mA. Connect the positive voltage lead
             from input power supply to VIN, at the J2 connector of the EVM. Connect the ground lead from the
             input power supply to GND at the J4 connector of the EVM.

          Connect a 0-50mA load (ILoad) between VOUT, at the J3 connector, and the GND, at the J4
             connector.

          Disable the output by connecting a jumper at J1 to short the EN (pin 2) to the OFF (pin 3).

3 Operation

       Turn on the input power supply. Verify that the output voltage is near 0.V.

       Enable the output by reconnecting the jumper on J1 to short the EN (pin 2) to the ON (pin 1).

       Vary the load current and VIN voltage as necessary for test purposes. Note that at room temperature

       (25C) the power dissipation (Pdisp) across the TPS7A4001.

       Pdisp = (VIN VOUT) x ILoad                                                                           (1)

2      TPS7A4001EVM-709                                                                            SLVU448 March 2011
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www.ti.com                                                             Test Results

4 Test Results

         This section provides typical performance waveforms for the TPS7A4001EVM-709 characteristic of this
         EVM design.

4.1 Turnon Characteristics

         Figure 1 shows the turn-on characteristic where VIN is pre-set to 9V, the output load is set to 50mA, and
         the regulator is enabled by a 4.5V step voltage (C1, gold) applied to EN (J1, pin 2). The VOUT softstart
         (C4, green) shows a rise time indicative of the R1 and C2 values selected.

                                                            EN

                                               VOUT

       Figure 1. Turnon Sequence: C1 EN - Turnon to 4.5V, C4 VOUT 5V Turnon Ramp Characteristic
4.2 Output Load Transition

         Figure 2 shows the VOUT transient response (C2, red) for a full load step transition from 0mA to 50mA
         (C1, gold).

                                      VOUT

                                       IOUT

Figure 2. Step Load and Output Voltage Transient Response: C1 Full Load Current Step, C2 VOUT
                                               Output Voltage Transient Response

SLVU448 March 2011                                                   TPS7A4001EVM-709                             3
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Thermal Guidelines and Layout Recommendations                                         www.ti.com

5 Thermal Guidelines and Layout Recommendations

   Thermal management is a key component of design of any power converter and is especially important
   when the power dissipation in the LDO is high. Use the following formula to approximate the maximum
   power dissipation for the particular ambient temperature:

   TJ = TA + Pd x JA                                                                                    (2)

   where:

       TJ is the junction temperature

       TA is the ambient temperature

       PD is the power dissipation in the device (Watts)

       JA is the thermal resistance from junction to ambient.
   All temperatures are in degrees Celcius. The maximum silicon junction temperature, TJ, must not be
   allowed to exceed 125C. The layout design must use copper trace and plane areas with care, as thermal
   sinks. Do not to allow TJ to exceed the absolute maximum rating under all temperature conditions and
   voltage conditions across the part.

   The layout should consider carefully the thermal design of the PCB for optimal performance over
   temperature. For this EVM, Figure 5 shows that the DQN package footprint employes a thermal pad for
   further cooling the part. The thermal pad contains a single 6.mil thermal via connection to the bottom side
   copper ground plane as well as a direct connection to the top side surface copper over the ground pad/pin
   for IC. The PCB is a two layer board with 2.oz. copper on top and bottom layers. The DQN package
   drawing can be found at the Texas Instruments web site in the product folder for the TPS707 LDO.

   Table 1 repeats information from the Dissipation Ratings Table of the TPS7A4001 data sheet for
   comparison with the thermal resistance, JA, calculated for this EVM layout to show the variation in thermal
   resistances for given copper areas. The High-K value is determined using a standard JEDEC high-k
   (2s2p) board having dimensions of 3-inch x 3-inch with 1-ounce internal power and ground planes and
   2-ounce copper traces on top and bottom of the board.

                     Table 1. Thermal Resistance, JA , and Maximum Power Dissipation

           Board      Package                      JA    Max Dissipation without  Max Dissipation without
           High-K       DGN                    55.1C/W             Derating                 Derating

                                                                  (TA = 25C)              (TA = 70C)

                                                                      1.83W                    1.08W

   TPS7A4001EVM-709   DGN                      49.0C/W            2.04W              1.12W

   The thermal resistance for the TPS7A4001EVM-709, JA, is the measured value for this particular layout
   scheme. The maximum power dissipation is proportional to the volume of copper volume connected to the

   package.

4  TPS7A4001EVM-709                                                                            SLVU448 March 2011
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www.ti.com                                                             Board Layout

6 Board Layout

                               Figure 3. Assembly Layer

                               Figure 4. Top Layer Routing

SLVU448 March 2011                                                   TPS7A4001EVM-709  5
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Board Layout                                                 www.ti.com

                     Figure 5. Bottom Layer Routing

6  TPS7A4001EVM-709                                                       SLVU448 March 2011
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www.ti.com                                                                 Schematic and Bill of Materials

7 Schematic and Bill of Materials
         Spacer
         Spacer

SLVU448 March 2011                   Figure 6. Schematic                 TPS7A4001EVM-709 7
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Schematic and Bill of Materials                                                                                                                                      www.ti.com

                                            Table 2. TPS7A4100EVM-709 Bill of Materials

COUNT   RefDes                   Value      Description                       Size               Part Number                                                MFR
1                                                                                                                                                           STD
1       C1                       2.2 uF     Capacitor, Ceramic, 100V, X7R, 10% 1210              STD                                                        STD

1       C2                       0.01uF     Capacitor, Ceramic, Low Inductance, 0603             STD                                                        STD
1                                                                                                                                                           Sullins
4                                           100V, X7R, 20%                                                                                                  Sullins
1                                                                                                                                                           STD
1       C3                       10.0 uF    Capacitor, Ceramic, 35V, X7R, 10% 1210               STD                                                        STD
1                                                                                                                                                           TI
1       J1                       PEC03SAAN  Header, Male 3-pin, 100mil spacing 0.100 inch x 3    PEC03SAAN                                                  Any
1                                                                                                                                                           3M
Notes:  J2, J3, J4, J5           PEC02SAAN  Header, Male 2-pin, 100mil spacing 0.100 inch x 2    PEC02SAAN

        R1                       107K       Resistor, Chip, 1/16W, 1%         0603               STD

        R2                       59K        Resistor, Chip, 1/16W, 1%         0603               STD

        U1                       TPS7A4001DGN IC, 120 V Input Voltage, 50 mA  DGN                TPS7A4001DGN

        --                       --         PCB, 1.260In x 2.370 In x 0.062 In --                HPA709

        --                       --         Shunt, 100-mil, Black             0.100 inch         929950-00

        1. These assemblies are ESD sensitive, ESD precautions shall be observed.
        2. These assemblies must be clean and free from flux and all contaminants.
        3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.
        4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components.

8 TPS7A4001EVM-709                                                                                                          SLVU448 March 2011
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                                                          2011, Texas Instruments Incorporated
                                           Evaluation Board/Kit Important Notice

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
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Should this evaluation board/kit not meet the specifications indicated in the User's Guide, the board/kit may be returned within 30
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                                                             FCC Warning

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
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                                               EVM Warnings and Restrictions

It is important to operate this EVM within the input voltage range of 7V to 100V and the output voltage range of not to exceed 90V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 160C. The EVM is designed to
operate properly with certain components above 160C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.

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