TPS7A4001
www.ti.com SBVS162A MARCH 2011 REVISED MARCH 2011
100V Input Voltage, 50mA, Very High Voltage
LINEAR REGULATOR
Check for Samples: TPS7A4001
FEATURES DESCRIPTION
1 The TPS7A4001 is a very high voltage-tolerant linear
regulator that offers the benefits of a
23 Very High Maximum Input Voltage: 100V thermally-enhanced package (MSOP-8), and is able
Wide Input Voltage Range: 7V to 100V to withstand continuous dc or transient input voltages
Accuracy: of up to 100V.
Nominal: 1% The TPS7A4001 is stable with any output
Over Line, Load, and Temperature: 2.5% capacitance greater than 4.7F and any input
Low Quiescent Current: 25A capacitance greater than 1F (over temperature and
Quiescent Current at Shutdown: 4.1A tolerance). Therefore, implementations of this device
Maximum Output Current: 50mA require minimal board space because of its
CMOS Logic-Level-Compatible Enable Pin miniaturized packaging (MSOP-8) and a potentially
Adjustable Output Voltage from ~1.175V to 90V small output capacitor. In addition, the TPS7A4001
Stable with Ceramic Capacitors: offers an enable pin (EN) compatible with standard
Input Capacitance: 1F CMOS logic to enable a low-current shutdown mode.
Output Capacitance: 4.7F
Dropout Voltage: 290mV The TPS7A4001 has an internal thermal shutdown
Built-In Current-Limit and Thermal Shutdown and current limiting to protect the system during fault
Protection conditions. The MSOP-8 packages has an operating
Package: High Thermal Performance MSOP-8 temperature range of TJ = 40C to +125C.
PowerPADTM
Operating Temperature Range: 40C to In addition, the TPS7A4001 is ideal for generating a
+125C low-voltage supply from intermediate voltage rails in
telecom and industrial applications; not only it can
APPLICATIONS supply a well-regulated voltage rail, but it can also
withstand and maintain regulation during very high
Microprocessors, Microcontrollers Powered by and fast voltage transients. These features translate
Industrial Busses with High Voltage Transients to simpler and more cost-effective electrical
surge-protection circuitry for a wide range of
Industrial Automation applications, including PoE, bias supply, and LED
Telecom Infrastrucure lighting.
Automotive
Power over Ethernet (PoE) Typical Application
LED Lighting
Bias Power Supplies 100V
VIN
VIN IN OUT VOUT
CIN CBYP R1
TPS7A4001
VEN EN GND FB COUT
R2
DGN PACKAGE
3mm 5mm MSOP-8 PowerPAD
(TOP VIEW)
OUT 1 8 IN Post DC/DC Converter Regulation for
High-Performace Analog Circuitry
FB 2 7 NC
NC 3 6 NC
GND 4 5 EN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date. Copyright 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS7A4001
SBVS162A MARCH 2011 REVISED MARCH 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
TPS7A4001 yyy z
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN MAX UNIT
V
IN pin to GND pin 0.3 +105 V
OUT pin to GND pin V
OUT pin to IN pin 0.3 +105 V
FB pin to GND pin V
FB pin to IN pin 105 +0.3
EN pin to IN pin V
Voltage EN pin to GND pin 0.3 +2
Peak output C
Current Operating virtual junction, TJ 105 +0.3 C
Temperature Storage, Tstg kV
Electrostatic discharge rating Human body model (HBM) 105 0.3 V
Charged device model (CDM)
0.3 +105
Internally limited
40 +125
65 +150
2.5
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC(1) TPS7A4001 UNITS
DGN
8 PINS
JA Junction-to-ambient thermal resistance 55.09 C/W
JC(top) Junction-to-case(top) thermal resistance 8.47
JB Junction-to-board thermal resistance --
JT Junction-to-top characterization parameter 0.36
JB Junction-to-board characterization parameter 14.6
JC(bottom) Junction-to-case(bottom) thermal resistance --
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS
BOARD PACKAGE RJA RJC DERATING FACTOR TA +25C POWER TA = +70C POWER TA = +85C POWER
High-K (1) DGN 55.9C/W 8.47C/W ABOVE TA = +25C RATING RATING RATING
16.6mW/C 1.83W 1.08W 0.833W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
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ELECTRICAL CHARACTERISTICS
At TJ = 40C to +125C, VIN = VOUT(NOM) + 2.0V or VIN = 7.0V (whichever is greater), VEN = VIN, IOUT = 100A, CIN = 1F, COUT = 4.7F,
and FB tied to OUT, unless otherwise noted.
TPS7A4001
VIN PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Input voltage range 7.0 1.173 100.0 V
Internal reference TJ = +25C, VFB = VREF, VIN = 9V, IOUT = 25mA 1.161 1.185 V
VOUT Output voltage range(1) VIN VOUT(NOM) + 2.0V VREF 0.03 V
Nominal accuracy TJ = +25C, VIN = 9V, IOUT = 25mA 1.0 90
VOUT(NOM) + 2.0V VIN 24V (2) +1.0 %VOUT
Overall accuracy 100A IOUT 50mA 2.5
+2.5 %VOUT
7V VIN 100V
D%VOUT Line regulation %VOUT
DVIN
D%VOUT 100A IOUT 50mA 0.31 %VOUT
DIOUT Load regulation
VDO Dropout voltage VIN = 17V, VOUT(NOM) = 18V, IOUT = 20mA 290 mV
VIN = 17V, VOUT(NOM) = 18V, IOUT = 50mA
ILIM Current limit VOUT = 90% VOUT(NOM), VIN = 7.0V, TJ +85C 0.78 1.3 V
VOUT = 90% VOUT(NOM), VIN = 9.0V
IGND Ground current 7V VIN 100V, IOUT = 0mA 51 117 200 mA
ISHDN Shutdown supply current IOUT = 50mA
I FB Feedback current(3) VEN = +0.4V 51 128 200 mA
IEN Enable current
VEN_HI Enable high-level voltage 7V VIN 100V, VIN = VEN 25 65 A
VEN_LO Enable low- level voltage
VIN = 12V, VOUT(NOM) = VREF, COUT = 10F, 25 A
VNOISE Output noise voltage BW = 10Hz to 100kHz
VIN = 12V, VOUT(NOM) = 5V, COUT = 10F, 4.1 20 A
PSRR Power-supply rejection ratio CBYP(4) = 10nF, BW = 10Hz to 100kHz
VIN = 12V, VOUT(NOM) = 5V, COUT = 10F, 0.1 0.01 0.1 A
TSD Thermal shutdown temperature CBYP(4) = 10nF, f = 100Hz
TJ Operating junction temperature Shutdown, temperature increasing 0.02 1.0 A
range Reset, temperature decreasing
1.5 VIN V
0 0.4 V
58 VRMS
73 VRMS
65 dB
+170 C
+150 C
40 +125 C
(1) To ensure stability at no-load conditions, a current from the feedback resistive network greater than or equal to 10A is required.
(2) Maximum input voltage is limited to 24V because of the package power dissipation limitations at full load (P (VIN VOUT) IOUT =
(24V VREF) 50mA 1.14W). The device is capable of sourcing a maximum current of 50mA at higher input voltages as long as the
power dissipated is within the thermal limits of the package plus any external heatsinking.
(3) IFB > 0 flows out of the device.
(4) CBYP refers to a bypass capacitor connected to the FB and OUT pins.
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FUNCTIONAL BLOCK DIAGRAM DEVICE INFORMATION
IN OUT
UVLO
Pass
Thermal Device
Shutdown
Error
Current Amp
Limit
Enable
EN FB
TYPICAL APPLICATION CIRCUIT
VIN IN OUT VOUT
CIN VOUT
R1 + R2
10mF TPS7A4001 CBYP R1 Where: 10mA, and
10nF
COUT
VEN EN FB 10mF R1 = R2 VOUT -1
VREF
GND
R2
Example Circuit to Maximize Transient Performance
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PIN CONFIGURATION
DGN PACKAGE
MSOP-8
(TOP VIEW)
OUT 1 8 IN
FB 2 7 NC
NC 3 6 NC
GND 4 5 EN
TPS7A40xx PIN DESCRIPTIONS
NAME NO. DESCRIPTION
Regulator output. A capacitor > 4.7F must be tied from this pin to ground to assure stability.
OUT 1 This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device.
Not internally connected. This pin must either be left open or tied to GND.
FB 2 Ground
This pin turns the regulator on or off.
NC 3, 6, 7 If VEN VEN_HI the regulator is enabled.
If VEN VEN_LO, the regulator is disabled.
GND 4 If not used, the EN pin can be connected to IN. Make sure that VEN VIN at all times.
Input supply
EN 5 Solder to printed circuit board (PCB) to enhance thermal performance.
NOTE: The PowerPAD is internally connected to GND.
IN 8 Although it can be left floating, it is highly recommended to connect the PowerPAD to the GND plane.
PowerPAD
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TYPICAL CHARACTERISTICS
At TJ = 40C to +125C, VIN = VOUT(NOM) + 2.0V or VIN = 9.0V (whichever is greater), VEN = VIN, IOUT = 100A, CIN = 1F, COUT
= 4.7F, and FB tied to OUT, unless otherwise noted.
LINE TRANSIENT RESPONSE vs CBYP LOAD TRANSIENT RESPONSE
VOUT = 5V, IOUT = 28mA, COUT = 10mF VIN = 12V, VOUT = 5V
DIOUT = 1mA29mA1mA
VIN Slew Rate = 220V/ms
COUT = 10mF, CBYP = 10nF
DVIN = 12V55V
VOUT
CBYP = 0nF VOUT
100mV/div 50mV/div
CBYP = 10nF VOUT
VIN
100mV/div IOUT
50V/div Time (1ms/div)
10mA/div
Figure 1. Time (100ms/div)
1.275
10 LINE REGULATION + 105C 1.225 Figure 2. + 105C
7.5 + 125C + 125C
- 40C FEEDBACK VOLTAGE
5 + 25C
2.5 + 85C - 40C
+ 25C
0 + 85C
-2.5
VOUT(NOM) (%) VFB (V) 1.175
-5
-7.5 1.125
-10
15 25 35 45 55 65 75 85 95 105 1.075 15 25 35 45 55 65 75 85 95 105
5 Input Voltage (V) 5 Input Voltage (V)
Figure 3. Figure 4.
QUIESCENT CURRENT vs INPUT VOLTAGE FEEDBACK CURRENT
100 100
- 40C 90
+ 25C
80 + 85C 80
+ 105C
+ 125C 70
IQ (A) 60 IFB (nA) 60
50
40 40
30
20 20
IOUT = 0mA 10
0
0 20 35 50 65 80 95 110 125
5 15 25 35 45 55 65 75 85 95 105 -40 -25 -10 5 Temperature (C)
Input Voltage (V)
Figure 6.
Figure 5.
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TPS7A4001
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TYPICAL CHARACTERISTICS (continued)
At TJ = 40C to +125C, VIN = VOUT(NOM) + 2.0V or VIN = 9.0V (whichever is greater), VEN = VIN, IOUT = 100A, CIN = 1F, COUT
= 4.7F, and FB tied to OUT, unless otherwise noted.
GROUND CURRENT DROPOUT VOLTAGE
100 2
90 - 40C - 40C + 105C
+ 25C 1.75 + 25C + 125C
80 + 85C + 85C
+ 105C 1.5
70 + 125C
IGND (A) 60 VDROP (V) 1.25
50 1
40 0.75
30
0.5
20
10 0.25
0 0 10 20 30 40 50 0 0 10 20 30 40 50
Output Current (mA) Output Current (mA)
Figure 7. Figure 8.
ENABLE THRESHOLD VOLTAGE OUTPUT SPECTRAL NOISE DENSITY
2.5 10
2
1
VEN (V) 1.5 Noise (V/ Hz) 0.1
OFF-TO-ON
1
0.5 0.01 VIN = 12V
ON-TO-OFF VOUT = VREF
COUT = 10F IOUT = 100A,VNOISE = 60VRMS
IOUT = 50mA,VNOISE = 100VRMS
CBYP = 10nF
0 20 35 50 65 80 95 110 125 0.001 10 100 1k 10k 100k 1M 10M
-40 -25 -10 5 Temperature (C)
Figure 9. Frequency (Hz)
Figure 10.
CURRENT LIMIT POWER-SUPPLY REJECTION RATIO
200 100
90
160 80
70
ICL (mA) 120 PSRR (dB) 60
50
80 40
- 40C 30
+ 25C VIN = 12V
40 + 85C 20 VOUT = 5V
0 + 105C
6 + 125C 10 COUT = 10F IOUT = 50mA
CBYP = 10nF IOUT = 100A
9 12 15 18 21 24 0 10 100 1k 10k 100k 1M 10M
Input Voltage (V) Frequency (Hz)
Figure 11. Figure 12.
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THEORY OF OPERATION
GENERAL DESCRIPTION ENABLE PIN OPERATION
The TPS7A4001 belongs to a new generation of The TPS7A4001 provides an enable pin (EN) feature
linear regulators that use an innovative BiCMOS that turns on the regulator when VEN > 1.5V.
process technology to achieve very high maximum
input and output voltages. CAPACITOR RECOMMENDATIONS
This process not only allows the TPS7A4001 to Low equivalent series resistance (ESR) capacitors
maintain regulation during very fast high-voltage should be used for the input, output, and bypass
transients up to 105V, but it also allows the capacitors. Ceramic capacitors with X7R and X5R
TPS7A4001 to regulate from a continuous dielectrics are preferred. These dielectrics offer more
high-voltage input rail. Unlike other regulators created stable characteristics. Ceramic X7R capacitors offer
using bipolar technology, the TPS7A4001 ground improved over-temperature performance, while
current is also constant over its output current range, ceramic X5R capacitors are the most cost-effective
resulting in increased efficiency and lower power and are available in higher values.
consumption.
Note that high ESR capacitors may degrade PSRR.
These features, combined with a high thermal
performance MSOP-8 PowerPAD package, make this INPUT AND OUTPUT CAPACITOR
device ideal for industrial and telecom applications. REQUIREMENTS
ADJUSTABLE OPERATION The TPS7A4001 high voltage linear regulator
achieves stability with a minimum output capacitance
The TPS7A4001 has an output voltage range of of 4.7F and input capacitance of 1F; however, it is
~1.175V to 90V. The nominal output voltage of the highly recommended to use 10F output and input
device is set by two external resistors, as shown in capacitors to maximize ac performance.
Figure 13.
BYPASS CAPACITOR REQUIREMENTS
VIN VOUT
Although a bypass capacitor (CBYP) is not needed to
IN OUT COUT achieve stability, it is highly recommended to use a
CIN 10mF 10nF bypass capacitor to maximize ac performance
(including line transient, noise and PSRR).
10mF TPS7A4001 CBYP R1
10nF MAXIMUM AC PERFORMANCE
EN GND FB
R2
Figure 13. Adjustable Operation for Maximum AC In order to maximize line transient, noise, and PSRR
Performance performance, it is recommended to include 10F (or
higher) input and output capacitors, and a 10nF
R1 and R2 can be calculated for any output voltage bypass capacitor, as shown in Figure 13. The
range using the formula shown in Equation 1. To solution shown delivers minimum noise levels of
ensure stability under no-load conditions, this 58VRMS and power-supply rejection levels above
resistive network must provide a current greater than 36dB from 10Hz to 10MHz.
or equal to 10A.
TRANSIENT RESPONSE
R1 = R2 VOUT -1 , where VOUT 10mA
VREF R1 + R2 (1) As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
If greater voltage accuracy is required, take into but increases duration of the transient response.
account the output voltage offset contributions
because of the feedback pin current and use 0.1% Note that the presence of the CBYP capacitor may
tolerance resistors. greatly improve the TPS7A4001 line transient
response, as noted in Figure 1.
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APPLICATION INFORMATION
TRANSIENT VOLTAGE PROTECTION not only for driving the intensity of an array of multiple
LEDs by using a PWM signal at its EN pin, but also
One of the primary applications of the TPS7A4001 is for controlling such an array. This PWM signal
to provide transient voltage protection to sensitive enables and disables the regulator, causing the LED
circuitry that may be damaged in the presence of light to vary its intensity.
high-voltage spikes.
Whenever the regulator is disabled, no current flows
This transient voltage protection can be more through the LED array. This condition means that the
cost-effective and compact compared to topologies regulator has the same high voltage applied to the
that use a transient voltage suppression (TVS) block. first LED in the array as is applied to the regulator
input. Figure 15 illustrates the solution to this problem
LED ARRAY DRIVER with the addition of the TPS7A4001 high-voltage
regulator.
The TPS7A4001 can be used to drive several LED
drivers connected in series, as shown in Figure 14. 100V
ILED ILED = VREF I = 0mA
100V RSET 100V
100V OUT
IN
IN OUT
TPS7A4001 COUT RSET
TPS7A4001 COUT RSET
Low EN FB
EN EN FB GND
GND
Figure 14. LED Array Driver Application Figure 15. LED Array Driver with Regulator
The TPS7A4001 high voltage rating makes it suitable Disabled
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LAYOUT
PACKAGE MOUNTING Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
Solder pad footprint recommendations for the inadequate heatsink. For reliable operation, junction
TPS7A4001 are available at the end of this product temperature should be limited to a maximum of
data sheet and at www.ti.com. +125C. To estimate the margin of safety in a
complete design (including heatsink), increase the
BOARD LAYOUT RECOMMENDATIONS TO ambient temperature until the thermal protection is
IMPROVE PSRR AND NOISE PERFORMANCE triggered; use worst-case loads and signal conditions.
For good reliability, thermal protection should trigger
To improve ac performance such as PSRR, output at least +35C above the maximum expected ambient
noise, and transient response, it is recommended that condition of the particular application. This
the board be designed with separate ground planes configuration produces a worst-case junction
for IN and OUT, with each ground plane connected temperature of +125C at the highest expected
only at the GND pin of the device. In addition, the ambient temperature and worst-case load.
ground connection for the output capacitor should
connect directly to the GND pin of the device. The internal protection circuitry of the TPS7A4001
has been designed to protect against overload
Equivalent series inductance (ESL) and ESR must be conditions. It was not intended to replace proper
minimized in order to maximize performance and heatsinking. Continuously running the TPS7A4001
ensure stability. Every capacitor (CIN, COUT, CBYP) into thermal shutdown degrades device reliability.
must be placed as close as possible to the device
and on the same side of the PCB as the regulator POWER DISSIPATION
itself.
The ability to remove heat from the die is different for
Do not place any of the capacitors on the opposite each package type, presenting different
side of the PCB from where the regulator is installed. considerations in the PCB layout. The PCB area
The use of vias and long traces is strongly around the device that is free of other components
discouraged because they may impact system moves the heat from the device to the ambient air.
performance negatively and even cause instability. Performance data for JEDEC low- and high-K boards
are given in the Dissipation Ratings Table. Using
If possible, and to ensure the maximum performance heavier copper increases the effectiveness in
denoted in this product data sheet, use the same removing heat from the device. The addition of plated
layout pattern used for TPS7A40 evaluation board, through-holes to heat dissipating layers also improves
available at www.ti.com. the heatsink effectiveness.
THERMAL PROTECTION
Thermal protection disables the output when the Power dissipation depends on input voltage and load
junction temperature rises to approximately +170C,
allowing the device to cool. When the junction conditions. Power dissipation (PD) is equal to the
temperature cools to approximately +150C, the product of the output current times the voltage drop
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient across the output pass element, as shown in
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the Equation 2:
regulator, protecting it from damage as a result of
overheating. PD = (VIN - VOUT) IOUT (2)
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PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2011
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package Pins Package Qty Eco Plan (2) Lead/ MSL Peak Temp (3) Samples
TPS7A4001DGNR Drawing 8 2500 Ball Finish (Requires Login)
TPS7A4001DGNT 8 250 Green (RoHS
ACTIVE MSOP- DGN & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ACTIVE PowerPAD DGN Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSOP-
PowerPAD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
www.ti.com PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION 18-Mar-2011
*All dimensions are nominal
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing 2500 Diameter Width (mm) (mm) (mm) (mm)
(mm) Quadrant
(mm) W1 (mm) 3.3 1.3 8.0
TPS7A4001DGNR MSOP- DGN 8 12.0 Q1
Power 330.0 12.4 5.3
PAD
TPS7A4001DGNT MSOP- DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
Power
PAD
Pack Materials-Page 1
www.ti.com PACKAGE MATERIALS INFORMATION
18-Mar-2011
*All dimensions are nominal Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
Device 2500 370.0 355.0 55.0
250 195.0 200.0 45.0
TPS7A4001DGNR MSOP-PowerPAD DGN 8
TPS7A4001DGNT MSOP-PowerPAD DGN 8
Pack Materials-Page 2
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