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TPS65987D

器件型号:TPS65987D
器件类别:半导体    模拟混合信号IC   
厂商名称:Texas Instruments
厂商官网:http://www.ti.com/
标准:
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器件描述

具有集成电源开关的 USB Type-C™ 和 USB PD 控制器

参数
产品属性属性值
Alternate modeYes
RatingCatalog
Device typePD controller
External power path controlGPIO,I2C
Package GroupVQFN|56
Policy managerIntegrated
Internal power path20V 5A Sink,20V 5A Source,5V 600mA VCONN
FunctionType-C
Data roleDFP,DRD,UFP
Power roleDRP,Sink,Source
Iq(Typ)(uA)45
Operating temperature range(C)-10 to 75
Dead battery supportYes
Realtime VBUS monitoringYes

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TPS65987D
SLVSES1B – MAY 2018 – REVISED JANUARY 2019
TPS65987D USB Type-C and USB PD Controller with Integrated Power Switches
1 Features
1
USB Power Delivery (PD) Controller
– USB PD 3.0 Compliant
– Fast Role Swap Support
– Physical Layer and Policy Engine
– Configurable at Boot and Host-Controlled
USB Type-C Specification Compliant
– Cable Attach and Orientation Detection
– Default, 1.5 A, or 3 A Power Advertisement
– Up to 600-mA VConn Current
Port Power Switch
– Two 5 V to 20 V, 5-A Bidirectional Switches to
or from VBUS
– Up to 10-A Adjustable Current Limiting
– Ideal Diode Reverse Current Protection
– Undervoltage, and Overvoltage Protection
– Slew Rate Control
– 5-V, 600-mA VConn Source
BC1.2 Support
– Advertisement as DCP and CDP
– Automatic DCP Modes Selection:
– Shorted Mode per BC1.2 and YD/T 1591-
2009
– 2.7-V Divider 3 Mode
– 1.2-V Mode
– Data Contact Detect
– Primary and Secondary Detection
I2C Master Write Control for Alt Mode Muxes and
Variable DCDCs
Alternate Mode Support
– DisplayPort
– Thunderbolt™
Power Management
– Power Supply from 3.3 V or VBUS Source
– 3.3-V LDO Output for Dead Battery Support
7-mm × 7-mm QFN Package
– 0.4-mm Pitch
– 56 Pin
2 Applications
Notebook Computers
Docking Systems
Tablets and Ultrabooks
DisplayPort, and Thunderbolt™ Systems
3 Description
The TPS65987D is a stand-alone USB Type-C and
Power Delivery (PD) controller providing cable plug
and orientation detection for a single USB Type-C
connector. Upon cable detection, the TPS65987D
communicates on the CC wire using the USB PD
protocol. When cable detection and USB PD
negotiation are complete, the TPS65987D enables
the appropriate power path and configures alternate
mode settings for external multiplexers.
Device Information
(1)
PART NUMBER
TPS65987D
PACKAGE
QFN (RSH56)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
5-20 V
5-20 V
5A
5A
V
BUS
3.3 V
Host
Host
Interface
Type-C Cable Detection
and
USB PD Controller
CC1/2
2
CC
V
CONN
TPS65987D
BC1.2
USB P/N
2
USB
Type-C
Connector
D+/-
GND
Alternate Mode Mux Ctrl
GPIO or I2C
SuperSpeed Mux/Retimer
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65987D
SLVSES1B – MAY 2018 – REVISED JANUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
1
1
1
2
3
6
8.2 Functional Block Diagram .......................................
19
8.3 Feature Description.................................................
19
8.4 Device Functional Modes........................................
41
9
Application and Implementation
........................
44
9.1 Application Information............................................
44
9.2 Typical Application .................................................
44
Absolute Maximum Ratings ......................................
6
ESD Ratings..............................................................
6
Recommended Operating Conditions.......................
6
Thermal Information ..................................................
7
Power Supply Requirements and Characteristics.....
7
Power Consumption Characteristics.........................
8
Power Switch Characteristics ...................................
8
Cable Detection Characteristics..............................
10
USB-PD Baseband Signal Requirements and
Characteristics .........................................................
11
6.10 BC1.2 Characteristics ...........................................
12
6.11 Thermal Shutdown Characteristics .......................
12
6.12 Oscillator Characteristics ......................................
13
6.13 I/O Characteristics.................................................
13
6.14 PWM Driver Characteristics..................................
13
6.15 I
2
C Requirements and Characteristics..................
14
6.16 SPI Master Timing Requirements .........................
15
6.17 HPD Timing Requirements ...................................
15
6.18 Typical Characteristics ..........................................
16
10 Power Supply Recommendations
.....................
54
10.1 3.3-V Power ..........................................................
54
10.2 1.8-V Power ..........................................................
54
10.3 Recommended Supply Load Capacitance............
54
11 Layout...................................................................
55
11.1
11.2
11.3
11.4
Layout Guidelines .................................................
55
Layout Example ....................................................
55
Component Placement..........................................
56
Routing PP_HV1/2, VBUS, PP_CABLE, VIN_3V3,
LDO_3V3, LDO_1V8 ...............................................
57
11.5 Routing CC and GPIO ..........................................
59
11.6 Thermal Dissipation for FET Drain Pads ..............
60
11.7 USB2 Recommended Routing For BC1.2
Detection/Advertisement ..........................................
62
12 Device and Documentation Support
.................
64
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
64
64
64
64
64
7
8
Parameter Measurement Information
................
16
Detailed Description
............................................
18
8.1 Overview .................................................................
18
13 Mechanical, Packaging, and Orderable
Information
...........................................................
65
4 Revision History
Changes from Revision A (August 2018) to Revision B
Page
Changed Pin Description to better clarify that VBUS1 and VBUS2 should be tied together ................................................
5
Changed
Figure 33
and
Figure 42
to use the Correct Pin Numbers ...................................................................................
44
Changes from Original (May 2018) to Revision A
Page
Changed status from Advance Information to Production Data .............................................................................................
1
2
Submit Documentation Feedback
Product Folder Links:
TPS65987D
Copyright © 2018–2019, Texas Instruments Incorporated
TPS65987D
www.ti.com
SLVSES1B – MAY 2018 – REVISED JANUARY 2019
5 Pin Configuration and Functions
RSH Package
56-Pin QFN
Top View
53
±
C_USB_N (GPIO19)
50
±
C_USB_P (GPIO18)
49
±
GPIO17 (PEXT2)
48
±
GPIO16 (PEXT1)
PP_HV2
±
1
PP_HV2
±
2
VBUS2
±
3
VBUS2
±
4
VIN_3V3
±
5
ADCIN1
±
6
DRAIN2
±
7
DRAIN1
±
8
LDO_3V3
±
9
ADCIN2
±
10
PP_HV1
±
11
PP_HV1
±
12
VBUS1
±
13
VBUS1
±
14
58
DRAIN1
59
GND
57
DRAIN2
43
±
GPIO15 (PWM)
44
±
HRESET
56
±
DRAIN2
52
±
DRAIN2
55
±
GPIO21
54
±
GPIO20
51
±
GND
47
±
GND
46
±
GND
45
±
GND
42
±
GPIO14 (PWM)
41
±
GPIO13
40
±
GPIO12
39
±
SPI_SS (GPIO11)
38
±
SPI_CLK (GPIO10)
37
±
SPI_MOSI (GPIO9)
36
±
SPI_MISO (GPIO8)
35
±
LDO_1V8
34
±
I2C2_IRQ
33
±
I2C2_SDA
32
±
I2C2_SCL
31
±
GPIO4
30
±
HPD (GPIO3)
29
±
I2C1_IRQ
15
±
DRAIN1
16
±
GPIO0
17
±
GPIO1
18
±
GPIO2
19
±
DRAIN1
20
±
GND
Pin Functions
PIN
NAME
ADCIN1
ADCIN2
C_CC1
NO.
6
10
24
TYPE
(1)
I
I
I/O
RESET STATE
(2)
Input
Input
High-Z
DESCRIPTION
Boot configuration Input. Connect to resistor
divider between LDO_3V3 and GND.
I2C address configuration Input. Connect to
resistor divider between LDO_3V3 and GND.
Output to Type-C CC or VCONN pin. Filter noise
with capacitor to GND
21
±
I2C3_SCL (GPIO5)
22
±
I2C3_SDA (GPIO6)
23
±
I2C3_IRQ (GPIO7)
24
±
C_CC1
25
±
PP_CABLE
26
±
C_CC2
27
±
I2C1_SCL
28
±
I2C1_SDA
(1)
(2)
I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect
Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware.
Submit Documentation Feedback
Product Folder Links:
TPS65987D
3
Copyright © 2018–2019, Texas Instruments Incorporated
TPS65987D
SLVSES1B – MAY 2018 – REVISED JANUARY 2019
www.ti.com
Pin Functions (continued)
PIN
NAME
C_CC2
C_USB_N (GPIO19)
C_USB_P (GPIO18)
DRAIN1
NO.
26
53
50
8, 15, 19, 58
TYPE
(1)
I/O
I/O
I/O
RESET STATE
(2)
High-Z
Input (High-Z)
Input (High-Z)
DESCRIPTION
Output to Type-C CC or VCONN pin. Filter noise
with capacitor to GND
USB D– connection for BC1.2 support
USB D+ connection for BC1.2 support
Drain of internal power path 1. Connect thermal
pad 58 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
Drain of internal power path 2. Connect thermal
pad 57 to as big of pad as possible on PCB for
best thermal performance. Short the other pins to
this thermal pad
Unused pin. Tie to GND.
General Purpose Digital I/O 0. Float pin when
unused. GPIO0 is asserted low during the
TPS65987D boot process. Once device
configuration and patches are loaded GPIO0 is
released
General Purpose Digital I/O 1. Ground pin with a
1-MΩ resistor when unused in the application
General Purpose Digital I/O 2. Float pin when
unused
General Purpose Digital I/O 3. Configured as Hot
Plug Detect (HPD) TX and RX when DisplayPort
alternate mode is enabled. Float pin when unused
General Purpose Digital I/O 4. Float pin when
unused
I2C port 3 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used. Float pin when unused
I2C port 3 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used.
Float pin when unused
I2C port 3 interrupt detection (port 3 operates as
an I2C Master Only). Active low detection. Connect
to the I2C slave's interrupt line to detect when the
slave issues an interrupt. Float pin when unused
General Purpose Digital I/O 12. Float pin when
unused
General Purpose Digital I/O 13. Float pin when
unused
General Purpose Digital I/O 14. May also function
as a PWM output. Float pin when unused
General Purpose Digital I/O 15. May also function
as a PWM output. Float pin when unused
General Purpose Digital I/O 16. May also function
as single wire enable signal for external power
path 1. Pull-down with external resistor when used
for external path control. Float pin when unused
General Purpose Digital I/O 17. May also function
as single wire enable signal for external power
path 2. Pull-down with external resistor when used
for external path control. Float pin when unused
General Purpose Digital I/O 20. Float pin when
unused
General Purpose Digital I/O 21. Float pin when
unused
DRAIN2
GND
7, 52, 56, 57
20, 45 , 46, 47, 51
GPIO0
16
I/O
Input (High-Z)
GPIO1
GPIO2
GPIO3 (HPD)
GPIO4
I2C3_SCL (GPIO5)
17
18
30
31
21
I/O
I/O
I/O
I/O
I/O
Input (High-Z)
Input (High-Z)
Input (High-Z)
Input (High-Z)
Input (High-Z)
I2C3_SDA (GPIO6)
22
I/O
Input (High-Z)
I2C3_IRQ (GPIO7)
23
I/O
Input (High-Z)
GPIO12
GPIO13
GPIO14 (PWM)
GPIO15 (PWM)
40
41
42
43
I/O
I/O
I/O
I/O
Input (High-Z)
Input (High-Z)
Input (High-Z)
Input (High-Z)
GPIO16 (PP_EXT1)
48
I/O
Input (High-Z)
GPIO17 (PP_EXT2)
49
I/O
Input (High-Z)
GPIO20
GPIO21
54
55
I/O
I/O
Input (High-Z)
Input (High-Z)
4
Submit Documentation Feedback
Product Folder Links:
TPS65987D
Copyright © 2018–2019, Texas Instruments Incorporated
TPS65987D
www.ti.com
SLVSES1B – MAY 2018 – REVISED JANUARY 2019
Pin Functions (continued)
PIN
NAME
HRESET
NO.
44
TYPE
(1)
RESET STATE
(2)
DESCRIPTION
Active high hardware reset input. Will reinitialize all
device settings. Ground pin when HRESET
functionality will not be used
I2C port 1 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C port 1 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C port 1 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
I2C port 2 interrupt. Active low. Implement
externally as an open drain with a pull-up
resistance. Float pin when unused
I2C port 2 serial clock. Open-drain output. Tie pin
to I/O voltage through a 10-kΩ resistance when
used or unused
I2C port 2 serial data. Open-drain output. Tie pin to
I/O voltage through a 10-kΩ resistance when used
or unused
Output of the 1.8-V LDO for internal circuitry.
Bypass with capacitor to GND
Output of the VBUS to 3.3-V LDO or connected to
VIN_3V3 by a switch. Main internal supply rail.
Used to power external flash memory. Bypass with
capacitor to GND
5-V supply input for port 1 C_CC pins. Bypass with
capacitor to GND
System side of first VBUS power switch. Bypass
with capacitor to ground. Tie to ground when
unused
System side of second VBUS power switch.
Bypass with capacitor to ground. Tie to ground
when unused
SPI serial clock. Ground pin when unused
SPI serial master input from slave. Ground pin
when unused
SPI serial master output to slave. Ground pin when
unused
SPI slave select. Ground pin when unused
Port side of first VBUS power switch. Bypass with
capacitor to ground. Tie to VBUS2
Port side of second VBUS power switch. Bypass
with capacitor to ground. Tie to VBUS1
Supply for core circuitry and I/O. Bypass with
capacitor to GND
Ground reference for the device as well as thermal
pad used to conduct heat from the device. This
connection serves two purposes. The first purpose
is to provide an electrical ground connection for
the device. The second purpose is to provide a low
thermal-impedance path from the device die to the
PCB. This pad must be connected to a ground
plane
I/O
Input
I2C1_IRQ
29
O
High-Z
I2C1_SCL
27
I/O
High-Z
I2C1_SDA
28
I/O
High-Z
I2C2_IRQ
34
O
High-Z
I2C2_SCL
32
I/O
High-Z
I2C2_SDA
LDO_1V8
33
35
I/O
PWR
High-Z
LDO_3V3
9
PWR
PP_CABLE
PP_HV1
25
11, 12
PWR
PWR
PP_HV2
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_SS
VBUS1
VBUS2
VIN_3V3
1, 2
38
36
37
39
13, 14
3, 4
5
PWR
I/O
I/O
I/O
I/O
PWR
PWR
PWR
Input
Input
Input
Input
Thermal Pad (PPAD)
59
GND
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
TPS65987D
5
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