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TPA3110D2

器件型号:TPA3110D2
器件类别:半导体    模拟混合信号IC   
厂商名称:Texas Instruments
厂商官网:http://www.ti.com/
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器件描述

TPA3110D2 15W Filter-Free Class D Stereo Amplifier with SpeakerGuard™ (TPA3110)

参数
产品属性属性值
Iq(Typ)(mA)10
Audio input typeAnalog Input
Analog supply(Max)(V)26
SNR(dB)102
THD + N @ 1 kHz(%)0.1
PSRR(dB)70
ArchitectureClass-D
RatingCatalog
Approx. price(US$)0.80 | 1ku
Power stage supply(Max)(V)26
Power to parallel bridge tied load(Max)(W)30
Analog supply(Min)(V)8
Control interfaceHardware
Output power(W)10
Operating temperature range(C)-40 to 85
Closed/open loopClosed
Power stage supply(Min)(V)8
Load(Min)(ohms)4
Speaker channels(Max)Stereo

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TPA3110D2
SLOS528F – JULY 2009 – REVISED APRIL 2017
TPA3110D2 15-W Fil ter-Free Stereo Class-D Audio Power Amplifier With Speakerguard™
1 Features
1
3 Description
The TPA3110D2 is a 15-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. Advanced EMI Suppression
Technology enables the use of inexpensive ferrite
bead filters at the outputs while meeting EMC
requirements. SpeakerGuard™ speaker protection
circuitry includes an adjustable power limiter and a
DC detection circuit. The adjustable power limiter
allows the user to set a "virtual" voltage rail lower
than the chip supply to limit the amount of current
through the speaker. The DC detect circuit measures
the frequency and amplitude of the PWM signal and
shuts off the output stage if the input capacitors are
damaged or shorts exist on the inputs.
The TPA3110D2 can drive stereo speakers as low as
4
Ω.
The high efficiency of the TPA3110D2, 90%,
eliminates the need for an external heat sink when
playing music.
The outputs are also fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an auto-
recovery feature.
Device Information
(1)
PART NUMBER
TPA3110D2
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm × 4.40 mm
15-W/ch into an 8-Ω Loads at 10% THD+N From
a 16-V Supply
10-W/ch into 8-Ω Loads at 10% THD+N From a
13-V Supply
30-W into a 4-Ω Mono Load at 10% THD+N From
a 16-V Supply
90% Efficient Class-D Operation Eliminates Need
for Heat Sinks
Wide Supply Voltage Range Allows Operation
From 8 V to 26 V
Filter-Free Operation
SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter Plus DC Protection
Flow Through Pin Out Facilitates Easy Board
Layout
Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection With Auto Recovery Option
Excellent THD+N / Pop-Free Performance
Four Selectable, Fixed Gain Settings
Differential Inputs
2 Applications
Televisions
Consumer Audio Equipment
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPA3110D2 Simplified Application Schematic
1
m
F
OUTL+
Audio
Source
OUTL-
OUTR+
OUTR-
LINP
LINN
RINP
RINN
GAIN0
GAIN1
TPA3110D2
OUTPL
OUTNL
FERRITE
BEAD
FILTER
15W
8W
OUTPR
OUTNR
PLIMIT
PBTL
Fault
SD
PVCC
FERRITE
BEAD
FILTER
15W
8W
8 to 26V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3110D2
SLOS528F – JULY 2009 – REVISED APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and F unctions
........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions......................
Thermal Information ..................................................
DC Characteristics: 24 V..........................................
DC Characteristics: 12 V..........................................
AC Characteristics: 24 V..........................................
AC Characteristics: 12 V..........................................
Typical Characteristics .............................................
1
1
1
2
4
4
5
5
6
6
6
6
7
7
7
8
9.2 Functional Block Diagram .......................................
14
9.3 Feature Description.................................................
15
9.4 Device Functional Modes........................................
20
10 Application and Implementation........................
21
10.1 Application Information..........................................
21
10.2 Typical Applications .............................................
21
11 Power Supply Recommendations
.....................
25
11.1 Power Supply Decoupling, C
S
.............................
25
12 Layout...................................................................
25
12.1 Layout Guidelines .................................................
25
12.2 Layout Example ....................................................
26
13 Device and Documentation Support
.................
27
13.1
13.2
13.3
13.4
13.5
13.6
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
8
9
Parameter Measurement Information
................
14
Detailed Description
............................................
14
9.1 Overview .................................................................
14
14 Mechanical, Packaging, and Orderable
Information
...........................................................
27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2015) to Revision F
Page
Added Measurement note added to characterization graphs...............................................................................................
10
Added New Output Power vs Supply Voltage Characterization graph ................................................................................
10
Added footnote for heatsink and EVM .................................................................................................................................
14
Changes from Revision D (July 2012) to Revision E
Page
Added
Pin Configuration and Functions
section,
ESD Ratings
table,
Feature Description
section,
Device Functional
Modes, Application and Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device
and Documentation Support
section, and
Mechanical, Packaging, and Orderable Information
section ..............................
1
Changes from Revision C (August 2010) to Revision D
Page
Added < 10 V/ms to V
I
in the Absolute Maximum Ratings table, added Note 2 ....................................................................
5
Changed the PBTL Select section. Added text - "The voltage slew.......series with the terminals." ....................................
19
Added a 100kΩ resistor to AVCC Pin 14 and Note 1 to
Figure 46
......................................................................................
24
Changes from Revision B (July 2010) to Revision C
Page
Replaced the Dissipations Ratings table with the Thermal Information table ........................................................................
6
Changes from Revision A (July 2009) to Revision B
Page
Added slew rate adjustment information ..............................................................................................................................
17
Added AVCC to Pin 7 of
Figure 46
......................................................................................................................................
24
2
Submit Documentation Feedback
Product Folder Links:
TPA3110D2
Copyright © 2009–2017, Texas Instruments Incorporated
TPA3110D2
www.ti.com
SLOS528F – JULY 2009 – REVISED APRIL 2017
Changes from Original (July 2009) to Revision A
Page
Changed Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration
Figure 42
-
Corrected the pin names. .....................................................................................................................................................
21
Changed Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input illustration
Figure 46
-
Corrected the pin names. .....................................................................................................................................................
24
Copyright © 2009–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
TPA3110D2
3
TPA3110D2
SLOS528F – JULY 2009 – REVISED APRIL 2017
www.ti.com
5 Device Comparison Table
DEVICE
NUMBER
TPA3110D2
TPA3130D1
TPA3118D2
TPA3116D1
SPEAKER CHANNELS
Stereo
Stereo
Stereo
Stereo
SPEAKER AMP
TYPE
Class D
Class D
Class D
Class D
OUTPUT POWER (W)
15
15
30
50
Power limiter
Power limiter
ADDITIONAL FEATURES
Power limiter
6 Pin Configuration and F unctions
PWP Package
28-Pin HTSSOP With PowerPAD™
Top View
SD
FAULT
LINP
LINN
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
RINN
RINP
NC
PBTL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PVCCL
PVCCL
BSPL
OUTPL
PGND
OUTNL
BSNL
BSNR
OUTNR
PGND
OUTPR
BSPR
PVCCR
PVCCR
Table 1. Pin Functions
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME
SD
FAULT
LINP
LINN
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
RINN
RINP
NC
PBTL
TYPE
I
O
I
I
I
I
P
O
I
I
I
I
DESCRIPTION
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC.
Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both
short circuit faults and dc detect faults must be reset by cycling PVCC.
Positive audio input for left channel. Biased at 3 V.
Negative audio input for left channel. Biased at 3 V.
Gain select least significant bit. TTL logic levels with compliance to AVCC.
Gain select most significant bit. TTL logic levels with compliance to AVCC.
Analog supply
Analog signal ground. Connect to the thermal pad.
High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for PLIMIT
function.
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect
directly to GVDD for no power limit.
Negative audio input for right channel. Biased at 3 V.
Positive audio input for right channel. Biased at 3 V.
Not connected
Parallel BTL mode switch
4
Submit Documentation Feedback
Product Folder Links:
TPA3110D2
Copyright © 2009–2017, Texas Instruments Incorporated
TPA3110D2
www.ti.com
SLOS528F – JULY 2009 – REVISED APRIL 2017
Table 1. Pin Functions (continued)
PIN
NO.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
PVCCR
PVCCR
BSPR
OUTPR
PGND
OUTNR
BSNR
BSNL
OUTNL
PGND
OUTPL
BSPL
PVCCL
PVCCL
TYPE
P
P
I
O
O
I
I
O
O
I
P
P
DESCRIPTION
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connect internally.
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connect internally.
Bootstrap I/O for right channel, positive high-side FET.
Class-D H-bridge positive output for right channel.
Power ground for the H-bridges.
Class-D H-bridge negative output for right channel.
Bootstrap I/O for right channel, negative high-side FET.
Bootstrap I/O for left channel, negative high-side FET.
Class-D H-bridge negative output for left channel.
Power ground for the H-bridges.
Class-D H-bridge positive output for left channel.
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connect internally.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connect internally.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
V
CC
Supply voltage
AVCC, PVCC
(2)
MAX
30 V
V
CC
+
0.3 V
< 10
V/ms
UNIT
V
V
–0.3 V
–0.3 V
SD, GAIN0, GAIN1, PBTL, FAULT
V
I
Interface pin voltage
PLIMIT
RINN, RINP, LINN, LINP
Continuous total power dissipation
BTL: PVCC > 15 V
R
L
T
A
T
J
T
stg
(1)
(2)
(3)
Minimum Load Resistance
BTL: PVCC
15 V
PBTL
Operating free-air temperature
Operating junction temperature range
(3)
Storage temperature
–0.3
–0.3
GVDD +
0.3
6.3
V
V
See
Thermal
Information
4.8
3.2
3.2
–40
–40
–65
85
150
150
°C
°C
°C
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resister in series
with the pins.
The TPA3110D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs
SLMA002
for more information about using the TSSOP thermal pad.
Copyright © 2009–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
TPA3110D2
5
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