TNY274-280
TinySwitch-III Family
Energy Efficient, Off-Line Switcher with
Enhanced Flexibility and Extended Power Range
Product Highlights + +
Lowest System Cost with Enhanced Flexibility Wide-Range D DC
Simple ON/OFF control, no loop compensation needed Output
Selectable current limit through BP/M capacitor value HV DC Input EN/UV
BP/M -
- Higher current limit extends peak power or, in open TinySwitch-III
frame applications, maximum continuous power S PI-4095-082205
- Lower current limit improves efficiency in enclosed -
adapters/chargers
Figure 1. Typical Standby Application.
- Allows optimum TinySwitch-III choice by swapping
devices with no other circuit redesign OUTPUT POWER TABLE
Tight I2f parameter tolerance reduces system cost 230 VAC 15% 85-265 VAC
- Maximizes MOSFET and magnetics power delivery
- Minimizes max overload power, reducing cost of PRODUCT3 Peak or Peak or
transformer, primary clamp & secondary components Adapter1 Open Adapter1 Open
Frame2 Frame2
ON-time extension extends low line regulation range/
hold-up time to reduce input bulk capacitance TNY274 P or G 6 W 11 W 5 W 8.5 W
Self-biased: no bias winding or bias components TNY275 P or G 8.5 W 15 W 6 W 11.5 W
Frequency jittering reduces EMI filter costs
Pin-out simplifies heatsinking to the PCB TNY276 P or G 10 W 19 W 7 W 15 W
SOURCE pins are electrically quiet for low EMI
TNY277 P or G 13 W 23.5 W 8 W 18 W
Enhanced Safety and Reliability Features
Accurate hysteretic thermal shutdown protection with TNY278 P or G 16 W 28 W 10 W 21.5 W
automatic recovery eliminates need for manual reset TNY279 P or G 18 W 32 W 12 W 25 W
Improved auto-restart delivers <3% of maximum power
TNY280 P or G 20 W 36.5 W 14 W 28.5 W
in short circuit and open loop fault conditions
Output overvoltage shutdown with optional Zener Table 1. Notes: 1. Minimum continuous power in a typical non-
Line under-voltage detect threshold set using a single ventilated enclosed adapter measured at 50 C ambient. Use of an
external heatsink will increase power capability 2. Minimum peak
optional resistor power capability in any design or minimum continuous power in an
Very low component count enhances reliability and open frame design (see Key Application Considerations). 3. Packages:
P: DIP-8C, G: SMD-8C. See Part Ordering Information.
enables single-sided printed circuit board layout
High bandwidth provides fast turn on with no overshoot PC Standby and other auxiliary supplies
DVD/PVR and other low power set top decoders
and excellent transient load response Supplies for appliances, industrial systems, metering, etc.
Extended creepage between DRAIN and all other pins
Description
improves field reliability
TinySwitch-III incorporates a 700 V power MOSFET, oscillator,
EcoSmart Extremely Energy Efficient high voltage switched current source, current limit (user
Easily meets all global energy efficiency regulations selectable) and thermal shutdown circuitry. The IC family uses
No-load <150 mW at 265 VAC without bias winding, an ON/OFF control scheme and offers a design flexible solution
with a low system cost and extended power capability.
<50 mW with bias winding
ON/OFF control provides constant efficiency down to February 2006
very light loads ideal for mandatory CEC regulations
and 1 W PC standby requirements
Applications
Chargers/adapters for cell/cordless phones, PDAs, digital
cameras, MP3/portable audio, shavers, etc.
TNY274-280
BYPASS/ REGULATOR DRAIN
MULTI-FUNCTION 5.85 V (D)
(BP/M)
LINE UNDER-VOLTAGE
115 A 25 A FAULT BYPASS PIN
PRESENT UNDER-VOLTAGE
+
AUTO- VILIMIT
RESTART -
COUNTER CURRENT LIMIT
CURRENT 5.85 V COMPARATOR
LIMIT STATE 4.9 V
6.4 V RESET MACHINE
ENABLE +
-
1.0 V + VT JITTER THERMAL
CLOCK SHUTDOWN
DCMAX
OSCILLATOR
ENABLE/ 1.0 V
UNDER-
VOLTAGE S Q
(EN/UV)
R Q
LEADING
EDGE
BLANKING
SOURCE
(S)
PI-4077-013106
Figure 2. Functional Block Diagram.
Pin Functional Description P Package (DIP-8C)
G Package (SMD-8C)
DRAIN (D) Pin:
This pin is the power MOSFET drain connection. It provides EN/UV 1 8S
internal operating current for both start-up and steady-state BP/M 2 7S
operation. 6S
D4 5S
BYPASS/MULTI-FUNCTION (BP/M) Pin:
This pin has multiple functions:
1. It is the connection point for an external bypass capacitor PI-4078-080905
for the internally generated 5.85 V supply.
Figure 3. Pin Configuration.
2. It is a mode selector for the current limit value, depending
on the value of the capacitance added. Use of a 0.1 F with a Zener connected from the BP/M pin to a bias winding
capacitor results in the standard current limit value. Use of supply.
a 1 F capacitor results in the current limit being reduced to
that of the next smaller device size. Use of a 10 F capacitor ENABLE/UNDER-VOLTAGE (EN/UV) Pin:
results in the current limit being increased to that of the next This pin has dual functions: enable input and line under-voltage
larger device size for TNY275-280. sense. During normal operation, switching of the power
3. It provides a shutdown function. When the current into the
bypass pin exceeds 5.5 mA, the device latches off until the
BP/M voltage drops below 4.9 V, during a power down.
This can be used to provide an output overvoltage function
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2/06
MOSFET is controlled by this pin. MOSFET switching is PI-2741-041901 TNY274-280
terminated when a current greater than a threshold current is
drawn from this pin. Switching resumes when the current being maximum duty cycle signal (DCMAX) and the clock signal that
pulled from the pin drops to less than a threshold current. A indicates the beginning of each cycle.
modulation of the threshold current reduces group pulsing. The
threshold current is between 60 A and 115 A. The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 8 kHz peak-to-peak, to
The EN/UV pin also senses line under-voltage conditions through minimize EMI emission. The modulation rate of the frequency
an external resistor connected to the DC line voltage. If there is jitter is set to 1 kHz to optimize EMI reduction for both average
no external resistor connected to this pin, TinySwitch-III detects and quasi-peak emissions. The frequency jitter should be
its absence and disables the line under-voltage function. measured with the oscilloscope triggered at the falling edge of
the DRAIN waveform. The waveform in Figure 4 illustrates
SOURCE (S) Pin: the frequency jitter.
This pin is internally connected to the output MOSFET source
for high voltage power return and control circuit common. Enable Input and Current Limit State Machine
The enable input circuit at the EN/UV pin consists of a low
TinySwitch-III Functional impedance source follower output set at 1.2 V. The current
Description through the source follower is limited to 115 A. When the
current out of this pin exceeds the threshold current, a low
TinySwitch-III combines a high voltage power MOSFET switch logic level (disable) is generated at the output of the enable
with a power supply controller in one device. Unlike conventional circuit, until the current out of this pin is reduced to less than
PWM (pulse width modulator) controllers, it uses a simple the threshold current. This enable circuit output is sampled
ON/OFF control to regulate the output voltage. at the beginning of each cycle on the rising edge of the clock
signal. If high, the power MOSFET is turned on for that cycle
The controller consists of an oscillator, enable circuit (sense and (enabled). If low, the power MOSFET remains off (disabled).
logic), current limit state machine, 5.85 V regulator, BYPASS/ Since the sampling is done only at the beginning of each cycle,
MULTI-FUNCTION pin under-voltage, overvoltage circuit, and subsequent changes in the EN/UV pin voltage or current during
current limit selection circuitry, over- temperature protection, the remainder of the cycle are ignored.
current limit circuit, leading edge blanking, and a 700 V power
MOSFET. TinySwitch-III incorporates additional circuitry for The current limit state machine reduces the current limit by
line under-voltage sense, auto-restart, adaptive switching cycle discrete amounts at light loads when TinySwitch-III is likely to
on-time extension, and frequency jitter. Figure 2 shows the switch in the audible frequency range. The lower current limit
functional block diagram with the most important features. raises the effective switching frequency above the audio range
and reduces the transformer flux density, including the associated
Oscillator audible noise. The state machine monitors the sequence of
The typical oscillator frequency is internally set to an average enable events to determine the load condition and adjusts the
of 132 kHz. Two signals are generated from the oscillator: the current limit level accordingly in discrete amounts.
600 Under most operating conditions (except when close to no-load),
the low impedance of the source follower keeps the voltage on
500 the EN/UV pin from going much below 1.2 V in the disabled
VDRAIN state. This improves the response time of the optocoupler that
is usually connected to this pin.
400
5.85 V Regulator and 6.4 V Shunt Voltage Clamp
300 The 5.85 V regulator charges the bypass capacitor connected
to the BYPASS pin to 5.85 V by drawing a current from the
200 voltage on the DRAIN pin whenever the MOSFET is off. The
BYPASS/MULTI-FUNCTION pin is the internal supply voltage
100 node. When the MOSFET is on, the device operates from the
energy stored in the bypass capacitor. Extremely low power
0 consumption of the internal circuitry allows TinySwitch-III to
136 kHz operate continuously from current it takes from the DRAIN
128 kHz pin. A bypass capacitor value of 0.1 F is sufficient for both
high frequency decoupling and energy storage.
0 5 10
Time (s)
Figure 4. Frequency Jitter.
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TNY274-280 Auto-Restart
In the event of a fault condition such as output overload, output
In addition, there is a 6.4 V shunt regulator clamping the short circuit, or an open loop condition, TinySwitch-III enters
BYPASS/MULTI-FUNCTION pin at 6.4 V when current into auto-restart operation. An internal counter clocked by the
is provided to the BYPASS/MULTI-FUNCTION pin oscillator is reset every time the EN/UV pin is pulled low. If the
through an external resistor. This facilitates powering of EN/UV pin is not pulled low for 64 ms, the power MOSFET
TinySwitch-III externally through a bias winding to decrease switching is normally disabled for 2.5 seconds (except in the
the no-load consumption to well below 50 mW. case of line under-voltage condition, in which case it is disabled
until the condition is removed). The auto-restart alternately
BYPASS/MULTI-FUNCTION Pin Under-Voltage enables and disables the switching of the power MOSFET until
The BYPASS/MULTI-FUNCTION pin under-voltage circuitry the fault condition is removed. Figure 5 illustrates auto-restart
disables the power MOSFET when the BYPASS/MULTI- circuit operation in the presence of an output short circuit.
FUNCTION pin voltage drops below 4.9 V in steady state
operation. Once the BYPASS/MULTI-FUNCTION pin voltage In the event of a line under-voltage condition, the switching of
drops below 4.9 V in steady state operation, it must rise back the power MOSFET is disabled beyond its normal 2.5 seconds
to 5.85 V to enable (turn-on) the power MOSFET. until the line under-voltage condition ends.
Over Temperature Protection Adaptive Switching Cycle On-Time Extension
The thermal shutdown circuitry senses the die temperature. The Adaptive switching cycle on-time extension keeps the cycle
threshold is typically set at 142 C with 75 C hysteresis. When on until current limit is reached, instead of prematurely
the die temperature rises above this threshold the power MOSFET terminating after the DCMAX signal goes low. This feature
is disabled and remains disabled until the die temperature falls reduces the minimum input voltage required to maintain
by 75 C, at which point it is re-enabled. A large hysteresis of regulation, extending hold-up time and minimizing the size
75 C (typical) is provided to prevent overheating of the PC of bulk capacitor required. The on-time extension is disabled
board due to a continuous fault condition. during the startup of the power supply, until the power supply
output reaches regulation.
Current Limit
The current limit circuit senses the current in the power MOSFET. Line Under-Voltage Sense Circuit
When this current exceeds the internal threshold (ILIMIT), the The DC line voltage can be monitored by connecting an external
power MOSFET is turned off for the remainder of that cycle. The resistor from the DC line to the EN/UV pin. During power-up or
current limit state machine reduces the current limit threshold when the switching of the power MOSFET is disabled in auto-
by discrete amounts under medium and light loads. restart, the current into the EN/UV pin must exceed 25 A to
initiate switching of the power MOSFET. During power-up, this
The leading edge blanking circuit inhibits the current limit is accomplished by holding the BYPASS/MULTI-FUNCTION
comparator for a short time (tLEB) after the power MOSFET is pin to 4.9 V while the line under-voltage condition exists. The
turned on. This leading edge blanking time has been set so that BYPASS/MULTI-FUNCTION pin then rises from 4.9 V to
current spikes caused by capacitance and secondary-side rectifier 5.85 V when the line under-voltage condition goes away. When the
reverse recovery time will not cause premature termination of switching of the power MOSFET is disabled in auto-restart mode
the switching pulse. and a line under-voltage condition exists, the auto-restart counter
is stopped. This stretches the disable time beyond its normal
300 V PI-4098-082305 2.5 seconds until the line under-voltage condition ends.
DRAIN
The line under-voltage circuit also detects when there is
200 no external resistor connected to the EN/UV pin (less than
~1 A into the pin). In this case the line under-voltage function
100 is disabled.
0 TinySwitch-III Operation
10 TinySwitch-III devices operate in the current limit mode. When
enabled, the oscillator turns the power MOSFET on at the
VDC-OUTPUT beginning of each cycle. The MOSFET is turned off when the
current ramps up to the current limit or when the DCMAX limit is
5 reached. Since the highest current limit level and frequency of
a TinySwitch-III design are constant, the power delivered to the
0
0 2500 5000
Time (ms)
Figure 5. Auto-Restart Operation.
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2/06
load is proportional to the primary inductance of the transformer TNY274-280
and peak primary current squared. Hence, designing the supply
involves calculating the primary inductance of the transformer not to proceed with the next switching cycle. The sequence of
for the maximum output power required. If the TinySwitch-III cycles is used to determine the current limit. Once a cycle is
is appropriately chosen for the power level, the current in the started, it always completes the cycle (even when the EN/UV
calculated inductance will ramp up to current limit before the pin changes state half way through the cycle). This operation
DCMAX limit is reached. results in a power supply in which the output voltage ripple
Enable Function is determined by the output capacitor, amount of energy per
TinySwitch-III senses the EN/UV pin to determine whether or switch cycle and the delay of the feedback.
VEN The EN/UV pin signal is generated on the secondary by
comparing the power supply output voltage with a reference
CLOCK voltage. The EN/UV pin signal is high when the power supply
output voltage is less than the reference voltage.
DCMAX
In a typical implementation, the EN/UV pin is driven by an
IDRAIN optocoupler. The collector of the optocoupler transistor is
connected to the EN/UV pin and the emitter is connected to
VDRAIN the SOURCE pin. The optocoupler LED is connected in series
with a Zener diode across the DC output voltage to be regulated.
PI-2749-082305 When the output voltage exceeds the target regulation voltage
level (optocoupler LED voltage drop plus Zener voltage), the
Figure 6. Operation at Near Maximum Loading. optocoupler LED will start to conduct, pulling the EN/UV pin
low. The Zener diode can be replaced by a TL431 reference
circuit for improved accuracy.
ON/OFF Operation with Current Limit State Machine
The internal clock of the TinySwitch-III runs all the time. At
the beginning of each clock cycle, it samples the EN/UV pin to
decide whether or not to implement a switch cycle, and based
on the sequence of samples over multiple cycles, it determines
the appropriate current limit. At high loads, the state machine
sets the current limit to its highest value. At lighter loads, the
state machine sets the current limit to reduced values.
VEN VEN
CLOCK CLOCK
DCMAX DCMAX
IDRAIN IDRAIN
VDRAIN VDRAIN
PI-2667-082305 PI-2377-082305
Figure 7. Operation at Moderately Heavy Loading. Figure 8. Operation at Medium Loading.
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TNY274-280 200 PI-2381-1030801
VEN 100 VDC-INPUT
CLOCK
DCMAX 0
IDRAIN 10
5 V
BYPASS
0
400
200 V
DRAIN
0
0 1 2
Time (ms)
VDRAIN Figure 11. Power-Up Without Optional External UV Resistor
Connected to EN/UV Pin.
PI-2661-082305 PI-2348-030801
Figure 9. Operation at Very Light Load. 200
100 VDC-INPUT
At near maximum load, TinySwitch-III will conduct during 0
nearly all of its clock cycles (Figure 6). At slightly lower load,
it will "skip" additional cycles in order to maintain voltage 400
regulation at the power supply output (Figure 7). At medium 300
loads, cycles will be skipped and the current limit will be reduced
(Figure 8). At very light loads, the current limit will be reduced 200 V
even further (Figure 9). Only a small percentage of cycles will DRAIN
occur to satisfy the power consumption of the power supply.
100
The response time of the ON/OFF control scheme is very fast 0
compared to PWM control. This provides tight regulation and
excellent transient response. 0 .5 1
Time (s)
Figure 12. Normal Power-Down Timing (without UV).
200 PI-2383-030801 PI-2395-030801
100 V 200
DC-INPUT
0 100 V
DC-INPUT
10 0
5 V 400
BYPASS
0 300
400 200 V
DRAIN
200 V 100
DRAIN
0 0
0 1 2 0 2.5 5
Time (ms) Time (s)
Figure 10. Power-Up with Optional External UV Resistor (4 M) Figure 13. Slow Power-Down Timing with Optional External
Connected to EN/UV Pin. (4 M) UV Resistor Connected to EN/UV Pin.
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Power Up/Down TNY274-280
The TinySwitch-III requires only a 0.1 F capacitor on the
BYPASS/MULTI-FUNCTION pin to operate with standard Functional Description above). This has two main benefits.
current limit. Because of its small size, the time to charge this First, for a nominal application, this eliminates the cost of a
capacitor is kept to an absolute minimum, typically 0.6 ms. The bias winding and associated components. Secondly, for battery
time to charge will vary in proportion to the BYPASS/MULTI- charger applications, the current-voltage characteristic often
FUNCTION pin capacitor value when selecting different current allows the output voltage to fall close to zero volts while still
limits. Due to the high bandwidth of the ON/OFF feedback, delivering power. TinySwitch-III accomplishes this without a
there is no overshoot at the power supply output. When an forward bias winding and its many associated components. For
external resistor (4 M) is connected from the positive DC applications that require very low no-load power consumption
input to the EN/UV pin, the power MOSFET switching will (50 mW), a resistor from a bias winding to the BYPASS/
be delayed during power-up until the DC line voltage exceeds MULTI-FUNCTION pin can provide the power to the chip.
the threshold (100 V). Figures 10 and 11 show the power-up The minimum recommended current supplied is 1 mA. The
timing waveform in applications with and without an external BYPASS/MULTI-FUNCTION pin in this case will be clamped
resistor (4 M) connected to the EN/UV pin. at 6.4 V. This method will eliminate the power draw from the
DRAIN pin, thereby reducing the no-load power consumption
Under startup and overload conditions, when the conduction time and improving full-load efficiency.
is less than 400 ns, the device reduces the switching frequency
to maintain control of the peak drain current. Current Limit Operation
Each switching cycle is terminated when the DRAIN current
During power-down, when an external resistor is used, the reaches the current limit of the device. Current limit operation
power MOSFET will switch for 64 ms after the output loses provides good line ripple rejection and relatively constant power
regulation. The power MOSFET will then remain off without delivery independent of input voltage.
any glitches since the under-voltage function prohibits restart
when the line voltage is low. BYPASS/MULTI-FUNCTION Pin Capacitor
The BYPASS/MULTI-FUNCTION pin can use a ceramic
Figure 12 illustrates a typical power-down timing waveform. capacitor as small as 0.1 F for decoupling the internal power
Figure 13 illustrates a very slow power-down timing waveform supply of the device. A larger capacitor size can be used to adjust
as in standby applications. The external resistor (4 M) is the current limit. For TNY275-280, a 1 F BP/M pin capacitor
connected to the EN/UV pin in this case to prevent unwanted will select a lower current limit equal to the standard current
restarts. limit of the next smaller device and a 10 F BP/M pin capacitor
will select a higher current limit equal to the standard current
No bias winding is needed to provide power to the chip limit of the next larger device. The higher current limit level of
because it draws the power directly from the DRAIN pin (see the TNY280 is set to 850 mA typical. The TNY274 MOSFET
does not have the capability for increased current limit so this
feature is not available in this device.
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TNY274-280
VR1 C5 D7 L2 +12 V, 1 A
P6KE150A 2.2 nF BYV28-200 Ferrite Bead
250 VAC 3.5 7.6 mm
NC T1 8
D1 D2 R2 1 6 C10 C11 J3
1N4007 1N4007 100 100 F
F1 1000 F
J1 3.15 A C1 C4 25 V 25 V J4
6.8 F 10 nF
85-265 RV1 400 V C2 R1 1 kV RTN
VAC 275 VAC 1 k
22 F 3 R7
J2 400 V
D3 4 20
1N4007 R5* D5 2 D6
3.6 M 1N4007GP 5 UF4003
D4 L1 VR2 R3
1N4007 1 mH 1N5255B 47
1/8 W
28 V C6 VR3
BZX79-C11
1 F
60 V 11 V
*R5 and R8 are optional R8* R6
components
21 k 390
C7 is configurable to adjust 1% 1/8 W
U1 current limit, see circuit
description D U2
EN/UV PC817A
S BP/M
S R4
TinySwitch-III C7 2 k
1/8 W
U1 100 nF
TNY278P 50 V
PI-4244-021406
Figure 14. TNY278P, 12 V, 1 A Universal Input Power Supply.
Applications Example LED forward drop, current will flow in the optocoupler LED.
This will cause the transistor of the optocoupler to sink current.
The circuit shown in Figure 14 is a low cost, high efficiency, When this current exceeds the ENABLE pin threshold current
flyback power supply designed for 12 V, 1 A output from the next switching cycle is inhibited. When the output voltage
universal input using the TNY278. falls below the feedback threshold, a conduction cycle is allowed
to occur and, by adjusting the number of enabled cycles, output
The supply features under-voltage lockout, primary sensed regulation is maintained. As the load reduces, the number of
output overvoltage latching shutdown protection, high enabled cycles decreases, lowering the effective switching
efficiency (>80%), and very low no-load consumption frequency and scaling switching losses with load. This provides
(<50 mW at 265 VAC). Output regulation is accomplished using almost constant efficiency down to very light loads, ideal for
a simple zener reference and optocoupler feedback. meeting energy efficiency requirements.
The rectified and filtered input voltage is applied to the primary As the TinySwitch-III devices are completely self-powered,
winding of T1. The other side of the transformer primary is there is no requirement for an auxiliary or bias winding on the
driven by the integrated MOSFET in U1. Diode D5, C2, R1, transformer. However by adding a bias winding, the output
R2, and VR1 comprise the clamp circuit, limiting the leakage overvoltage protection feature can be configured, protecting
inductance turn-off voltage spike on the DRAIN pin to a safe the load against open feedback loop faults.
value. The use of a combination a Zener clamp and parallel
RC optimizes both EMI and energy efficiency. Resistor R2 When an overvoltage condition occurs, such that bias voltage
allows the use of a slow recovery, low cost, rectifier diode by exceeds the sum of VR2 and the BYPASS/MULTIFUNCTION
limiting the reverse current through D5. The selection of a (BP/M) pin voltage (28 V+5.85 V), current begins to flow into the
slow diode also improves efficiency and conducted EMI but BP/M pin. When this current exceeds 5 mA the internal latching
should be a glass passivated type, with a specified recovery shutdown circuit in TinySwitch-III is activated. This condition
time of 2 s. is reset when the BP/M pin voltage drops below 2.6 V after
removal of the AC input. In the example shown, on opening
The output voltage is regulated by the Zener diode VR3. When the loop, the OVP trips at an output of 17 V.
the output voltage exceeds the sum of the Zener and optocoupler
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2/06
For lower no-load input power consumption, the bias winding TNY274-280
may also be used to supply the TinySwitch-III device. Resistor
R8 feeds current into the BP/M pin, inhibiting the internal high Key Application Considerations
voltage current source that normally maintains the BP/M pin
capacitor voltage (C7) during the internal MOSFET off time. TinySwitch-lll Design Considerations
This reduces the no-load consumption of this design from
140 mW to 40 mW at 265 VAC. Output Power Table
The data sheet output power table (Table 1) represents the
Under-voltage lockout is configured by R5 connected between minimum practical continuous output power level that can be
the DC bus and EN/UV pin of U1. When present, switching obtained under the following assumed conditions:
is inhibited until the current in the EN/UV pin exceeds 25 A.
This allows the startup voltage to be programmed within the 1. The minimum DC input voltage is 100 V or higher for
normal operating input voltage range, preventing glitching of 85 VAC input, or 220 V or higher for 230 VAC input or
the output under abnormal low voltage conditions and also on 115 VAC with a voltage doubler. The value of the input
removal of the AC input. capacitance should be sized to meet these criteria for AC
input designs.
In addition to the simple input pi filter (C1, L1, C2) for
differential mode EMI, this design makes use of E-ShieldTM 2. Efficiency of 75%.
shielding techniques in the transformer to reduce common 3. Minimum data sheet value of I2f.
mode EMI displacement currents, and R2 and C4 as a damping 4. Transformer primary inductance tolerance of 10%.
network to reduce high frequency transformer ringing. These 5. Reflected output voltage (VOR) of 135 V.
techniques, combined with the frequency jitter of TNY278, 6. Voltage only output of 12 V with a fast PN rectifier diode.
give excellent conducted and radiated EMI performance with 7. Continuous conduction mode operation with transient KP*
this design achieving >12 dBV of margin to EN55022 Class
B conducted EMI limits. value of 0.25.
8. Increased current limit is selected for peak and open frame
For design flexibility the value of C7 can be selected to pick one
of the 3 current limits options in U1. This allows the designer power columns and standard current limit for adapter
to select the current limit appropriate for the application. columns.
9. The part is board mounted with SOURCE pins soldered to
Standard current limit (ILIMIT) is selected with a 0.1 F BP/M a sufficient area of copper and/or a heatsink is used to keep
pin capacitor and is the normal choice for typical enclosed the SOURCE pin temperature at or below 110 C.
adapter applications. 10. Ambient temperature of 50 C for open frame designs and
40 C for sealed adapters.
When a 1 F BP/M pin capacitor is used, the current
limit is reduced (ILIMITred or ILIMIT-1) offering reduced RMS *Below a value of 1, KP is the ratio of ripple to peak primary
device currents and therefore improved efficiency, but at current. To prevent reduced power capability due to premature
the expense of maximum power capability. This is ideal termination of switching cycles a transient KP limit of 0.25
for thermally challenging designs where dissipation must is recommended. This prevents the initial current limit (IINIT)
be minimized. from being exceeded at MOSFET turn on.
When a 10 F BP/M pin capacitor is used, the current For reference, Table 2 provides the minimum practical power
limit is increased (ILIMITinc or ILIMIT+1), extending the power delivered from each family member at the three selectable current
capability for applications requiring higher peak power or limit values. This assumes open frame operation (not thermally
continuous power where the thermal conditions allow. limited) and otherwise the same conditions as listed above.
These numbers are useful to identify the correct current limit
Further flexibility comes from the current limits between adjacent to select for a given device and output power requirement.
TinySwitch-III family members being compatible. The reduced
current limit of a given device is equal to the standard current Overvoltage Protection
limit of the next smaller device and the increased current limit is The output overvoltage protection provided by TinySwitch-III
equal to the standard current limit of the next larger device. uses an internal latch that is triggered by a threshold current
of approximately 5.5 mA into the BP/M pin. In addition to an
internal filter, the BP/M pin capacitor forms an external filter
providing noise immunity from inadvertent triggering. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE
and BP/M pins of the device.
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2/06
TNY274-280
OUTPUT POWER TABLE
PRODUCT 230 VAC 15% 85-265 VAC
ILIMIT
TNY274 P or G ILIMIT-1 ILIMIT ILIMIT+1 ILIMIT-1 8.5 ILIMIT+1
TNY275 P or G 9 10.9 9.1 7.1 9.3 7.1
TNY276 P or G 11.9 11.8
TNY277 P or G 10.8 12 15.1 8.4 15.3 15.1
TNY278 P or G 11.8 18.6 18.5
TNY279 P or G 15.1 15.3 19.4 9.2 22 21.8
TNY280 P or G 19.4 25.4 25.2
23.7 19.6 23.7 11.8 28.5
28
24 28 15.1
28.4 32.2 18.5
32.7 36.6 21.8
Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.
For best performance of the OVP function, it is recommended practically eliminates audible noise. Vacuum impregnation
that a relatively high bias winding voltage is used, in the range of of the transformer should not be used due to the high primary
15 V-30 V. This minimizes the error voltage on the bias winding capacitance and increased losses that result. Higher flux densities
due to leakage inductance and also ensures adequate voltage are possible, however careful evaluation of the audible noise
during no-load operation from which to supply the BP/M pin performance should be made using production transformer
for reduced no-load consumption. samples before approving the design.
Selecting the Zener diode voltage to be approximately 6 V Ceramic capacitors that use dielectrics such as Z5U, when used
above the bias winding voltage (28 V for 22 V bias winding) in clamp circuits, may also generate audio noise. If this is the
gives good OVP performance for most designs, but can be case, try replacing them with a capacitor having a different
adjusted to compensate for variations in leakage inductance. dielectric or construction, for example a film type.
Adding additional filtering can be achieved by inserting a low
value (10 to 47 ) resistor in series with the bias winding TinySwitch-lll Layout Considerations
diode and/or the OVP Zener as shown by R7 and R3 in
Figure 14. The resistor in series with the OVP Zener also limits Layout
the maximum current into the BP/M pin. See Figure 15 for a recommended circuit board layout for
TinySwitch-III.
Reducing No-load Consumption
As TinySwitch-III is self-powered from the BP/M pin capacitor, Single Point Grounding
there is no need for an auxillary or bias winding to be provided Use a single point ground connection from the input filter capacitor
on the transformer for this purpose. Typical no-load consumption to the area of copper connected to the SOURCE pins.
when self-powered is <150 mW at 265 VAC input. The addition
of a bias winding can reduce this down to <50 mW by supplying Bypass Capacitor (CBP)
the TinySwitch-III from the lower bias voltage and inhibiting the The BP/M pin capacitor should be located as near as possible
internal high voltage current source. To achieve this, select the to the BP/M and SOURCE pins.
value of the resistor (R8 in Figure 14) to provide the data sheet
DRAIN supply current. In practice, due to the reduction of the Primary Loop Area
bias voltage at low load, start with a value equal to 40% greater The area of the primary loop that connects the input filter
than the data sheet maximum current, and then increase the value capacitor, transformer primary and TinySwitch-III together
of the resistor to give the lowest no-load consumption. should be kept as small as possible.
Audible Noise Primary Clamp Circuit
The cycle skipping mode of operation used in TinySwitch-III A clamp is used to limit peak voltage on the DRAIN pin at turn
can generate audio frequency components in the transformer. off. This can be achieved by using an RCD clamp or a Zener
To limit this audible noise generation the transformer should (~200 V) and diode clamp across the primary winding. In all
be designed such that the peak core flux density is below cases, to minimize EMI, care should be taken to minimize the
3000 Gauss (300 mT). Following this guideline and using the circuit path from the clamp components to the transformer and
standard transformer production technique of dip varnishing TinySwitch-III.
10 E
2/06
TOP VIEW Input Filter TNY274-280
Capacitor
HV DC Output Filter
INPUT Y1- Capacitor
+-Capacitor
CBP S SSS
- T
+ TinySwitch-III r
a
EN/UV BP/M D n
s
f
o
r
m
e
r
Opto-
coupler
DC
Maximize hatched copper OUT
areas ( ) for optimum
heatsinking
PI-4278-013006
Figure 15. Recommended Circuit Board Layout for TinySwitch-III with Under-Voltage Lock Out Resistor.
Thermal Considerations Optocoupler
The four SOURCE pins are internally connected to the IC lead Place the optocoupler physically close to the TinySwitch-III
frame and provide the main path to remove heat from the device. to minimizing the primary-side trace lengths. Keep the high
Therefore all the SOURCE pins should be connected to a copper current, high voltage drain and clamp traces away from the
area underneath the TinySwitch-III to act not only as a single optocoupler to prevent noise pick up.
point ground, but also as a heatsink. As this area is connected
to the quiet source node, this area should be maximized for Output Diode
good heatsinking. Similarly for axial output diodes, maximize For best performance, the area of the loop connecting the
the PCB area connected to the cathode. secondary winding, the output diode and the output filter
capacitor, should be minimized. In addition, sufficient copper
Y-Capacitor area should be provided at the anode and cathode terminals
The placement of the Y-capacitor should be directly from the of the diode for heatsinking. A larger area is preferred at the
primary input filter capacitor positive terminal to the common/ quiet cathode terminal. A large anode area can increase high
return terminal of the transformer secondary. Such a placement frequency radiated EMI.
will route high magnitude common mode surge currents away
from the TinySwitch-III device. Note if an input (C, L, C)
EMI filter is used then the inductor in the filter should be placed
between the negative terminals of the input filter capacitors.
11 E
2/06
TNY274-280 startup. Repeat under steady state conditions and verify that
the leading edge current spike event is below ILIMIT(Min) at the
Quick Design Checklist end of the t . LEB(Min) Under all conditions, the maximum drain
current should be below the specified absolute maximum
As with any power supply design, all TinySwitch-III designs ratings.
should be verified on the bench to make sure that component 3. Thermal Check At specified maximum output power,
specifications are not exceeded under worst case conditions. The minimum input voltage and maximum ambient temperature,
following minimum set of tests is strongly recommended: verify that the temperature specifications are not exceeded
for TinySwitch-III, transformer, output diode, and output
1. Maximum drain voltage Verify that VDS does not exceed capacitors. Enough thermal margin should be allowed for
650 V at highest input voltage and peak (overload) output part-to-part variation of the RDS(ON) of TinySwitch-III as
power. The 50 V margin to the 700 V BVDSS specification specified in the data sheet. Under low line, maximum power,
gives margin for design variation. a maximum TinySwitch-III SOURCE pin temperature of
110 C is recommended to allow for these variations.
2. Maximum drain current At maximum ambient temperature,
maximum input voltage and peak output (overload) power,
verify drain current waveforms for any signs of transformer
saturation and excessive leading edge current spikes at
12 E
2/06
TNY274-280
ABSOLUTE MAXIMUM RATINGS(1,5)
DRAIN Voltage ................................................-0.3 V to 700 V Lead Temperature(4) ....................................................... 260 C
DRAIN Peak Current: TNY274.......................400 (750) mA(2)
TNY275.....................560 (1050) mA(2) Notes:
TNY276.....................720 (1350) mA(2) 1. All voltages referenced to SOURCE, TA = 25 C.
TNY277.....................880 (1650) mA(2) 2. The higher peak DRAIN current is allowed while the
TNY278...................1040 (1950) mA(2) DRAIN voltage is simultaneously less than 400 V.
TNY279 ................. 1200 (2250) mA(2) 3. Normally limited by internal circuitry.
TNY280 ................. 1360 (2550) mA(2) 4. 1/16 in. from case for 5 seconds.
EN/UV Voltage ................................................... -0.3 V to 9 V 5. Maximum ratings specified may be applied one at a time,
EN/UV Current ........................................................... 100 mA without causing permanent damage to the product.
BP/M Voltage ......................................................-0.3 V to 9 V Exposure to Absolute Maximum Rating conditions for
Storage Temperature ......................................-65 C to 150 C extended periods of time may affect product reliability.
Operating Junction Temperature(3) .................-40 C to 150 C
THERMAL IMPEDANCE
Thermal Impedance: P or G Package: Notes:
(JA) ........................... 70 C/W(2); 60 C/W(3)
(JC)(1) ............................................... 11 C/W 1. Measured on the SOURCE pin close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
CONTROL FUNCTIONS
Output Frequency fOSC TJ = 25 C Average 124 132 140 kHz
in Standard Mode See Figure 4 Peak-Peak Jitter
8
Maximum Duty DCMAX S1 Open 62 65 %
Cycle
EN/UV Pin Upper
Turnoff Threshold IDIS -150 -115 -90 A
Current
EN/UV Pin VEN IEN/UV = 25 A 1.8 2.2 2.6 V
Voltage IEN/UV = -25 A
0.8 1.2 1.6
IS1 EN/UV Current > IDIS (MOSFET Not 290 A
Switching) See Note A
TNY274 275 360
TNY275
DRAIN Supply TNY276 295 400
Current TNY277
EN/UV Open TNY278 310 430
TNY279
IS2 (MOSFET TNY280 365 460 A
Switching at fOSC)
See Note B 445 540
510 640
630 760
13 E
2/06
TNY274-280
Parameter Symbol Conditions Min Typ Max Units
SOURCE = 0 V; TJ = -40 to 125 C -6 -3.8
See Figure 16 -8.3 -5.4
-9.7 -6.8
(Unless Otherwise Specified) -4.1 -2.3
-5 -3.5
CONTROL FUNCTIONS (cont.) -6.6 -4.6
5.6 5.85
VBP/M = 0 V, TNY274 0.80 0.95 -1.8
TJ = 25 C TNY275-279 6.0 6.4
ICH1 See Note C, D -2.5
VBP/M = 4 V, TNY280 22.5 25
BP/M Pin Charge TJ = 25 C TNY274 -3.9
Current See Note C, D TNY275-279 233 250 mA
TNY280 256 275
ICH2 326 350 -1
419 450
512 550 -1.5
605 650
698 750 -2.1
196 210
BP/M Pin Voltage VBP/M See Note C 233 250 6.15 V
BP/M Pin Voltage VBP/MH 1.20 V
Hysteresis
BP/M Pin Shunt VSHUNT IBP = 2 mA 6.7 V
Voltage TJ = 25 C
EN/UV Pin Line
Under-Voltage ILUV 27.5 A
Threshold
CIRCUIT PROTECTION
TNY274 di/dt = 50 mA/s 267
TJ = 25 C See Note E
294
TNY275 di/dt = 55 mA/s
Standard Current TJ = 25 C See Note E 374
Limit (BP/M TNY276 di/dt = 70 mA/s
TJ = 25 C See Note E
Capacitor = ILIMIT 481 mA
TNY277 di/dt = 90 mA/s
0.1 F) TJ = 25 C See Note E
See Note D TNY278 di/dt = 110 mA/s 588
TJ = 25 C See Note E
695
TNY279 di/dt = 130 mA/s
TJ = 25 C See Note E 802
Reduced Current ILIMITred TNY280 di/dt = 150 mA/s 233
Limit (BP/M TJ = 25 C See Note E mA
Capacitor = 1 F)
TNY274 di/dt = 50 mA/s 277
TJ = 25 C See Note E
TNY275 di/dt = 55 mA/s
TJ = 25 C See Note E
14 E
2/06
TNY274-280
Parameter Symbol Conditions Min Typ Max Units
SOURCE = 0 V; TJ = -40 to 125 C 256 275
See Figure 16 326 350
419 450
(Unless Otherwise Specified) 512 550
605 650
CIRCUIT PROTECTION (cont.) 196 210
326 350
TNY276 di/dt = 70 mA/s 419 450 305
TJ = 25 C See Note E 512 550
Reduced Current 605 650 388
Limit (BP/M TNY277 di/dt = 90 mA/s 698 750
Capacitor = 1 F) ILIMITred TJ = 25 C See Note E 791 850 499 mA
See Note D 0.9 I2f
TNY278 di/dt = 110 mA/s I2f I2f 610
TJ = 25 C See Note E 0.9
I2f 215 721
TNY279 di/dt = 130 mA/s 0.75 150
TJ = 25 C See Note E ILIMIT(MIN) 142 233
170
TNY280 di/dt = 150 mA/s 388
TJ = 25 C See Note E
Increased Current 499
Limit (BP/M TNY274 di/dt = 50 mA/s
Capacitor = 10 F) ILIMITinc TJ = 25 C See Note E, F 610 mA
See Note D
TNY275 di/dt = 55 mA/s 721
TJ = 25 C See Note E
833
TNY276 di/dt = 70 mA/s
TJ = 25 C See Note E 943
TNY277 di/dt = 90 mA/s 1.12
TJ = 25 C See Note E I2f
TNY278 di/dt = 110 mA/s 1.16
TJ = 25 C See Note E I2f
TNY279 di/dt = 130 mA/s
TJ = 25 C See Note E
TNY280 di/dt = 150 mA/s
TJ = 25 C See Note E
Power Coefficient I2f I2f = I2 Standard A2Hz
Current Limit
LIMIT(TYP) Reduced or
fOSC(TYP)
Increased
Current Limit
Initial Current Limit IINIT See Figure 19 mA
TJ = 25 C, See Note G
Leading Edge tLEB TJ = 25 C ns
Blanking Time See Note G
Current Limit tILD TJ = 25 C ns
Delay See Note G, H
Thermal Shutdown TSD 135 150 C
Temperature
15 E
2/06
TNY274-280
Parameter Symbol Conditions Min Typ Max Units
SOURCE = 0 V; TJ = -40 to 125 C 4 75
See Figure 16 1.6
5.5
(Unless Otherwise Specified) 700
50 2.6
CIRCUIT PROTECTION (cont.)
28
Thermal Shut- TSDH 42 C
down Hysteresis 19
29
BP/M Pin Shut- 14
21
down Threshold ISD 7.8 7.5 mA
11.7
Current 5.2
7.8
BP/M Pin Power- VBP/M(RESET) 3.9 3.6 V
Up Reset Thresh- 5.8
old Voltage 2.6
3.9
OUTPUT
15
ON-State RDS(ON) TNY274 TJ = 25 C 32
Resistance ID = 25 mA TJ = 100 C 48
TJ = 25 C 22
TNY275 TJ = 100 C 33
ID = 28 mA TJ = 25 C 16
TJ = 100 C 24
TNY276 TJ = 25 C 9.0
ID = 35 mA TJ = 100 C
TJ = 25 C
TNY277 TJ = 100 C 13.5
ID = 45 mA TJ = 25 C 6.0
TJ = 100 C 9.0
TNY278 TJ = 25 C 4.5
ID = 55 mA TJ = 100 C 6.7
TNY274-276 3.0
TNY279 4.5
ID = 65 mA TNY277-278
50
TNY280 TNY279-280
IDSS1 ID = 75 mA 100
OFF-State Drain IDSS2 VBP/M = 6.2 V 200 A
Leakage Current BVDSS VEN/UV = 0 V
VDS = 560 V
Breakdown TJ = 125 C
Voltage See Note I
DRAIN Supply
Voltage VBP/M = 6.2 V VDS = 375 V,
VEN/UV = 0 V TJ = 50 C
See Note G, I
VBP = 6.2 V, VEN/UV = 0 V, V
See Note J, TJ = 25 C V
16 E
2/06
TNY274-280
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
See Figure 16
(Unless Otherwise Specified)
OUTPUT (cont.)
Auto-Restart tAR TJ = 25 C 64 ms
ON-Time at fOSC DCAR See Note K
TJ = 25 C 3 %
Auto-Restart
Duty Cycle
NOTES:
A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so
low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2.
B Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BP/M pin current at 6.1 V.
C. BP/M pin is not intended for sourcing supply current to external circuitry.
D. To ensure correct current limit it is recommended that nominal 0.1 F / 1 F / 10 F capacitors are used. In
addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient
temperature range of the target application. The minimum and maximum capacitor values are guaranteed by
characterization.
Nominal BP/M Tolerance Relative to Nominal
Pin Cap Value Capacitor Value
0.1 F Min MAX
1 F
10 F -60% +100%
-50% +100%
-50% NA
E. For current limit at other di/dt values, refer to Figure 23.
F. TNY274 does not set an increased current limit value, but with a 10 F BP/M pin capacitor the current limit is the
same as with a 1 F BP/M pin capacitor (reduced current limit value).
G. This parameter is derived from characterization.
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT
specification.
I. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction
temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load
consumption calculations.
J. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up
to but not exceeding minimum BVDSS.
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to
frequency).
17 E
2/06
TNY274-280
470
5W S2
S D S1 470
2 M 10 V
S
S BP/M 50 V
S EN/UV
0.1 F 150 V
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-4079-080905
Figure 16. General Test Circuit.
DCMAX
(internal signal)
tP
EN/UV
VDRAIN tEN/UV
1
t=
P fOSC
PI-2364-012699
Figure 17. Duty Cycle Measurement. Figure 18. Output Enable Timing.
PI-4279-013006
0.8
Figure 19. Current Limit Envelope.
18 E
2/06
TNY274-280
Typical Performance Characteristics 1.2 PI-4280-012306
1.1 1.0
PI-2213-012301
Breakdown Voltage 1.0 0.8
(Normalized to 25 C) Output Frequency
(Normalized to 25 C) 0.6
0.9 0.4
-50 -25 0 25 50 75 100 125 150
Junction Temperature (C) 0.2
Figure 20. Breakdown vs. Temperature. 0
-50 -25 0 25 50 75 100 125
Junction Temperature (C)
Figure 21. Frequency vs. Temperature.
1.2 PI-4102-010906 1.4 PI-4081-082305
1.2
Standard Current Limit 1 Normalized Current Limit
(Normalized to 25 C)
1.0
0.8
0.8 Normalized
0.6 di/dt = 1
0.6 TNY274 50 mA/s
0.4 TNY275 55 mA/s Note: For the
TNY276 70 mA/s normalized current
0.4 TNY277 90 mA/s limit value, use the
0.2 TNY278 110 mA/s typical current limit
specified for the
0.2 TNY279 130 mA/s appropriate BP/M
TNY280 150 mA/s capacitor.
0 0
-50
0 50 100 150 1 2 3 4
Temperature (C) Normalized di/dt
Figure 22. Standard Current Limit vs. Temperature. Figure 23. Current Limit vs. di/dt.
300 PI-4082-082305 1000 PI-4083-082305
Scaling Factors: Drain Capacitance (pF)
250 TNY274 1.0
TNY275 1.5
Drain Current (mA)
TNY276 2.0
200 TNY277 3.5 100
TNY278 5.5 Scaling Factors:
TNY279 7.3 TNY274 1.0
150 TNY280 11 TNY275 1.5
TNY276 2.0
TNY277 3.5
100 10 TNY278 5.5
TNY279 7.3
50 TCASE=25 C TNY280 11
TCASE=100 C
0 1
0 100 200 300 400 500 600
0 2 4 6 8 10 Drain Voltage (V)
DRAIN Voltage (V) Figure 25. COSS vs. Drain Voltage.
Figure 24. Output Characteristic. 19 E
2/06
TNY274-280
Typical Performance Characteristics (cont.)
50
1.2
Scaling Factors:
Power (mW)
PI-4084-08230540TNY274 1.01.0
TNY275 1.5
Under-Voltage Threshold
(Normalized to 25 C)TNY276 2.0
PI-4281-012306TNY277 3.50.8
30 TNY278 5.5
TNY279 7.3
TNY280 11 0.6
20
0.4
10 0.2
0 200 400 600 0
0 -50 -25 0 25 50 75 100 125
Junction Temperature (C)
DRAIN Voltage (V)
Figure 27. Under-Voltage Threshold vs. Temperature.
Figure 26. Drain Capacitance Power.
20 E
2/06
TNY274-280
PART ORDERING INFORMATION TinySwitch Product Family
TNY 278 G N - TL Series Number
Package Identifier
G Plastic Surface Mount SMD-8C
P Plastic DIP-8C
Lead Finish
N Pure Matte Tin (Pb-Free)
Tape & Reel and Other Options
Blank Standard Configurations
TL Tape & Reel, 1000 pcs min./mult., G Package only
DIP-8C
-E- D S .004 (.10) Notes:
1. Package dimensions conform to JEDEC specification
.240 (6.10) .367 (9.32)
.260 (6.60) .387 (9.83) MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
Pin 1 .057 (1.45) 2. Controlling dimensions are inches. Millimeter sizes are
-D- .068 (1.73) shown in parentheses.
3. Dimensions shown do not include mold flash or other
.125 (3.18) (NOTE 6) protrusions. Mold flash or protrusions shall not exceed
.145 (3.68) .006 (.15) on any side.
-T- .015 (.38) 4. Pin locations start with Pin 1, and continue counter-clock-
MINIMUM wise to Pin 8 when viewed from the top. The notch and/or
SEATING dimple are aids in locating Pin 1. Pin 3 is omitted.
PLANE 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.100 (2.54) BSC 6. Lead width measured at package body.
7. Lead spacing measured with the leads constrained to be
perpendicular to plane T.
.120 (3.05) .008 (.20)
.140 (3.56) .015 (.38)
.014 (.36) .048 (1.22) .137 (3.48) .300 (7.62) BSC P08C
.022 (.56) .053 (1.35) MINIMUM (NOTE 7)
.300 (7.62) PI-3933-100504
T E D S .010 (.25) M .390 (9.91)
21 E
2/06
TNY274-280
SMD-8C
D S .004 (.10) .046 .060 .060 .046 Notes:
1. Controlling dimensions are
-E- .372 (9.45) .086 .080
.388 (9.86) .186 .420 inches. Millimeter sizes are
.240 (6.10) .286 shown in parentheses.
.260 (6.60) E S .010 (.25) 2. Dimensions shown do not
include mold flash or other
Pin 1 .137 (3.48) Pin 1 protrusions. Mold flash or
.100 (2.54) (BSC) MINIMUM Solder Pad Dimensions protrusions shall not exceed
-D- .006 (.15) on any side.
.125 (3.18) .367 (9.32) 3. Pin locations start with Pin 1,
.145 (3.68) .387 (9.83) and continue counter-clock-
wise to Pin 8 when viewed
.032 (.81) from the top. Pin 3 is omitted.
.037 (.94) 4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
5. Lead width measured at
package body.
6. D and E are referenced
datums on the package
body.
.057 (1.45)
.068 (1.73)
(NOTE 5)
.048 (1.22) .009 (.23) .004 (.10) .004 (.10) 0- 8
.053 (1.35) .012 (.30)
.036 (0.91) G08C
.044 (1.12)
PI-4015-013106
22 E
2/06
TNY274-280
23 E
2/06
TNY274-280
Revision Notes Date
D Release final data sheet. 1/06
E Corrected figure numbers and references. 2/06
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume
any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY
DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
PATENT INFORMATION
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S.
and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents
may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
LIFE SUPPORT POLICY
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform,
when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, EcoSmart, Clampless, E-Shield, Filterfuse,
PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
Copyright 2006, Power Integrations, Inc.
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Shenzhen, Guangdong, Phone: +39-028-928-6000 Phone: +65-6358-2160 World Wide +1-408-414-9760
China, 518031 Fax: +39-028-928-6009 Fax: +65-6358-2015
Phone: +86-755-8379-3243 e-mail: eurosales@powerint.com e-mail: singaporesales@powerint.com
Fax: +86-755-8379-5828
e-mail: chinasales@powerint.com
24 E
2/06
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采用光纤或双绞线接口、符合 EMI/EMC 标准的 10/100Mbps 以太网砖型模块参考设计
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