TLC5947
www.ti.com ................................................................................................................................................. SBVS114A JULY 2008 REVISED SEPTEMBER 2008
24-Channel, 12-Bit PWM LED Driver with
Internal Oscillator
FEATURES Noise Reduction:
4-channel grouped delay to prevent inrush
1 current
23 24 Channels, Constant Current Sink Output Operating Temperature: 40C to +85C
30-mA Capability (Constant Current Sink)
12-Bit (4096 Steps) PWM Grayscale Control APPLICATIONS
LED Power-Supply Voltage up to 30 V
VCC = 3.0 V to 5.5 V Static LED Displays
Constant Current Accuracy: Message Boards
Amusement Illumination
Channel-to-Channel = 2% (typ) TV Backlighting
Device-to-Device = 2% (typ) DESCRIPTION
CMOS Logic Level I/O
30-MHz Data Transfer Rate (Standalone) The TLC5947 is a 24-channel, constant current sink
15-MHz Data Transfer Rate (Cascaded Devices, LED driver. Each channel is individually adjustable
with 4096 pulse-width modulated (PWM) steps. PWM
SCLK Duty = 50%) control is repeated automatically with the
Shift Out Data Changes With Falling Edge to programmed grayscale (GS) data. GS data are
written via a serial interface port. The current value of
Avoid Data Shift Errors all 24 channels is set by a single external resistor.
Auto Display Repeat
4-MHz Internal Oscillator The TLC5947 has a thermal shutdown (TSD) function
Thermal Shutdown (TSD): that turns off all output drivers during an
over-temperature condition. All of the output drivers
Automatic shutdown at over temperature automatically restart when the temperature returns to
conditions normal conditions.
Restart under normal temperature
VLED VLED VLED VLED
OUT0 OUT23 OUT0 OUT23
DATA SIN SOUT SIN SOUT
SCLK
XLAT SCLK VCC SCLK VCC
BLANK
Controller
XLAT TLC5947 XLAT TLC5947
IC1 VCC BLANK ICn VCC
BLANK
IREF GND IREF GND
RIREF RIREF
3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLC5947
SBVS114A JULY 2008 REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD ORDERING NUMBER TRANSPORT MEDIA, QUANTITY
TLC5947 HTSSOP-32 PowerPADTM TLC5947DAPR Tape and Reel, 2000
TLC5947 TLC5947DAP Tube, 46
5-mm 5-mm QFN-32 TLC5947RHBR Tape and Reel, 3000
TLC5947RHB Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER TLC5947 UNIT
0.3 to +6.0 V
VCC Supply voltage: VCC OUT0 to OUT23 mA
IO Output current (dc) 38 V
VI 0.3 to VCC + 0.3 V
Input voltage range SIN, SCLK, XLAT, BLANK 0.3 to VCC + 0.3 V
VO C
Output voltage range SOUT 0.3 to +33 C
TJ(MAX) OUT0 to OUT23 +150 kV
TSTG V
Operating junction temperature 55 to +150
2
Storage temperature range
500
ESD rating Human body model (HBM)
Charged device model (CDM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE OPERATING FACTOR TA < +25C TA = +70C TA = +85C
HTSSOP-32 with ABOVE TA = +25C POWER RATING POWER RATING POWER RATING
PowerPAD soldered(1) 42.54 mW/C
HTSSOP-32 with 5318 mW 3403 mW 2765 mW
PowerPAD not soldered(2) 22.56 mW/C
27.86 mW/C 2820 mW 1805 mW 1466 mW
QFN-32 (3) 3482 mW 2228 mW 1811 mW
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) With PowerPAD not soldered onto copper area on PCB.
(3) The package thermal impedance is calculated in accordance with JESD51-5.
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RECOMMENDED OPERATING CONDITIONS
At TA= 40C to +85C, unless otherwise noted.
TLC5947
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC Characteristics: VCC = 3 V to 5.5 V OUT0 to OUT23 5.5 V
30 V
VCC Supply voltage SOUT 3.0 VCC V
SOUT 0.3 VCC V
VO Voltage applied to output OUT0 to OUT23 3 mA
mA
VIH High-level input voltage SCLK, Standalone operation 0.7 VCC 3 mA
SCLK, Duty 50%, cascade operation GND 30
VIL Low-level input voltage +85 C
SCLK = High-level pulse width +125
IOH High-level output current SCLK = Low-level pulse width C
XLAT, BLANK High-level pulse width 30
IOL Low-level output current 15 MHz
SINSCLK MHz
IOLC Constant output sink current XLATSCLK 2 ns
XLATBLANK 40 ns
TA Operating free-air temperature 40 ns
range SINSCLK ns
XLATSCLK ns
TJ Operating junction temperature ns
ns
AC Characteristics: VCC = 3 V to 5.5 V ns
fSCLK Data shift clock frequency
TWH0 Pulse duration 12
TWL0 Setup time 10
TWH1 Hold time 30
TSU0
TSU1 5
TSU2 100
TH0
TH1 30
3
10
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ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V and TA = 40C to +85C. Typical values at VCC = 3.3 V and TA = +25C, unless otherwise noted.
TLC5947
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = 3 mA at SOUT VCC 0.4 VCC V
1
VOL Low-level output voltage IOL = 3 mA at SOUT 0.4 V
27.7
IIN Input current VIN = VCC or GND at SIN, XLAT, and BLANK 1 A
ICC1 SIN/SCLK/XLAT = low, BLANK = high, VOUTn = 1 V, 0.5 3 mA
RIREF = 24 k 1
ICC2 6 mA
Supply current (VCC) SIN/SCLK/XLAT = low, BLANK = high, VOUTn = 1 V, 15
RIREF = 3.3 k 30 45 mA
ICC3 30.75
SIN/SCLK/XLAT = low, BLANK = low, VOUTn = 1 V,
ICC4 RIREF = 3.3 k, GSn = FFFh 90 mA
IOLC Constant output current SIN/SCLK/XLAT = low, BLANK = low, VOUTn = 1 V, 33.8 mA
RIREF = 1.6 k, GSn = FFFh
IOLK Output leakage current 0.1 A
All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.6 k
BLANK = high, VOUTn = 30 V, RIREF = 1.6 k,
At OUT0 to OUT23
IOLC Constant current error All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V, 2 4 %
(channel-to-channel) (1) RIREF = 1.6 k, At OUT0 to OUT23
IOLC1 Constant current error 2 7 %
(device-to-device) (2) All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V,
IOLC2 RIREF = 1.6 k 1 3 %/V
Line regulation(3)
IOLC3 All OUTn = ON, VOUTn = 1 V, VOUTfix = 1 V, 2 6 %/V
TDOWN Load regulation(4) RIREF = 1.6 k, At OUT0 to OUT23 +162
THYS +150 +175 C
VIREF Thermal shutdown threshold All OUTn = ON, VOUTn = 1 V to 3 V, VOUTfix = 1 V, +5 +10
Thermal error hysteresis RIREF = 1.6 k, At OUT0 to OUT23 1.20 +20 C
Reference voltage output Junction temperature(5) 1.16
1.24 V
Junction temperature(5)
RIREF = 1.6 k
(1) The deviation of each output from the average of OUT0OUT23 constant current. Deviation is calculated by the formula:
D (%) = IOUTn - 1 100
(IOUT0 + IOUT1 + ... + IOUT22 + IOUT23)
24 .
(2) The deviation of the OUT0OUT23 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
D (%) = (IOUT0 + IOUT1 + ... IOUT22 + IOUT23) - (Ideal Output Current) 100
24
Ideal Output Current
Ideal current is calculated by the formula:
IOUT(IDEAL) = 41 1.20
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V) 100
D (%/V) =
(IOUTn at VCC = 3.0 V) 5.5 V - 3 V
(4) Load regulation is calculated by the equation:
D (%/V) = (IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V) 100
(IOUTn at VOUTn = 1 V)
3V-1V
(5) Not tested. Specified by design.
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SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = 40C to +85C, CL = 15 pF, RL = 150 , RIREF = 1.6 k, and VLED = 5.5 V. Typical values at
VCC = 3.3 V and TA = +25C, unless otherwise noted.
TLC5947
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 Rise time SOUT 10 15 ns
tR1 OUTn
tF0 Fall time SOUT 15 40 ns
tF1 Internal oscillator OUTn
frequency 10 15 ns
fOSC
100 300 ns
2.4 4 5.6 MHz
tD0 SCLK to SOUT 15 25 ns
tD1 BLANK to OUT0 sink current off 20 40 ns
tD2 Propagation delay time OUT0 current on to OUT1/5/9/13/17/21 current on 15 24 33 ns
tD3 OUT0 current on to OUT2/6/10/14/18/22 current on 30 48 66 ns
tD4 OUT0 current on to OUT3/7/11/15/19/23 current on 45 72 99 ns
FUNCTIONAL BLOCK DIAGRAM
VCC VCC LSB MSB
SIN
SCLK 4 MHz DQ SOUT
Internal CK
XLAT Oscillator Grayscale (12 Bits 24 Channels) Data
Thermal Shift Register
BLANK Detection
IREF 0 287
GND
288
LSB MSB
Grayscale (12 Bits 24 Channels) Data
Data Latch
0 287
288
12 Bits PWM Timing Control
24
24-Channel, Constant Current Driver
OUT0 OUT1 OUT22 OUT23
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DEVICE INFORMATION
HTSSOP-32 5-mm 5-mm QFN-32(1)
DAP PACKAGE RHB PACKAGE
(TOP VIEW)
(TOP VIEW)
GND 1 32 VCC 24 OUT23
BLANK 2 31 IREF 23 OUT22
30 XLAT 22 OUT21
SCLK 3 29 SOUT 21 OUT20
SIN 4 28 OUT23 20 OUT19
27 OUT22 19 OUT18
OUT0 5 26 OUT21 18 OUT17
OUT1 6 25 OUT20 17 OUT16
OUT2 7 24 OUT19
OUT3 8 23 OUT18 SOUT 25 Thermal Pad 16 OUT15
OUT4 9 22 OUT17 XLAT 26 (Bottom Side) 15 OUT14
OUT5 10 21 OUT16 IREF 27 14 OUT13
OUT6 11 Thermal Pad 20 OUT15 VCC 28 13 OUT12
OUT7 12 (Bottom Side) 19 OUT14 GND 29 12 OUT11
OUT8 13 18 OUT13 BLANK 30 11 OUT10
OUT9 14 17 OUT12 SCLK 31 10 OUT9
OUT10 15
OUT11 16 SIN 32 9 OUT8
OUT0 1
OUT1 2
OUT2 3
OUT3 4
OUT4 5
OUT5 6
OUT6 7
OUT7 8
(1) This device is product preview.
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND via the PCB
pattern.
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TERMINAL FUNCTIONS
TERMINAL
NAME DAP RHB I/O DESCRIPTION
32
SIN 4 I Serial input for grayscale data
Serial data shift clock. Schmitt buffer input. Data present on the SIN pin are shifted into the shift
SCLK 3 31 I register with the rising edge of the SCLK pin. Data are shifted to the MSB side by 1-bit
synchronizing of the rising edge of SCLK. The MSB data appears on SOUT at the falling edge of
SCLK. A rising edge on the SCLK input is allowed 100 ns after an XLAT rising edge.
The data in the grayscale shift register are moved to the grayscale data latch with a low-to-high
XLAT 30 26 I transition on this pin. When the XLAT rising edge is input, all constant current outputs are forced
off until the next grayscale display period. The grayscale counter is not reset to zero with a rising
edge of XLAT.
Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0
BLANK 2 30 I through OUT23) are forced off, the grayscale PWM timing controller initializes, and the grayscale
counter resets to '0'. When BLANK is low, all constant current outputs are controlled by the
grayscale PWM timing controller.
IREF 31 27 I/O This pin sets the constant current value. OUT0 through OUT23 constant sink current is set to the
desired value by connecting an external resistor between IREF and GND.
Serial data output. This output is connected to the shift register placed after the MSB of the
SOUT 29 25 O grayscale shift register. Therefore, the MSB data of the grayscale shift register appears at the
falling edge of SCLK. This function reduces the data shifting errors caused by small timing
margins between SIN and SCLK.
OUT0 5 1 O Constant current output. Multiple outputs can be tied together to increase the constant current
capability. Different voltages can be applied to each output.
OUT1 6 2 O Constant current output
OUT2 7 3 O Constant current output
OUT3 8 4 O Constant current output
OUT4 9 5 O Constant current output
OUT5 10 6 O Constant current output
OUT6 11 7 O Constant current output
OUT7 12 8 O Constant current output
OUT8 13 9 O Constant current output
OUT9 14 10 O Constant current output
OUT10 15 11 O Constant current output
OUT11 16 12 O Constant current output
OUT12 17 13 O Constant current output
OUT13 18 14 O Constant current output
OUT14 19 15 O Constant current output
OUT15 20 16 O Constant current output
OUT16 21 17 O Constant current output
OUT17 22 18 O Constant current output
OUT18 23 19 O Constant current output
OUT19 24 20 O Constant current output
OUT20 25 21 O Constant current output
OUT21 26 22 O Constant current output
OUT22 27 23 O Constant current output
OUT23 28 24 O Constant current output
VCC 32 28 -- Power-supply voltage
GND 1 29 -- Power ground
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC VCC
INPUT SOUT
GND GND
Figure 1. SIN, SCLK, XLAT, BLANK Figure 2. SOUT
OUTn
GND
Figure 3. OUT0 Through OUT23
TEST CIRCUITS
VCC RL VCC
VCC
IREF OUTn VLED VCC SOUT
RIREF GND CL GND CL
Figure 4. Rise Time and Fall Time Test Circuit for OUTn Figure 5. Rise Time and Fall Time Test Circuit for SOUT
VCC OUT0
VCC
IREF OUTn
RIREF GND OUT23 VOUTn
VOUTFIX
Figure 6. Constant Current Test Circuit for OUTn
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TIMING DIAGRAMS
TWH0, TWL0, TWH1:
VCC
INPUT(1) 50%
GND
TWH TWL
TSU0, TSU1, TSU2, TH0, TH1: VCC
CLOCK GND
INPUT(1) 50% VCC
GND
TSU TH
VCC
DATA/CONTROL GND
INPUT(1) 50% VOH or VOUTn
VOL or VOUTn
(1) Input pulse rise and fall time is 1 ns to 3 ns. tR or tF
Figure 7. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4:
INPUT(1) 50%
tD
90%
OUTPUT 50%
10%
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Output Timing
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SIN GS0 GS23 GS23 GS23 GS23 GS23 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23 GS23
0A 11B 10B 9B 8B 7B 3B 2B 1B 0B 11C 10C 9C 8C 7C 6C 5C
TSU0 fSCLK TWH0 TH1 TSU1
TH0
SCLK
123 45 285 286 287 288 TWH1 1234567
TWL0
XLAT
TSU2
TWH1
BLANK
Grayscale tD1
Previous Grayscale Data
Latch Data Latest Grayscale Data
(Internal) Counter 4094 4096
Oscillator Value 4093 4095 1 2 3 4 fOSC 0 0 0 0 1 2 3 4 5 0 0 0 0 0 1 2
Clock
(Internal)
SOUT GS23 tD0 GS23 GS23 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23 GS23
11A 8A 7A 3A 2A 1A 0A 11B 10B 9B 8B 7B 6B 5B
OUT0/4/8/ GS23 GS23
12/16/20(1) OFF 10A 9A tR0/tF0
ON
OFF tR1 tF1
ON
OUT1/5/9/
13/17/21(1)
OUT2/6/10/ OFF tD2
14/18/22(1) ON tD3
OUT3/7/11/ OFF tD4
15/19/23(1) ON
(1) GS data = FFFh.
Figure 9. Grayscale Data Write and OUTn Operation Timing
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TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25C, unless otherwise noted.
REFERENCE RESISTOR POWER DISSIPATION RATE
vs OUTPUT CURRENT vs FREE-AIR TEMPERATURE
100000 6000
Reference Resistor (W) Power Dissipation Rate (mW) 5000 TLC5947DAP
PowerPAD Soldered
4000
24600 TLC5947RHB
10000 9840 3000
TLC5947DAP
1000 4920
0 2000 PowerPAD Not Soldered
3280
2460 1968
1640
1000
0
5 10 15 20 25 30 -40 -20 0 20 40 60 80 100
Output Current (mA) Free-Air Temperature (C)
Figure 10. Figure 11.
OUTPUT CURRENT vs OUTPUT CURRENT vs
OUTPUT VOLTAGE OUTPUT VOLTAGE
35 TA = +25C IO = 30 mA 35
30 IO = 30 mA
25 IO = 25 mA
20 34
IO = 20 mA
33
Output Current (mA) Output Current (mA) 32
31
IO = 15 mA 30
15
29
IO = 10 mA 28 TA = -40C
10 TA = +25C
27 TA = +85C
IO = 2 mA IO = 5 mA
5 26
0 25
0
0 0.5 1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Voltage (V) Output Voltage (V)
Figure 12. Figure 13.
IOLC vs AMBIENT TEMPERATURE IOLC vs OUTPUT CURRENT
4 4
IO = 30 mA TA = +25C
3 3
2 2
DIOLC (%) 1 DIOLC (%) 1
0 0
-1 -1
-2 VCC = 3.3 V -2 VCC = 3.3 V
VCC = 5 V VCC = 5 V
-3 -3
0 20 40 60 80 100 5 10 15 20 25 30
-4 -4
-40 -20 0
Ambient Temperature (C) Output Current (mA)
Figure 14. Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25C, unless otherwise noted.
INTERNAL OSCILLATOR FREQUENCY CONSTANT CURRENT OUTPUT
vs AMBIENT TEMPERATURE VOLTAGE WAVEFORM
5.0 CH1-OUT0
(GSData = 001h)
Internal Oscillator Frequency (MHz) 4.5 VCC = +3.3 V CH1 (2 V/div)
CH2 (2 V/div)
4.0 CH3 (2 V/div)
3.5 VCC = +5 V IOLCMax = 30 mA
TA = +25C
3.0 CH2-OUT0 RL = 150 W
(GSData = 002h) CL = 15 pF
2.5
VLED = 5.5 V
2.0
1.5
1.0 CH3-OUT23
(GSData = 003h)
0.5
Time (100 ns/div)
0
-40 -20 0 20 35 55 70 85
Ambient Temperature (C) Figure 17.
Figure 16.
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DETAILED DESCRIPTION
SETTING FOR THE CONSTANT SINK CURRENT VALUE
The constant current value for all channels is set by an external resistor (RIREF) placed between IREF and GND.
The resistor (RIREF) value is calculated by Equation 1.
RIREF (W) = 41 VIREF (V)
IOLC (mA)
(1)
Where:
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V).
IOLC must be set in the range of 2 mA to 30 mA. The constant sink current characteristic for the external resistor
value is shown in Figure 10. Table 1 describes the constant current output versus external resistor value.
Table 1. Constant-Current Output versus External Resistor Value
IOLC (mA, Typical) RIREF ()
30 1640
25 1968
20 2460
15 3280
10 4920
5 9840
2 24600
GRAYSCALE (GS) CONTROL FUNCTION
Each constant current sink output OUT0OUT23 (OUTn) turns on (starts to sink constant current) at the fifth
rising edge of the grayscale internal oscillator clock after the BLANK signal transitions from high to low if the
grayscale data latched into the grayscale data latch are not zero. After turn-on, the number of rising edges of the
internal oscillator is counted by the 12-bit grayscale counter. Each OUTn output is turned off once its
corresponding grayscale data values equal the grayscale counter or the counter reaches 4096d (FFFh). The
PWM control operation is repeated as long as BLANK is low. OUTn is not turned on when BLANK is high. The
timing is shown in Figure 18. All outputs are turned off at the XLAT rising edge. After that, each output is
controlled again from the first clock of the internal oscillator for the next display period, based on the latest
grayscale data.
When the IC is powered on, the data in the grayscale data shift register and latch are not set to default values.
Therefore, grayscale data must be written to the GS latch before turning on the constant current output. BLANK
should be at a high level when powered on to keep the outputs off until valid grayscale data are written to the
latch. This avoids the LED being randomly illuminated immediately after power-up. If having the outputs turn on
at power-up is not a problem for the application, then BLANK does not need to be held high. The grayscale
functions can be controlled directly by grayscale data writing, even though BLANK is connected to GND.
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BLANK 1027 1030 2049 2052 3073 3076 4096
3072 3075
Counter Value 64 66 1026 1029 2048 2051 3071 3074 3077 4095
Internal 63 65
000012 3 1025 1028 1031 2047 2050 4094 12
Oscillator
Clock Grayscale counter starts to count from 5th clock of the internal oscillator clock after BLANK goes low.
OUTn OFF Drivers do not turn on when grayscale data are `0'. Dotted line indicates BLANK is high.
(GS Data = 000h) ON T = Internal CLK 1
OUTn OFF T = Internal CLK 2
(GS Data = 001h) ON
T = Internal CLK 3
OUTn OFF
(GS Data = 002h) ON
OUTn OFF
(GS Data = 003h) ON
T = Internal
CLK 63
OUTn OFF T = Internal CLK 64
(GS Data = 03Fh) ON
T = Internal CLK 65
OUTn OFF
(GS Data = 040h) ON
OUTn OFF
(GS Data = 041h) ON
OUTn OFF T = Internal CLK 1024
(GS Data = 400h) ON T = Internal CLK 1025
OUTn OFF
(GS Data = 401h) ON
OUTn OFF T = Internal CLK 2048
(GS Data = 800h) ON
OUTn OFF T = Internal CLK 3072
(GS Data = C00h) ON
OUTn OFF T = Internal CLK 4094
(GS Data = FFEh) ON T = Internal CLK 4095
OUTn OFF Figure 18. PWM Operation
(GS Data = FFFh) ON
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REGISTER CONFIGURATION
The TLC5947 has a grayscale (GS) data shift register and data latch. Both the GS data shift register and latch
are 288 bits long and are used to set the PWM timing for the constant current driver. Table 2 shows the on duty
cycle for each GS data. Figure 19 shows the shift register and data latch configuration. The data at the SIN pin
are shifted to the LSB of the shift register at the rising edge of the SCLK pin; SOUT data are shifted out on the
falling edge of SCLK. The timing diagram for data writing is shown in Figure 20. The driver on duty is controlled
by the data in the GS data latch.
Grayscale Data Shift Register (12 Bits 24 Channels)
GS Data for OUT23 GS Data for OUT22 GS Data for OUT1 GS Data for OUT0
MSB 276 275 12 11 LSB
287 0
SOUT GS Data for GS Data for GS Data for GS Data for SIN
GS Data for Bit 0 of Bit 11 of Bit 0 of OUT1 Bit 11 of GS Data for SCLK
Bit 11 of OUT23 OUT22 OUT0
OUT23 Bit 0 of OUT0
GS Data for OUT23 GS Data for OUT22 GS Data for OUT1 GS Data for OUT0
MSB 276 275 12 11 LSB
287 0
GS Data for GS Data for GS Data for GS Data for XLAT
GS Data for Bit 0 of Bit 11 of Bit 0 of OUT1 Bit 11 of GS Data for
Bit 11 of OUT23 OUT22 OUT0
OUT23 Bit 0 of OUT0
Grayscale Data Latch (12 Bits 24 Channels) 288 Bits
To PWM Timing Control Block
Figure 19. Grayscale Data Shift Register and Latch Configuration
Table 2. GS Data versus On Duty
GS DATA GS DATA GS DATA DUTY OF DRIVER TURN-ON
(Binary) (Decimal) (Hex) TIME (%)
0000 0000 0000 000 0.00
0000 0000 0001 0 001 0.02
0000 0000 0010 1 002 0.05
0000 0000 0011 2 003 0.07
3 -- --
-- -- 7FF 49.98
0111 1111 1111 2047 800 50.00
1000 0000 0000 2048 801 50.02
1000 0000 0001 2049 -- --
-- FFD 99.93
-- 4093 FFE 99.95
1111 1111 1101 4094 FFF 99.98
1111 1111 1110 4095
1111 1111 1111
Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TLC5947
TLC5947
SBVS114A JULY 2008 REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
GS data are transferred from the shift register to the latch by the rising edge of XLAT. When powered up, the
data in the grayscale shift register and data latch are not set to default values. Therefore, grayscale data must be
written to the GS latch before turning on the constant current output. BLANK should be at a high level when
powered on to avoid falsely turning on the constant current outputs due to random values in the latch at
power-up. All of the constant current outputs are forced off when BLANK is high. However, if the random values
turning on at power-up is not a concern in the application, BLANK can be at any level. GS can be controlled
correctly with the grayscale data writing functions, even if BLANK is connected to GND. Equation 2 determines
each output on duty.
On Duty (%) = GSn 100
4096 (2)
where:
GSn = the programmed grayscale value for OUTn (GSn = 0 to 4095)
SIN GS0 GS23 GS23 GS23 GS23 GS23 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23
0A 11B 10B 9B 8B 7B 11C 10C 9C 8C 7C 6C
3B 2B 1B 0B
SCLK 123 4 5 285 286 287 288 12 3456 7
XLAT
Shift Register GS0 GS23 GS23 GS23 GS23 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23
Bit 0 Data (Internal) 0A 11B 10B 9B 8B 3B 2B 1B 0B 11C 10C 9C 8C 7C 6C
Shift Register GS0 GS0 GS23 GS23 GS23 GS0 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23
Bit 1 Data (Internal) 1A 0A 11B 10B 9B 4B 3B 2B 1B 0B 11C 10C 9C 8C 7C
Shift Register GS23 GS23 GS23 GS23 GS23 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23 GS23 GS23
Bit 286 Data (Internal) 10A 9A 8A 7A 6A 1A 0A 11B 10B 9B 8B 7B 6B 5B 4B
Shift Register GS23 GS23 GS23 GS23 GS23 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23 GS23 GS23
Bit 287 Data (Internal) 11A 10A 9A 8A 7A 2A 1A 0A 11B 10B 9B 8B 7B 6B 5B
Grayscale Latch Data Previous Grayscale Latch Data Latest Grayscale Latch Data
(Internal)
SOUT GS23 GS23 GS23 GS23 GS23 GS0 GS0 GS0 GS0 GS23 GS23 GS23 GS23 GS23 GS23 GS23
11A 10A 9A 8A 7A 3A 2A 1A 0A 11B 10B 9B 8B 7B 6B 5B
Oscillator Clock 4094 4096
(Internal) 4094 4096
4093 4095 1 2 3 4 5 6 7 8
OUT0/4/8/12/16/20(1) 4093 4095 1 2 3 4
OFF
OUT1/5/9/13/17/21(1) OFF ON
OUT2/6/10/14/18/22(1) ON ON ON OFF
ON
OUT3/7/11/15/19/23(1) OFF
OFF
ON ON ON
OFF OFF
ON
ON ON
OFF
ON ON
(1) GS data = FFFh.
Figure 20. Grayscale Data Write Operation
16 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TLC5947
TLC5947
www.ti.com ................................................................................................................................................. SBVS114A JULY 2008 REVISED SEPTEMBER 2008
AUTO DISPLAY REPEAT FUNCTION
This function can repeat the total display period without any timing control signal, as shown in Figure 21.
BLANK
GS Counter Value 2048 4095 2048 4095 4095
Internal Oscillator Clock
0 0 0 0 1 2 3 2047 2049 4094 0 1 2 3 2047 2049 4094 0 1 2 3 0 0 0 0 0 0 1 2 4094 4096 1 2
Grayscale counter starts to count from the fifth clock Display period is turned on again by
of the internal oscillator clock after BLANK goes low. the auto display repeat function.
OUTn OFF
(GS Data = 001h) ON
OUTn OFF
(GS Data = 800h) ON
OUTn OFF
(GS Data = FFFh) ON
First Display Period Second Display Period First Second
(4096 Internal Clock) (4096 Internal Clock) Display Period Display Period
Four Internal Clock Intervals After BLANK Goes Low Nth Display Period Four Internal Clock Intervals After BLANK Goes Low
Figure 21. Auto Display Repeat Operation
THERMAL SHUTDOWN (TSD)
The thermal shutdown (TSD) function turns off all constant current outputs immediately when the IC junction
temperature exceeds the high temperature threshold (T(TEF) = +162 C, typ). The outputs will remain disabled as
long as the over-temperature condition exists. The outputs are turned on again at the first clock after the IC
junction temperature falls below the temperature of T(TEF) T(HYS). Figure 22 shows the TSD operation.
IC Junction Temperature (TJ) TJ < T(TEF) - T(HYS) TJ T(TEF) TJ < T(TEF) - T(HYS) TJ T(TEF)
BLANK High
Low
1 23 4096 4096 4096 4096 4096 4096
4095 1 2 4095 1 2 4095 1 2 4095 1 2 4095 1 2 4095 1 2
Internal Oscillator Clock
OFF OFF OFF
ON
OUTn ON
(GS Data = FFFh)
Figure 22. TSD Operation
Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TLC5947
TLC5947
SBVS114A JULY 2008 REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com
NOISE REDUCTION
Large surge currents may flow through the IC and the board on which the device is mounted if all 24 LED
channels turn on simultaneously at the start of each grayscale cycle. These large current surges could introduce
detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5947 turns on the LED
channels in a series delay, to provide a current soft-start feature. The output current sinks are grouped into four
groups of six channels each. The first group is OUT0, 4, 8, 12, 16, 20; the second group is OUT1, 5, 9, 13, 17,
21; the third group is OUT2, 6, 10, 14, 18, 22; and the fourth group is OUT3, 7, 11, 15, 19, 23. Each group turns
on sequentially with a small delay between groups; see Figure 9. Both turn-on and turn-off are delayed.
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package (illustrated in
Figure 11) to ensure correct operation. Equation 3 calculates the power dissipation of the device:
PD = (VCC ICC) + (VOUT IOLC N dPWM) (3)
Where:
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IOLC = LED current adjusted by RIREF resistor
N = number of OUTn driving LED at the same time
dPWM = duty ratio defined by GS value
18 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TLC5947
PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2012
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package Pins Package Qty Eco Plan (2) Lead/ MSL Peak Temp (3) Samples
TLC5947DAP Drawing 32 46 Ball Finish (Requires Login)
Green (RoHS
TLC5947DAPG4 ACTIVE HTSSOP DAP & no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TLC5947DAPR Green (RoHS
TLC5947DAPRG4 ACTIVE HTSSOP DAP 32 46 & no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TLC5947RHBR Green (RoHS
TLC5947RHBRG4 ACTIVE HTSSOP DAP 32 2000 & no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TLC5947RHBT Green (RoHS
TLC5947RHBTG4 ACTIVE HTSSOP DAP 32 2000 & no Sb/Br) CU NIPDAU Level-3-260C-168 HR
Green (RoHS
ACTIVE QFN RHB 32 3000 & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
ACTIVE QFN RHB 32 3000 & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
ACTIVE QFN RHB 32 250 & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
ACTIVE QFN RHB 32 250 & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION 14-Jul-2012
*All dimensions are nominal
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing
2000 Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
3000
250 (mm) W1 (mm)
TLC5947DAPR HTSSOP DAP 32 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
TLC5947RHBR QFN RHB 32
TLC5947RHBT QFN RHB 32 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
Pack Materials-Page 1
www.ti.com PACKAGE MATERIALS INFORMATION
14-Jul-2012
*All dimensions are nominal Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
Device HTSSOP 2000 367.0 367.0 45.0
QFN DAP 32 3000 367.0 367.0 35.0
TLC5947DAPR QFN 250 210.0 185.0 35.0
TLC5947RHBR RHB 32
TLC5947RHBT
RHB 32
Pack Materials-Page 2
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