1 TC7106
TC7106A
TC7107
TC7107A
3-1/2 DIGIT A/D CONVERTERS 2
FEATURES GENERAL DESCRIPTION
s Internal Reference with Low Temperature Drift The TC7106A and TC7107A 3-1/2 digit direct-display
TC7106/7 ....................................... 80ppm/C Typical
TC7106A/7A .................................. 20ppm/C Typical drive analog-to-digital converters allow existing 7106/7107
s Drives LCD (TC7106) or LED (TC7107) Display based systems to be upgraded. Each device has a preci-
Directly
sion reference with a 20ppm/C max temperature coeffi-
s Guaranteed Zero Reading With Zero Input
s Low Noise for Stable Display cient. This represents a 4 to 7 times improvement over
s Auto-Zero Cycle Eliminates Need for Zero
3 similar 3-1/2 digit converters. Existing 7106 and 7107 based
Adjustment
s True Polarity Indication for Precision Null systems may be upgraded without changing external pas-
sive component values. The TC7107A drives common
Applications
s Convenient 9 V Battery Operation (TC7106A) anode light emitting diode (LED) displays directly with 8mA
s High Impedance CMOS Differential Inputs .... 1012
s Differential Reference Inputs Simplify Ratiometric per segment. A low-cost, high-resolution indicating meter
Measurements requires only a display, four resistors, and four capacitors.
s Low Power Operation ..................................... 10mW
The TC7106A low power drain and 9V battery operation
make it suitable for portable applications.
ORDERING INFORMATION 4 The TC7106A/TC7107A reduces linearity error to less
than 1 count. Rollover error the difference in readings for
equal magnitude but opposite polarity input signals is
below 1 count. High impedance differential inputs offer
PART CODE TC710X X X XXX 1pA leakage current and a 1012 input impedance. The
differential reference input allows ratiometric measurements
} 6 = LCD for ohms or bridge transducer measurements. The
7 = LED 15VPP noise performance guarantees a "rock solid" read-
A or blank* ing. The auto-zero cycle guarantees a zero display read- 5
R (reversed pins) or blank (CPL pkg only) ing with a zero-volts input.
* "A" parts have an improved reference TC
Package Code (see below): 0.1F
Package Pin Layout Temperature + 1M 34 33 LCD DISPLAY (TC7106/A) OR
Code Package Range 0.01F CR+EF CREF COMMON ANODE LED
Formed Leads ANALOG DISPLAY (TC7107/A)
-- 0C to +70C INPUT 31 VI+N 219
0C to +70C 2225 SEGMENT
Normal 0C to +70C DRIVE
Normal 25C to +85C
CKW 44-Pin PQFP Normal 25C to +85C 30 VIN POL 20 BACKPLANE 6
CLW 44-Pin PLCC 32 ANALOG MINUS SIGN DRIVE 7
CPL 40-Pin PDIP BP
IPL 40-Pin PDIP COMMON V+ 21
IJL 40-Pin CerDIP
1
28 VBUFF TC7106/A 24k +
TC7107/A 1k 9V
47k V+REF 36 VREF
0.22F 0.47F
29 CAZ VREF 35 100mV
AVAILABLE PACKAGES 27 VINT V 26
OSC2 OSC3 OSC1 TO ANALOG
COMMON (PIN 32)
39 38 COSC 40
ROSC 100pF 3 CONVERSIONS/SEC
100k 200mV FULL SCALE
40-Pin Plastic DIP 40-Pin CERDIP
Figure 1. TC7106/A/7/A Typical Operating Circuit
44-Pin Plastic Quad Flat 44-Pin Plastic Chip 8
Package Formed Leads Carrier PLCC
TELCOM SEMICONDUCTOR, INC. TC7106/6A/7/7A-7 11/4/96
3-183
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
ABSOLUTE MAXIMUM RATINGS* Analog Input Voltage (either input) (Note 1) ......... V+ to V
Reference Input Voltage (either input) ................. V+ to V
TC7106A Clock Input ....................................................... GND to V+
Power Dissipation (Note 2) (TA 70C)
Supply Voltage (V+ to V) ........................................... 15 V
Analog Input Voltage (either input) (Note 1) ......... V+ to V 40-Pin CerDIP Package ...................................2.29W
Reference Input Voltage (either input) ................. V+ to V 40-Pin Plastic DIP ............................................. 1.23W
Clock Input ........................................................ Test to V+ 44-Pin PLCC .....................................................1.23W
Package Power Dissipation (Note 2) (TA 70C) 44-Pin PQFP .................................................... 1.00W
Operating Temperature
CerDIP ..............................................................2.29W "C" Devices ............................................ 0C to +70C
Plastic DIP ........................................................1.23W "I" Devices ........................................ 25C to +85C
PLCC ................................................................1.23W Storage Temperature ............................ 65C to +150C
PQFP ................................................................1.00W Lead Temperature (Soldering, 10 sec) ................. +300C
Operating Temperature
"C" Devices ............................................ 0C to +70C *Static-sensitive device. Unused devices must be stored in conductive
"I" Devices ........................................ 25C to +85C material. Protect devices from static discharge and static fields. Stresses
Storage Temperature ............................ 65C to +150C above those listed under Absolute Maximum Ratings may cause perma-
Lead Temperature (Soldering, 60 sec) ................... 300C nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
TC7107A indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
Supply Voltage may affect device reliability.
V+ ................................................................................................ +6 V
V ............................................................................................... 9 V
ELECTRICAL CHARACTERISTICS (Note 3)
TC7106/A & TC7107/A
Parameters Test Conditions Min Typ Max Unit
Zero Input Reading
VIN = 0.0 V 000.0 000.0 +000.0 Digital
Ratiometric Reading Full-Scale = 200.0mV Reading
VIN = VREF 999 999/1000 1000 Digital
Roll-Over Error (Difference in VREF = 100 mV Reading
Reading for Equal Positive and VIN = +V+IN 200mV 1 0.2 +1 Counts
Negative Reading Near Full-Scale)
Linearity (Max. Deviation From Full-Scale = 200mV 1 0.2 +1 Counts
Best Straight Line Fit) or Full-Scale = 2.000 V
Common-Mode VCM = 1V, VIN = 0V, -- 50 -- V/V
Rejection Ratio (Note 4) Full Scale = 200.0 mV
Noise (Pk Pk Value Not -- 15 -- V
Exceeded 95% of Time) VIN = 0 V
Leakage Current @ Input Full-Scale = 200.0mV -- 1 10 pA
Zero Reading Drift
VIN = 0 V -- 0.2 1 V/C
Scale Factor VIN = 0 V
Temperature Coefficient "C" Device = 0C to +70C -- 1.0 2 V/C
VIN = 0 V
Supply Current (Does Not "I" Device = 25C to +85C -- 1 5 ppm/C
Include LED Current For TC7107/A) VIN = 199.0mV,
"C" Device = 0C to +70C -- -- 20 ppm/C
(Ext. Ref = 0ppmC)
VIN = 199.0mV -- 0.8 1.8 mA
"I" Device = 25C to +85C
VIN = 0
3-184 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
ELECTRICAL CHARACTERISTICS (Cont.) (Note 3)
TC7106/A & TC7107/A 2
Parameters Test Conditions Min Typ Max Unit
Analog Common Voltage 25k Between Common 2.7 3.05 3.35 V
(With Respect to Pos. Supply) and Pos. Supply
Temp. Coeff. of 25k Between Common
Analog Common
(With Respect and Pos. Supply
to Pos. Supply)
0C TA +70C 7106A/7A 20 50 ppm/C
Temp. Coeff. of
Analog Common ("C", Commercial Temp. Range Devices) 7106/7 80 -- 3 ppm/C
(With Respect
to Pos. Supply) 25k Between Common
TC7106A ONLY Pk Pk and Pos. Supply
Segment Drive Voltage (Note 5)
25C TA 85C -- -- 75 ppm/C
TC7106A ONLY Pk Pk
Backplane Drive Voltage (Note 5) ("I," Industrial Temp. Range Devices)
TC7107A ONLY V+ to V = 9V 4 5 6 V
Segment Sinking Current (Except Pin 19)
V+ to V = 9V 4 5 6 V
TC7107A ONLY
Segment Sinking Current (Pin 19) V+ = 5.0V 5 8.0 -- mA 4
Segment Voltage = 3V
V+ = 5.0V 10 16 -- mA
Segment Voltage = 3V
NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to 100A. 5
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. Unless otherwise noted, specifications apply to both the TC7106/A and TC7107/A at TA = 25C, fCLOCK = 48 kHz. Parts are tested in the
circuit of Figure 1.
4. Refer to "Differential Input" discussion.
5. Backplane drive is in phase with segment drive for "OFF" segment, 180 out of phase for "ON" segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
6
7
TELCOM SEMICONDUCTOR, INC. 8
3-185
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN CONFIGURATIONS
V+ 1 NORMAL PIN 40 OSC 1 OSC1 1 REVERSE PIN 40 V+
D1 2 CONFIGURATION 39 OSC2 OSC2 2 CONFIGURATION 39 D1
C1 3 38 OSC 3 OSC 3 3 38 C1
B1 4 37 TEST TEST 4 37 B1
1's A1 5 36 VR+ EF VR+ EF 5 36 A1 1's
F1 6 35 VREF VREF 6 35 F1
G1 7 34 CR+EF CR+EF 7 34 G1
E1 8 33 CREF CREF 8 33 E1
D2 9 32 ANALOG ANALOG 9 32 D2
C2 10 COMMON COMMON 31 C2
VI+N 10
31 VI+N
B2 11 TC7106ACPL 30 V V IN 11 TC7106AIJL 30 B2
TC7107AIPL IN TC7107AIJL
10's 10's
A2 12 29 CAZ CAZ 12 29 A2
F2 13 28 VBUFF VBUFF 13 28 F2
E2 14 27 VINT VINT 14 27 E2
D3 15 26 V V 15 26 D3
100's B3 16 25 G2 G2 16 25 B3 100's
F3 17 24 C3 C3 17 24 F3
E3 18 23 A 3 100's 100's A 3 18 23 E3
1000's AB 4 19 22 G3 G3 19 22 AB4 1000's
POL 20 21 BP/GND BP/GND 20 21 POL
(7106A/7107A) (MINUS SIGN)
(MINUS SIGN) (7106A/7107A)
A1
B1
C1
D1
V+
NC
OSC1
OSC2
OSC3
TEST
REF HI
REF HI
REF LO
CREF
CREF
COM
IN HI
IN LO
A/Z
BUFF
INT
V
6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34
F1 7 TC7106ACLW 39 REF LO NC 1 TC7106ACKW 33 NC
G1 8 TC7107ACLW 38 CREF NC 2 TC7107ACKW 32 G2
E1 9 37 CREF TEST 3 (FLAT PACKAGE) 31 C3
D2 10 (PLCC) 36 COMMON OSC3 4 30 A3
C2 11 35 IN HI NC 5 29 G3
NC 12 34 NC OSC2 6 28 BP/GND
33 IN LO OSC1 7 27 POL
B2 13 32 A/Z V+ 8 26 AB4
A2 14 31 BUFF D1 9 25 E3
F2 15 30 INT C1 10 24 F3
E2 16 29 V B1 11 23 B3
D3 17
18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22
B3
F3
E3
AB4
POL
NC
BP/GND
G3
A3
C3
G2
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
3-186 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
PIN DESCRIPTION
Pin No. Pin No. 2
40-Pin PDIP 40-Pin PDIP
Symbol Description 3
(Normal) (Reverse) 4
V+ Positive supply voltage. 5
1 (40) D1 Activates the D section of the units display. 6
2 (39) C1 Activates the C section of the units display. 7
3 (38) B1 Activates the B section of the units display. 8
4 (37) A1 Activates the A section of the units display.
5 (36) F1 Activates the F section of the units display.
6 (35) G1 Activates the G section of the units display.
7 (34) E1 Activates the E section of the units display.
8 (33) D2 Activates the D section of the tens display.
9 (32) C2 Activates the C section of the tens display.
10 (31) B2 Activates the B section of the tens display.
11 (30) A2 Activates the A section of the tens display.
12 (29) F2 Activates the F section of the tens display.
13 (28) E2 Activates the E section of the tens display.
14 (27) D3 Activates the D section of the hundreds display.
15 (26) B3 Activates the B section of the hundreds display.
16 (25) F3 Activates the F section of the hundreds display.
17 (24) E3 Activates the E section of the hundreds display.
18 (23) AB4 Activates both halves of the 1 in the thousands display.
19 (22) POL Activates the negative polarity display.
20 (21) BP LCD Backplane drive output (TC7106A).
21 (20) GND Digital ground (TC7107A).
G3 Activates the G section of the hundreds display.
22 (19) A3 Activates the A section of the hundreds display.
C3 Activates the C section of the hundreds display.
23 (18) G2 Activates the G section of the tens display.
V Negative power supply voltage.
24 (17) VINT Integrator output. Connection point for integration capacitor. See
INTEGRATING CAPACITOR section for more details
25 (16) VBUFF Integration resistor connection. Use a 47k resistor for a 200mV full-
scale range and a 470k resistor for 2V full-scale range.
26 (15) CAZ The size of the auto-zero capacitor influences system noise. Use a
0.47F capacitor for 200mV full scale, and a 0.047F capacitor for
27 (14) 2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more
details.
28 (13) The analog LOW input is connected to this pin.
The analog HIGH input signal is connected to this pin.
29 (12) This pin is primarily used to set the analog common-mode voltage
for battery operation or in systems where the input signal is
30 (11) V referenced to the power supply. It also acts as a reference voltage
IN source. See paragraph on ANALOG COMMON for more details.
See pin 34.
31 (10) V +
IN
32 (9) ANALOG
COMMON
33 (8) C
REF
TELCOM SEMICONDUCTOR, INC. 3-187
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN DESCRIPTION (Cont.)
Pin No. Pin No.
40-Pin PDIP 40-Pin PDIP
(Normal) (Reverse) Symbol Description
34 (7) C + A 0.1F capacitor is used in most applications. If a large common-
REF
mode voltage exists (for example, the V IN pin is not at analog
common), and a 200mV scale is used, a 1F capacitor is recom-
mended and will hold the roll-over error to 0.5 count.
35 (6) VR EF See pin 36.
36 (5) V + The analog input required to generate a full-scale output (1999
REF counts). Place 100mV between pins 35 and 36 for 199.9mV
full-scale. Place 1V between pins 35 and 36 for 2V full scale. See
paragraph on REFERENCE VOLTAGE.
37 (4) Test Lamp test. When pulled HIGH (to V+) all segments will be turned on
and the display should read 1888. It may also be used as a negative
supply for externally-generated decimal points. See paragraph under
TEST for additional information.
38 (3) OSC3 See pin 40.
OSC2
39 (2) OSC1 See pin 40.
40 (1) Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock
(3 readings per section), connect pin 40 to the junction of a 100k
resistor and a 100pF capacitor. The 100k resistor is tied to pin 39
and the 100pF capacitor is tied to pin 38.
GENERAL THEORY OF OPERATION where:
DUAL SLOPE CONVERSION PRINCIPLES
VR = Reference Voltage
(All Pin Designations Refer to the 40-Pin DIP) TSI = Signal Integration Time (Fixed)
TRI = Reference Voltage Integration Time (Variable)
The TC7106A and TC7107A are dual slope, integrating
analog-to-digital converters. An understanding of the dual For a constant VIN:
slope conversion technique will aid in following the detailed VIN = VR TRI
operation theory.
TSI
The conventional dual slope converter measurement
cycle has two distinct phases: C
Input Signal Integration ANALOG INTEGRATOR COMPARATOR
Reference Voltage Integration (Deintegration) INPUT
SIGNAL +
+
The input signal being converted is integrated for a fixed
time period (TSI). Time is measured by counting clock +/ SWITCH CLOCK
pulses. An opposite polarity constant reference voltage is DRIVER
REF
then integrated until the integrator output voltage returns to VOLTAGE PHASE CONTROL
CONTROL LOGIC
zero. The reference integration time is directly proportional
POLARITY CONTROL
to the input signal (TRI). (Figure 2A). COUNTER
In a simple dual slope converter a complete conversion
requires the integrator output to "ramp-up" and "ramp- INTEGRATOR DISPLAY
OUTPUT
down." VIN VFULL SCALE
VIN 1/2 VFULL SCALE
A simple mathematical equation relates the input signal,
reference voltage and integration time: FIXED VARIABLE
SIGNAL REFERENCE
1 TSI VRTRI INTEGRATE INTEGRATE
TIME
TIME
RC 0 VIN(t)dt = RC Figure 2A. Basic Dual Slope Converter
3-188 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
The dual slope converter accuracy is unrelated to the Signal Integrate Cycle
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is 2 When the auto-zero loop is opened, the internal differ-
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are ential inputs connect to VI+N and VIN. The differential input
immune to the large conversion errors that plague succes- signal is integrated for a fixed time period. The signal
sive approximation converters in high-noise environments. integration period is 1000 counts. The externally set clock
Interfering signals with frequency components at multiples frequency is divided by four before clocking the internal
of the averaging period will be attenuated. Integrating ADCs counters. The integration time period is:
commonly operate with the signal integration period set to a
multiple of the 50/60 Hz power line period. (Figure 2B) TSI = 4 x 1000
fOSC
30 3
where:
fOSC = External Clock Frequency
NORMAL MODE REJECTION (dB) 20 The differential input voltage must be within the device
common-mode range (1V of either supply) when the con-
10 verter and measured system share the same power supply
common (ground). If the converter and measured system do
T = MEASUREMENT PERIOD
4 not share the same power supply common, VIN should be
tied to analog common.
Polarity is determined at the end of the signal integrate
phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection, limited only by device noise and
auto-zero residual offsets.
0 1/T 10/T 5 Reference Integrate Cycle
0.1/T INPUT FREQUENCY The final phase is reference integrate or de-integrate.
VIN is internally connected to analog common and VI+N is
Figure 2B. Normal-Mode Rejection of Dual Slope Converter connected across the previously charged reference capaci-
ANALOG SECTION tor. Circuitry within the chip ensures that the capacitor will be
In addition to the basic signal integrate and deintegrate connected with the correct polarity to cause the integrator
cycles discussed, the circuit incorporates an auto-zero
cycle. This cycle removes buffer amplifier, integrator, and output to return to zero. The time required for the output to
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external return to zero is proportional to the input signal and is
potentiometers. A complete conversion consists of three
cycles: an auto-zero, signal-integrate and reference-inte- 6 between 0 and 2000 counts. The digital reading displayed is:
grate cycle. 1000 x VIN
VREF
Auto-Zero Cycle DIGITAL SECTION (TC7106A)
During the auto-zero cycle the differential input signal is The TC7106A (Figure 3) contains all the segment driv-
disconnected from the circuit by opening internal analog ers necessary to directly drive a 3 -1/2 digit liquid crystal
gates. The internal nodes are shorted to analog common
(ground) to establish a zero-input condition. Additional ana- 7 display (LCD). An LCD backplane driver is included. The
log gates close a feedback loop around the integrator and
comparator. This loop permits comparator offset voltage backplane frequency is the external clock frequency divided
error compensation. The voltage level established on CAZ by 800. For three conversions/second the backplane fre-
compensates for device offset voltages. The offset error quency is 60Hz with a 5V nominal amplitude. When a
referred to the input is less than 10V. segment driver is in phase with the backplane signal the
segment is "OFF." An out of phase segment drive signal
The auto-zero cycle length is 1000 to 3000 counts. causes the segment to be "ON" or visible. This AC drive
configuration results in negligible DC voltage across each
TELCOM SEMICONDUCTOR, INC.
8 LCD segment. This insures long LCD display life. The
polarity segment driver is "ON" for negative analog inputs. If
VI+N and VIN are reversed, this indicator will reverse.
3-189
3-190 TC7106
TC7106A
TC7107
TC7107A
TYPICAL SEGMENT OUTPUT
V+
0.5mA
SEGMENT LCD DISPLAY
OUTPUT
2mA
TC7106A INTERNAL DIGITAL GROUND
BACKPLANE
21
Figure 3. TC7106A Block Diagram CREF RINT CAZ CINT
C + VR+EF VREF C VBUFF V+ VINT LCD SEGMENT DRIVERS
REF REF
34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT 7 SEGMENT 7 SEGMENT 200
DECODE DECODE DECODE
TO
10 A/Z DIGITAL
+ SECTION
A/Z
A + + DATA LATCH
A/Z
+ 31
IN
V DE DE COMPARATOR THOUSANDS HUNDREDS TENS UNITS
() (+)
INT
A/Z LOW TO SWITCH DRIVERS
+ TEMPCO FROM COMPARATOR OUTPUT
V+ 3.0V VREF 1 V+
3-1/2 DIGIT A/D CONVERTERS
ANALOG 32 DE (+) DE () 26 CLOCK fOSC 6.2V
COMMON AZ & DE () V 4 37
TEST
30 CONTROL LOGIC
IN 500
V
26 V
TELCOM SEMICONDUCTOR, INC. INT INTERNAL DIGITAL GOUND
VTH
40 39 = 1V
OSC 1 OSC2
38
ROSC OSC 3
COSC
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
When the TEST pin on the TC7106A is pulled to V+, all Signal Integrate: 1000 Counts
segments are turned "ON." The display reads 1888. During
this mode the LCD segments have a constant DC voltage (4000 Clock Pulses) 2
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE This time period is fixed. The integration period is:
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended [ ] TSI = 4000 1
periods. fOSC
The display font and the segment drive assignment are Where fOSC is the externally set clock frequency.
shown in Figure 4.
Reference Integrate: 0 to 2000 Counts
DISPLAY FONT
(0 to 8000 Clock Pulses) 3
The TC7106A/7107A are drop-in replacements for the
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
1000's 100's 10's 1's Clock Circuit
Three clocking methods may be used:
1. An external oscillator connected to pin 40. 4
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
Figure 4. Display Font and Segment Assignment 4 TO
COUNTER
In the TC7106A, an internal digital ground is generated
from a 6 volt zener diode and a large P channel source 40 39 38 5
follower. This supply is made stiff to absorb the large
capacitive currents when the backplane voltage is switched. CRYSTAL
DIGITAL SECTION (TC7107A) EXT RC NETWORK TC7106A
OSC TC7107A
Figure 5 shows the TC7107A. It is designed to drive
common anode LEDs. It is identical to the TC7106A except TO TEST PIN ON TSC7106A
that the regulated supply and backplane drive have been TO GND PIN ON TSC7107A
eliminated and the segment drive is typically 8mA. The
1000's output (pin 19) sinks current from two LED segments, Figure 6. Clock Circuits
and has a 16mA drive capability.
COMPONENT VALUE SELECTION 6
In both devices, the polarity indication is "ON" for nega-
tive analog inputs. If VIN and VI+N are reversed, this indication Auto-Zero Capacitor CAZ
can be reversed also, if desired.
The CAZ capacitor size has some influence on system
The display font is the same as the TC7106A. noise. A 0.47F capacitor is recommended for 200mV full-
System Timing scale applications where 1 LSB is 100V. A 0.047F capaci-
The oscillator frequency is divided by 4 prior to clocking tor is adequate for 2.0V full-scale applications. A mylar
the internal decade counters. The three-phase measure-
ment cycle takes a total of 4000 counts or 16000 clock dielectric capacitor is adequate. 7
pulses. The 4000 count cycle is independent of input signal
magnitude. Reference Voltage Capacitor CREF
Each phase of the measurement cycle has the following The reference voltage used to ramp the integrator
length: output voltage back to zero during the reference-integrate
cycle is stored on CREF. A 0.1F capacitor is acceptable
Auto-Zero Phase: 1000 to 3000 Counts when VIN is tied to analog common. If a large common-mode
(4000 to 12000 Clock Pulses) voltage exists (VREF analog common) and the application
For signals less than full-scale, the auto-zero phase is 8 requires 200mV full-scale, increase CREF to 1.0 F. Rollover
assigned the unused reference integrate time period.
error will be held to less than 1/2 count. A mylar dielectric
TELCOM SEMICONDUCTOR, INC. capacitor is adequate.
3-191
3-192 TC7106
TC7106A
TC7107
TC7107A
TYPICAL SEGMENT OUTPUT
V+
0.5mA
SEGMENT LED DISPLAY
OUTPUT
8mA
TC7107A INTERNAL DIGITAL GROUND
Figure 5. TC7107A Block Diagram CREF RINT CAZ CINT
C + VR+EF VREF CREF VBUFF V+ VINT LCD SEGMENT DRIVERS
REF
34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT 7 SEGMENT 7 SEGMENT
TO DECODE DECODE DECODE
DIGITAL
10 A/Z SECTION
+
A A/Z DATA LATCH
+ +
A/Z
+ 31
IN
V DE DE COMPARATOR THOUSANDS HUNDREDS TENS UNITS
() (+)
INT
A/Z LOW TO SWITCH DRIVERS
+ TEMPCO FROM COMPARATOR OUTPUT
V+ 3.0V VREF 1 V+ 3-1/2 DIGIT A/D CONVERTERS
ANALOG 32 DE (+) DE () 26 CLOCK fOSC 21
COMMON AZ & DE () V 4 DIGITAL
GROUND
30 LOGIC CONTROL
IN
TELCOM SEMICONDUCTOR, INC. V
INT DIGITAL GOUND
500
40 39 38 37
OSC 1 OSC2 OSC 3 TEST
ROSC COSC
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
Integrating Capacitor CINT Oscillator Components
CINT should be selected to maximize the integrator 2 ROSC (Pin 40 to Pin 39) should be 100k. COSC is
output voltage swing without causing output saturation. Due
to the TC7106A/7107A superior temperature coefficient selected using the equation:
specification, analog common will normally supply the differ-
ential voltage reference. For this case a 2V full-scale 0.45
integrator output swing is satisfactory. For 3 readings/ fOSC = RC
second (fOSC = 48kHz) a 0.22F value is suggested. If a
different oscillator frequency is used, CINT must be changed For fOSC of 48kHz, COSC is 100pF nominally.
in inverse proportion to maintain the nominal 2 V integrator
swing. Note that fOSC is divided by four to generate the TC7106A
An exact expression for CINT is: 3 internal control clock. The backplane drive signal is derived
by dividing fOSC by 800.
To achieve maximum rejection of 60Hz noise pickup,
the signal-integrate period should be a multiple of 60Hz.
(4000) ( 1 ) ( VFS ) Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
fOSC RINT 48kHz, 40kHz, etc. should be selected. For 50 Hz rejection,
CINT = oscillator frequencies of 200kHz, 100kHz, 66 2/3kHz, 50kHz,
VINT 40kHz, etc. would be suitable. Note that 40kHz (2.5 read-
ings/second) will reject both 50Hz and 60Hz. 4
Where: Reference Voltage Selection
fOSC = Clock frequency at Pin 38 A full-scale reading (2000 counts) requires the input
VFS = Full-scale input voltage signal be twice the reference voltage.
RINT = Integrating resistor
VINT = Desired full-scale integrator output swing Required Full-Scale Voltage* VREF
200.0mV
CINT must have low dielectric absorption to minimize 2.000V 100.0mV 5
rollover error. A polypropylene capacitor is recommended. 1.000V
* VFS = 2 VREF
Integrating Resistor RINT
In some applications a scale factor other than unity may
The input buffer amplifier and integrator are designed
with class A output stages. The output stage idling current exist between a transducer output voltage and the required
is 100A. The integrator and buffer can supply 20A drive
currents with negligible linearity errors. RINT is chosen to digital reading. Assume, for example, a pressure transducer
remain in the output stage linear drive region but not so large
that printed circuit board leakage currents induce errors. For output is 400mV for 2000 lb/in2. Rather than dividing the
a 200mV full-scale, RINT is 47k. 2.0V full-scale requires
470k. 6 input voltage by two the reference voltage should be set to
200mV. This permits the transducer input to be used
directly.
The differential reference can also be used when a
Component Nominal Full-Scale Voltage digital zero reading is required when VIN is not equal to zero.
This is common in temperature measuring instrumentation.
Value 200.0mV 2.000V A compensating offset voltage can be applied between
CAZ 0.47F 0.047F
RINT 47k analog common and VIN. The transducer output is con-
CINT 0.22F 470k +
0.22F 7 nected IN
Note:1. fOSC = 48kHz (3 readings/sec) between V and analog common.
The internal voltage reference potential available at
analog common will normally be used to supply the convert-
er's reference. This potential is stable whenever the supply
potential is greater than approximately 7V. In applications
where an externally-generated reference voltage is desired,
refer to Figure 7.
8
TELCOM SEMICONDUCTOR, INC. 3-193
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
V+ V+ INPUT CI
V+ BUFFER RI
VR+EF
VR EF V+ + +
VIN
TC7106A 6.8V
TC7107A ZENER VCM
6.8k VI
(a) IZ
TC04 +
1.2V
TC7106A 20k REF INTEGRATOR
TC7107A
TI
VR+EF [ VI = RI CI VCM VIN [
Where: 4000
VR EF TI = INTEGRATION TIME = fOSC
COMMON CI = INTEGRATION CAPACITOR
RI = INTEGRATION RESISTOR
(b)
Figure 7. External Reference Figure 9. Common-Mode Voltage Reduces Available Integrator
Swing. (VCOM VIN)
DEVICE PIN FUNCTIONAL DESCRIPTION full-scale swing. The integrator output will swing within 0.3V
of V+ or V without increasing linearity errors.
Differential Signal Inputs
(V+IN (Pin 31), VIN (Pin 30)) Differential Reference
+ VREF
The TC7106A/7017A is designed with true differential (V REF (Pin 36), (Pin 35))
inputs and accepts input signals within the input stage
common mode voltage range (VCM). The typical range is V+ The reference voltage can be generated anywhere
1.0 to V +1 V. Common-mode voltages are removed from within the V+ to V power supply range.
the system when the TC7106A/TC7107A operates from a
battery or floating power source (isolated from measured To prevent rollover errors from being induced by large
system) and VIN is connected to analog common (VCOM): common-mode voltages, CREF should be large compared to
See Figure 8. stray node capacitance.
In systems where common-mode voltages exist, the The TC7106A/TC7107A circuits have a significantly
86dB common-mode rejection ratio minimizes error. Com- lower analog common temperature coefficient. This gives a
mon-mode voltages do, however, affect the integrator out- very stable voltage suitable for use as a reference. The
put level. Integrator output saturation must be prevented. A temperature coefficient of analog common is 20ppm/C
worst-case condition exists if a large positive VCM exists in typically.
conjunction with a full-scale negative differential signal. The
negative signal drives the integrator output positive along
with VCM (Figure 9). For such applications the integrator
output swing can be reduced below the recommended 2.0V
SEGMENT LCD DISPLAY
DRIVE
MEASURED VBUF CAZ VINT POL BP
SYSTEM V+IN OSC1
V+ V IN TC7106A OSC3
V GND OV SC2
ANALOG VRE F VR+ EF V+
V+ V GND COMMON
POWER
SOURCE +
9V
Figure 8. Common-Mode Voltage Removed in Battery Operation with VIN = Analog Common
3-194 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
Analog Common (Pin 32) Internal Voltage Reference Stability
The analog common pin is set at a voltage potential 2 The analog common voltage temperature stability has
approximately 3.0V below V+. The potential is guaranteed
to be between 2.7V and 3.35 V below V+. Analog common been significantly improved (Figure 10). The "A" version of
is tied internally to the N channel FET capable of sinking the industry standard circuits allow users to upgrade old
20mA. This FET will hold the common line at 3.0V should an systems and design new systems without external voltage
external load attempt to pull the common line toward V+. references. External R and C values do not need to be
Analog common source current is limited to 10A. Analog changed. Figure 11 shows analog common supplying the
common is therefore easily pulled to a more negative necessary voltage reference for the TC7106A/TC7107A.
voltage (i.e., below V+ 3.0V).
3
The TC7106A connects the internal VI+N and VIN inputs
to analog common during the auto-zero cycle. During the 200
reference-integrate phase, VIN is connected to analog com-
mon. If VIN is not externally connected to analog common, TEMPERATURE COEFFICIENT (ppm/C) 180 NO
a common-mode voltage exists. This is rejected by the
converter's 86dB common-mode rejection ratio. In battery MAXIMUM NO MAXIMUM
operation, analog common and VIN are usually connected, SPECIFIED
removing common-mode voltage concerns. In systems where 160 SPECIFIED
VIN is connected to the power supply ground or to a given TYPICAL
voltage, analog common should be connected to VIN. 140
The analog common pin serves to set the analog section 120 4
reference or common point. The TC7106A is specifically 5
designed to operate from a battery or in any measurement 100 NO MAXIMUM
system where input signals are not referenced (float) with
respect to the TC7106A power source. The analog common 80 MAXIMUM SPECIFIED
potential of V+ 3.0V gives a 6 V end of battery life voltage.
The common potential has a 0.001%/% voltage coefficient LIMIT TYPICAL
and a 15 output impedance.
60
With sufficiently high total supply voltage (V+ V
> 7.0V) analog common is a very stable potential with TYPICAL
excellent temperature stability--typically 20ppm/C. This 40
potential can be used to generate the reference voltage. An
external voltage reference will be unnecessary in most 20 TC
cases because of the 50ppm/C maximum temperature
coefficient. See Internal Voltage Reference discussion. 7106A ICL7106 ICL7136
Test (Pin 37) 0
The TEST pin potential is 5V less than V+. TEST may be Figure 10. Analog Common Temperature Coefficient
used as the negative power supply connection for external
CMOS logic. The TEST pin is tied to the internally generated 1 6
negative logic supply (Internal Logic Ground) through a 7
500 resistor in the TC7106A. The TEST pin load should be V V+ 24k 8
no more than 1mA . 1k
TC7106A
If TEST is pulled to V+ all segments plus the minus sign TC7107A
will be activated. Do not operate in this mode for more than
several minutes with the TC7106A. With TEST = V+ the LCD VR+EF 36
segments are impressed with a DC voltage which will
destroy the LCD. VR EF VREF
35
The TEST pin will sink about 10mA when pulled to V+. ANALOG
COMMON 32
SET VREF = 1/2 VFULL SCALE
Figure 11. Internal Voltage Reference Connection
TELCOM SEMICONDUCTOR, INC. 3-195
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
POWER SUPPLIES TC7107 Power Dissipation Reduction
The TC7107A is designed to work from 5V supplies. The TC7107A sinks the LED display current and this
However, if a negative supply is not available, it can be causes heat to build up in the IC package. If the internal
generated from the clock output with two diodes, two capaci- voltage reference is used, the changing chip temperature
tors, and an inexpensive IC. (Figure 12) can cause the display to change reading. By reducing the
LED common anode voltage the TC7107A package power
In selected applications a negative supply is not re- dissipation is reduced.
quired. The conditions to use a single +5V supply are:
The input signal can be referenced to the center of the Figure 14 is a photograph of a curve-tracer display
showing the relationship between output current and output
common-mode range of the converter. voltage for a typical TC7107CPL. Since a typical LED has
The signal is less than 1.5V. 1.8 volts across it at 7mA, and its common anode is con-
An external reference is used. nected to +5V, the TC7107A output is at 3.2V (point A on
Figure 13). Maximum power dissipation is 8.1mA x 3.2V x
The TSC7660 DC to DC converter may be used to 24 segments = 622mW.
generate 5 V from +5 V (Figure 13).
Notice, however, that once the TC7107A output voltage
V+ is above two volts, the LED current is essentially constant as
CD4009 output voltage increases. Reducing the output voltage by
0.7V (point B in Figure 14) results in 7.7mA of LED current,
V+ 0.047 1N914 only a 5 percent reduction. Maximum power dissipation is
F 10 + only 7.7mA x 2.5 V x 24 = 462mW, a reduction of 26%. An
OSC1 F output voltage reduction of 1 volt (point C) reduces LED
OSC2 current by 10% (7.3mA) but power dissipation by 38%!
OSC3 1N914 (7.3mA x 2.2V x 24 = 385mW).
TC7107A
GND
V
V = 3.3V
Figure 12. Generating Negative Supply From +5 V
+5 V
LED 1 Figure 14. TC7107A Output Current vs Output Voltage
DRIVE V+ VR+EF 36
Reduced power dissipation is very easy to obtain.
VR EF 35 Figure 15 shows two ways: either a 5.1 ohm, 1/4 watt resistor
32 or a 1 Amp diode placed in series with the display (but not in
series with the TC7107A). The resistor will reduce the
COM TC7107A output voltage, when all 24 segments are "ON," to
point "C" of Figure 14. When segments turn off, the output
TC7107A VI+N 31 voltage will increase. The diode, on the other hand, will result
in a relatively steady output voltage, around point "B."
VIN
VIN 30 In addition to limiting maximum power dissipation, the
resistor reduces the change in power dissipation as the
+ 8 V GND 21 display changes. This effect is caused by the fact that, as
10F 26
2 TELCOM SEMICONDUCTOR, INC.
5 (5 V)
4 TC7660
3 *3-1/2 DIGIT ADC
+ 10F
Figure 13. Negative Power Supply Generation with TC7660
3-196
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
fewer segments are "ON," each "ON" output drops more APPLICATIONS INFORMATION
voltage and current. For the best case of six segments (a
"111" display) to worst case (a "1888" display) the resistor Liquid Crystal Display Sources 2
will change about 230mW, while a circuit without the resistor
will change about 470mW. Therefore, the resistor will re- Several LCD manufacturers supply standard LCD dis-
duce the effect of display dissipation on reference voltage plays to interface with the TC7106A 3-1/2 digit analog-to-
drift by about 50%. digital converter.
The change in LED brightness caused by the resistor is Manufacturer Address/Phone Part Numbers1 3
almost unnoticeable as more segments turn off. If display
brightness remaining steady is very important to the de- Crystaloid 5282 Hudson Dr. C5335, H5535,
signer, a diode may be used instead of the resistor. Electronics Hudson, OH 44236
216/655-2429
T5135, SX440
Figure 15. Diode or Resistor Limits Package Power Dissipation AND 720 Palomar Ave. FE 0201,0701
Sunnyvale, CA 94086 FE 0203, 2201
APPLICATIONS INFORMATION 408/523-8200 FE 0501
+5V IN 5V Epson 3415 Kashikawa St. LD-B709BZ
Hamlin, Inc. Torrance, CA 90505
+ 213/534-0360 LD-H7992AZ
24k 1 M 150 612 E. Lake St. 4
Lake Mills, WI 53551
TP3 414/648-2361 3902, 3933, 3903
1k 0.47
100 0.01 F 0.22 Note: 1. Contact LCD manufacturer for full product listing/specifications.
pF F F
TP5
TP2 0.1 DISPLAY
100
k TP1 F 47 Light Emitting Diode Display Sources
k
5 Several LED manufacturers supply seven segment
40 30 TP 21
digits with and without decimal point annunciators for the
4 TC7107A.
TC7107A
1 10 20
Manufacturer Address Display Type
DISPLAY Hewlett-Packard 640 Page Mill Rd. LED
5.1 1/4W Components Palo Alto, CA 94304
1N4001
AND 720 Palomar Ave. LED
6
Sunnyvale, CA 94086
7
TELCOM SEMICONDUCTOR, INC. 8
3-197
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
Decimal Point and Annunciator Drive Ratiometric Resistance Measurements
The TEST pin is connected to the internally-generated The true differential input and differential reference
digital logic supply ground through a 500 resistor. The make ratiometric reading possible. Typically in a ratiometric
TEST pin may be used as the negative supply for external operation, an unknown resistance is measured with respect
CMOS gate segment drivers. LCD display annunciators for to a known standard resistance. No accurately defined
decimal points, low battery indication, or function indication reference voltage is needed.
may be added without adding an additional supply. No more
than 1mA should be supplied by the TEST pin: its potential The unknown resistance is put in series with a known
is approximately 5V below V+. standard and a current passed through the pair. The voltage
developed across the unknown is applied to the input and
V+ V+ the voltage across the known resistor is applied to the
4049 reference input. If the unknown equals the standard, the
TC7106A display will read 1000. The displayed reading can be deter-
mined from the following expression:
BP 21
TEST 37 Displayed Reading = R Unknown x 1000
TO LCD R Standard
DECIMAL
GND POINT The display will overrange for R Unknown 2 x R
standard.
TO LCD
BACK- VR+EF V+
PLANE VREF
V+ RSTANDARD VI+N LCD DISPLAY
RUNKNOWN TC7106A
V+ BP TO LCD
DECIMAL VIN
TC7106A DECIMAL POINTS ANALOG
POINT COMMON
SELECT
Figure 17. Low Parts Count Ratiometric Resistance
Measurement
TEST 4030
GND
Figure 16. Decimal Point Drive Using TEST as Logic Ground
3-198 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
+ 9V
IN4148 + 26 2
200mV 1F 3
VIN 4
9M 1 14 1 V+ V 27
900k 10k
90k 2V 0.02 1M 2 13 24k
F 3 12 TC7106A 29
20 V 1M 1k 36 V+REF
200 V
47k 4 AD636 11
1W
35 VREF 28
10%
6.8F + 5 10
6 9 32 ANALOG
10k 1M 10% 31 COMMON 40
7 V+IN
8
20kW 2.2F 0.01
10%
F 30 VIN 38
COM
C1 = 310pF VARIABLE, 26 V 39
C2 = 132pF VARIABLE
SEG BP
DRIVE
LCD DISPLAY
Figure 18. 3 1/2 Digit True RMS AC DMM
+ 9V + 9V 5
6
160k 300k 300k 5.6k 160k
1N4148 R1 V+ V V+ V
SENSOR 50k
VIN 1N914 R1 VIN
R2 20k
50k VI+N TC7106A
VI+N TC7106A
VFS = 2V
VR+ EF 0.7%/C R3 R2 VR+ EF
PTC 20k
VR EF VR EF
COMMON COMMON
Figure 19. Temperature Sensor Figure 20. Positive Temperature Coefficient Resistor 7
Temperature Sensor
TELCOM SEMICONDUCTOR, INC. 8
3-199
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
9V
2 CONSTANT 5 V 1
V+
V+ V+REF
REF02 6 51k 5.1k TC911 50k TC7106A
R4 R5 R2
VOUT 2 VREF
NC 3+ VFS = 2.00V
5 8
ADJ 1.3k 1 VIN
V+IN
3 4 VOUT =
TEMP COMMON
1.86V @ V
26
TEMPERATURE 25C 50k
DEPENDENT
OUTPUT R1
GND
4
Figure 21. Integrated Circuit Temperature Sensor
TO PIN 1 TO PIN 1
40 SET VREF = 100mV 40 SET VREF = 100mV
100k 39 100k
39 38
37
38 36
35
37 100pF 34 100pF
33
36 32
31
35 +5V
TC7107A 30 +
34 0.1F 1 k 22k 0.1F 1k 22k
0.47F 1M 29 0.47F IN
33 0.22F + 28 0.22F 1M
IN 27
32 26 5V
25
TC7106A 31 0.01F 9V 24 0.01F
30 23
+ 22
29 47k 21 47k
28
27
26
25
24 TO DISPLAY TO DISPLAY
TO BACKPLANE
23
22
21
Figure 22. TC7106A Using the Internal Reference: 200mV Full- Figure 23. TC7107A Internal Reference (200mV Full-Scale,
Scale, 3 Readings-per-second (RPS). 3RPS, VIN Tied to GND for Single Ended Inputs).
3-200 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS 1 TC7106
TC7106A
TC7107
TC7107A
V+ 1 40 TO PIN 1 2
3
TO 40 SET VREF = 1V 4
LOGIC 100k
39
VCC
TO 38
LOGIC
GND 37 100pF
36 24k V+
+
35
IN
TC7106A 34 0.1F 25k
33 1M V
32
V TC7106A 31 0.01F
30 470k
O/R TC7107A 29 0.047F
U/R 28
CD4023 27 0.22F
OR 74C10
26
20 21 25
24 TO DISPLAY
23
CD4077 O/R = OVERRANGE 22
U/R = UNDERRANGE
21
Figure 24. Circuit for Developing Underrange and Overrange Figure 25. TC7106A/TC7107A: Recommended Component
Signals from TC7106A Outputs. Values for 2.00V Full-Scale
TO PIN 1 TO PIN 1 5
6
40 100k SET VREF= 100mV 40 100k SET VREF= 100mV 7
39 39
38 100pF 38 100pF
37 37
36 10k 10k V+ 36 10k 10k
35 35 V+
34 0.1F 1k TC04 34 0.1F 1 k
33 0.47F 1.2V + 33 0.47F TC04
32 32 1.2V +
0.01F
31 1M IN TC7107A 31 0.01F 1M IN
47k
TC7107A 30 30
29
29 28 47k
28 27
27 0.22F V 26 0.22F
26 25
25 TO DISPLAY 24 TO DISPLAY
24 23
23 22
22 21
21
Figure 26. TC7107A With a 1.2V External Band-Gap Reference. Figure 27. TC7107A Operated from Single +5V Supply. An
(VIN Tied to Common.) External Reference Must Be Used in This Application.
TELCOM SEMICONDUCTOR, INC. 8
3-201
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