STM8L052R8
Value Line, 8-bit ultralow power MCU, 64-KB Flash,
256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
Datasheet - production data
Features
• Operating conditions
– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C
• Low power features
– 5 low power modes: Wait, Low power run LQFP64
(5.9 µA), Low power wait (3 µA), Active-halt
with full RTC (1.4 µA), Halt (400 nA) • DMA
– Dynamic power consumption: – 4 channels supporting ADC, SPIs, I2C,
200 µA/MHz + 330 µA USARTs, timers
– Ultra-low leakage per I/0: 50 nA – 1 channel for memory-to-memory
– Fast wakeup from Halt: 4.7 µs • 12-bit ADC up to 1 Msps/27 channels
• Advanced STM8 core – Internal reference voltage
– Harvard architecture and 3-stage pipeline • Timers
– Max freq. 16 MHz, 16 CISC MIPS peak – Three 16-bit timers with 2 channels (used
– Up to 40 external interrupt sources as IC, OC, PWM), quadrature encoder
• Reset and supply management – One 16-bit advanced control timer with 3
– Low power, ultra-safe BOR reset with 5 channels, supporting motor control
programmable thresholds – One 8-bit timer with 7-bit prescaler
– Ultra low power POR/PDR – 2 watchdogs: 1 Window, 1 Independent
– Programmable voltage detector (PVD) – Beeper timer with 1, 2 or 4 kHz frequencies
• Clock management • Communication interfaces
– 32 kHz and 1 to 16 MHz crystal oscillators – Two synchronous serial interfaces (SPI)
– Internal 16 MHz factory-trimmed RC – Fast I2C 400 kHz SMBus and PMBus
– 38 kHz low consumption RC – Three USARTs (ISO 7816 interface + IrDA)
– Clock security system • Up to 54 I/Os, all mappable on interrupt vectors
• Low power RTC • Development support
– BCD calendar with alarm interrupt – Fast on-chip programming and non-
– Digital calibration with +/- 0.5ppm accuracy intrusive debugging with SWIM
– Advanced anti-tamper detection – Bootloader using USART
• LCD: 8x24 or 4x28 w/ step-up converter
• Memories
– 64 KB Flash program memory and 256
bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 4 KB of RAM
February 2017 Doc ID023337 Rev 3 1/112
This is information on a product in full production. www.st.com
Contents STM8L052R8
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Central processing unit STM8 ................................. 14
3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Reset and supply management ................................ 15
3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Low power real-time clock .................................... 17
3.6 LCD (Liquid crystal display) ................................... 18
3.7 Memories ................................................. 18
3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Analog-to-digital converter .................................... 19
3.10 System configuration controller and routing interface ............... 19
3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Beeper ................................................... 21
3.14 Communication interfaces .................................... 21
3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/112 Doc ID023337 Rev 3
STM8L052R8 Contents
3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Memory mapping ........................................... 31
5.2 Register map .............................................. 32
6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . 60
8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.4 Thermal characteristics ..................................... 106
Doc ID023337 Rev 3 3/112
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Contents STM8L052R8
9 Package characteristics . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . 107
9.1 Package mechanical data ........ . . . . . . . ..... . . . . . . . . . . . . . . . 107
10 Ordering information scheme ...... . . . . . . . .... . . . . . . . . . . . . . . 110
11 Revision history ................. . . . . . . . .... . . . . . . . . . . . . . . 111
4/112 Doc ID023337 Rev 3
STM8L052R8 List of tables
List of tables
Table 1. High density value line STM8L05xxx low power device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. High density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to
3.6 V ............................................................... . . 68
Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 70
Table 21. Total current consumption and timing in Active-halt mode
at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 72
Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 74
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 87
Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Doc ID023337 Rev 3 5/112
6
List of tables STM8L052R8
Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 53. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 108
Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6/112 Doc ID023337 Rev 3
STM8L052R8 List of figures
List of figures
Figure 1. High density value line STM8L05xxx device block diagram .......... . . .... .. . . . . 12
Figure 2. High density value line STM8L05xxx clock tree diagram ............. . . .... .. . . . . 17
Figure 3. STM8L052R8 64-pin LQFP64 package pinout ..................... . . .... .. . . . . 23
Figure 4. Memory map ............................................... . . .... .. . . . . 31
Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 56
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 57
Figure 7. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 62
RFRFlAlAaaMsMshhvv(vsHss..S.VVVIDDcDDDlDo((cH(HHkSSSsIIoIccuclloroloccceckkk),sssofoCouuPurrUcrccee=e)),),1,ff6CfCCPPMPUUUH===z111166)6.MMM.HH.Hz.zz.111.)))...
Figure 8. Typical IDD(RUN) from . . .... .. . . . . 65
Figure 9. Typical IDD(RUN) from . . .... .. . . . . 65
Figure 10. Typical IDD(Wait) from . . .... .. . . . . 67
Figure 11. Typical IDD(Wait) from . . .... .. . . . . 67
Figure 12. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . .... .. . . . . 69
source), all peripherals OFF (1)
Figure 13. Typical IDD(LPW) vs. VDD (LSI clock . . . . . . . .... .. . . . . 70
Figure 14. Typical IDD(AH) vs. VDD (LSI clock source) ....................... . . .... .. . . . . 73
Figure 15. Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . .... .. . . . . 74
Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 78
Figure 17. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 79
Figure 18. Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 80
Figure 19. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 81
Figure 20. Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 85
Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . .... .. . . . . 85
Figure 22. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . .... .. . . . . 86
Figure 23. Typical pull-up current Ipu vs. VDD with VIN=VSS ................... . . .... .. . . . . 86
Figure 24. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 25. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 26. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 27. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 28. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 29. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 30. Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 89
Figure 31. Typical NRST pull-up current Ipu vs. VDD ......................... . . .... .. . . . . 90
Figure 32. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 91
Figure 33. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 93
SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . .
Figure 34. SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 93
Figure 35. . . .... .. . . . . 94
Figure 36. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . .... .. . . . . 96
Figure 37. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 102
Figure 38. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 102
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . .... .. . . . 103
Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . .... .. . . . 103
Figure 41. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . .... .. . . . 108
Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 109
Figure 43. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 110
Doc ID023337 Rev 3 7/112
7
Introduction STM8L052R8
1 Introduction
This document describes the features, pinout, mechanical data and ordering information of
the high density value line STM8L052R8 microcontroller with a Flash memory density of
64 Kbytes.
For further details on the whole STMicroelectronics high density family please refer to
Section 2.2: Ultra low power continuum.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
High density value line devices provide the following benefits:
• Integrated system
– 64 Kbytes of high density embedded Flash program memory
– 256 bytes of data EEPROM
– 4 Kbytes of RAM
– Internal high speed and low-power low speed RC
– Embedded reset
• Ultra low power consumption
– 1 µA in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low power wait mode and low power run
mode
• Advanced features
– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access
• Short development cycles
– Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
– Wide choice of development tools
These features make the value line STM8L05xxx ultra low power microcontroller family
suitable for a wide range of consumer and mass market applications.
Refer to Table 1: High density value line STM8L05xxx low power device features and
peripheral counts and Section 3: Functional overview for an overview of the complete range
of peripherals proposed in this family.
Figure 1 shows the block diagram of the high density value line STM8L05xxx family.
8/112 Doc ID023337 Rev 3
STM8L052R8 Description
2 Description
The high density value line STM8L05xxx devices are members of the STM8L ultra low
power 8-bit family.
The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.
High density value line STM8L05xxx microcontrollers feature embedded data EEPROM and
low-power, low-voltage, single-supply program Flash memory.
All devices offer 12-bit ADC, real-time clock, four 16-bit timers, one 8-bit timer as well as
standard communication interface such as two SPIs, I2C, three USARTs and 8x24 or 4x28-
segment LCD. The 8x24 or 4x 28-segment LCD is available on the high density value line
STM8L05xxx.
The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C
temperature range.
The modular design of the peripheral set allows the same peripherals to be found in
different ST microcontroller families including 32-bit families. This makes any transition to a
different family very easy, and simplified even more by the use of a common set of
development tools.
All value line STM8L ultra low power products are based on the same architecture with the
same memory mapping and a coherent pinout.
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52
Description STM8L052R8
2.1 Device overview
Table 1. High density value line STM8L05xxx low power device features and
peripheral counts
Features STM8L052R8
Flash (Kbytes) 64
Data EEPROM (bytes) 256
RAM (Kbytes) 4
LCD 8x24 or 4x28
Basic 1
(8-bit)
Timers General purpose 3
(16-bit)
Advanced control 1
(16-bit)
SPI 2
Communication I2C 1
interfaces
USART 3
GPIOs 54(1)
12-bit synchronized ADC 1
(number of channels) (26)
RTC, window watchdog, independent watchdog,
Others 16-MHz and 38-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency 16 MHz
Operating voltage 1.8 V to 3.6 V
Operating temperature -40 to +85 °C
Package LQFP64
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
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STM8L052R8 Description
2.2 Ultra low power continuum
The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra low power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.
2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:
• Analog peripheral: ADC1
• Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:
• Same power supply range from 1.8 to 3.6 V
• Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
• Fast startup strategy from low power modes
• Flexible system clock
• Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on
reset, power-down reset, brownout reset and programmable voltage detector
Features
ST ultra low power continuum also lies in feature compatibility:
• More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
• Memory density ranging from 4 to 128 Kbytes
Doc ID023337 Rev 3 11/112
52
Functional overview STM8L052R8
3 Functional overview
Figure 1. High density value line STM8L05xxx device block diagram
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1. Legend:
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
I²C: Inter-integrated circuit multimaster interface
LCD: Liquid crystal display
POR/PDR: Power on reset / power down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
IWDG: independent watchdog
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STM8L052R8 Functional overview
3.1 Low power modes
The high density value line STM8L05xxx devices support five low power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
• Wait mode: The CPU clock is stopped, but selected peripherals keep running. An
internal or external interrupt, event or a Reset can be used to exit the microcontroller
from Wait mode (WFE or WFI mode).
• Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra low power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
• Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1) and I/O ports). When the wakeup is triggered by an event, the
system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
• Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
• Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The wakeup is triggered by an external interrupt or reset. A few peripherals have also a
wakeup from Halt capability. Switching off the internal reference voltage reduces power
consumption. Through software configuration it is also possible to wake up the device
without waiting for the internal reference voltage wakeup time to have a fast wakeup
time of 5 µs.
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Functional overview STM8L052R8
3.2 Central processing unit STM8
3.2.1 Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching most instructions
• X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64-Kbyte level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for lookup tables located anywhere in the address
space
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
3.2.2 Interrupt controller
The high density value line STM8L05xxx devices feature a nested vectored interrupt
controller:
• Nested interrupts with 3 software priority levels
• 32 interrupt vectors with hardware priority
• Up to 40 external interrupt sources on 11 vectors
• Trap and reset interrupts
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STM8L052R8 Functional overview
3.3 Reset and supply management
3.3.1 Power supply scheme
The device requires a 1.8 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
• VSS1, VDD1, VSS2, VDD2, VSS3, VDD3 = 1.8 to 3.6 V: external power supply for I/Os and
for the internal regulator. Provided externally through VDD pins, the corresponding
ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3 must not be left
unconnected.
• VSSA ; VDDA = 1.8 to 3.6 V: external power supplies for analog peripherals. VDDA and
VSSA must be connected to VDD and VSS, respectively.
• VREF+ ; VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry that ensures proper operation starting
from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,
either to confirm or modify default thresholds, or to disable BOR permanently.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains
under reset when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need
for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The high density value line STM8L05xxx embeds an internal voltage regulator for
generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
• Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes
• Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and
Low power wait modes
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
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Functional overview STM8L052R8
3.4 Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
• Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock sources: 4 different clock sources can be used to drive the system
clock:
– 1-16 MHz High speed external crystal (HSE)
– 16 MHz High speed internal RC oscillator (HSI)
– 32.768 kHz Low speed external crystal (LSE)
– 38 kHz Low speed internal RC (LSI)
• RTC and LCD clock sources: The above four sources can be chosen to clock the
RTC and the LCD, whatever the system clock.
• Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If a HSE
clock failure occurs, the system clock is automatically switched to HSI.
• Configurable main clock output (CCO): This outputs an external clock for use by the
application.
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STM8L052R8 Functional overview
Figure 2. High density value line STM8L05xxx clock tree diagram
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1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE
bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE
bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031).
3.5 Low power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically.The subsecond field can also be read in binary format.
The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a
synchronization to a master clock.
The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
• Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours.
• Periodic alarms based on the calendar can also be generated from every second to
every year.
A clock security system detects a failure on LSE, and can provide an interrupt with wakeup
capability. The RTC clock can automatically switch to LSI in case of LSE failure.
The RTC also provides 3 anti-tamper detection pins. This detection embeds a
programmable filter and can wakeup the MCU.
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Functional overview STM8L052R8
3.6 LCD (Liquid crystal display)
The LCD is only available on STM8L052xx devices.
The liquid crystal display drives up to 8 common terminals and up to 24 segment terminals
to drive up to 192 pixels. It can also be configured to drive up to 4 common and 28
segments (up to 112 pixels).
• Internal step-up converter to guarantee contrast control whatever VDD.
• Static 1/2, 1/3, 1/4, 1/8 duty supported.
• Static 1/2, 1/3, 1/4 bias supported.
• Phase inversion to reduce power consumption and EMI.
• Up to 8 pixels which can be programmed to blink.
• The LCD controller can operate in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.
3.7 Memories
The high density value line STM8L05xxx devices have the following main features:
• 4 Kbytes of RAM
• The non-volatile memory is divided into three arrays:
– 64 Kbytes of high density embedded Flash program memory
– 256 bytes of data EEPROM
– Option bytes
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, SPI 2, USART1, USART2, USART3
and the five timers.
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STM8L052R8 Functional overview
3.9 Analog-to-digital converter
• 12-bit analog-to-digital converter (ADC1) with 27 channels (including 4 fast channels)
and internal reference voltage
• Conversion time down to 1 µs with fSYSCLK= 16 MHz
• Programmable resolution
• Programmable sampling time
• Single and continuous mode of conversion
• Scan capability: automatic conversion performed on a selected group of analog inputs
• Analog watchdog: interrupt generation when the converted voltage is outside the
programmed threshold
• Triggered by timer
Note: ADC1 can be served by DMA1.
3.10 System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1 and the internal reference voltage VREFINT.
3.11 Timers
The high density value line STM8L05xxx devices contain one advanced control timer
(TIM1), three 16-bit general purpose timers (TIM2, TIM3 and TIM5) and one 8-bit basic
timer (TIM4).
All the timers can be served by DMA1.
Table 2 compares the features of the advanced control, general-purpose and basic timers.
Table 2. Timer feature comparison
Counter Counter DMA1 Capture/compare Complementary
Timer resolution type Prescaler factor request channels outputs
generation
TIM1 Any integer 3+1 3
from 1 to 65536
TIM2 16-bit up/down
TIM3 Any power of 2 Yes 2
from 1 to 128 None
TIM5
TIM4 8-bit up Any power of 2 0
from 1 to 32768
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Functional overview STM8L052R8
3.11.1 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
• 16-bit up, down and up/down autoreload counter with 16-bit prescaler
• 3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
• 1 additional capture/compare channel which is not connected to an external I/O
• Synchronization module to control the timer with external signals
• Break input to force timer outputs into a defined state
• 3 complementary outputs with adjustable dead time
• Encoder mode
• Interrupt capability on various events (capture, compare, overflow, break, trigger)
3.11.2 16-bit general purpose timers
• 16-bit autoreload (AR) up/down-counter
• 7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
• 2 individually configurable capture/compare channels
• PWM mode
• Interrupt capability on various events (capture, compare, overflow, break, trigger)
• Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
3.11.3 8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer
overflow.
3.12 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.12.1 Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.12.2 Independent watchdog timer
The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.
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STM8L052R8 Functional overview
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.13 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
3.14 Communication interfaces
3.14.1 SPI
The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial
communication with external devices.
• Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave
• Full duplex synchronous transfers
• Simplex synchronous transfers on 2 lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• Hardware CRC calculation
• Slave/master selection input pin
Note: SPI1 and SPI2 can be served by the DMA1 Controller.
3.14.2 I²C
The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-
specific sequencing, protocol, arbitration and timing.
• Master, slave and multi-master capability
• Standard mode up to 100 kHz and fast speed modes up to 400 kHz
• 7-bit and 10-bit addressing modes
• SMBus 2.0 and PMBus support
• Hardware CRC calculation
Note: I2C1 can be served by the DMA1 Controller.
3.14.3 USART
The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous
communications with external devices requiring an industry standard NRZ asynchronous
serial data format. It offers a very wide range of baud rates.
• 1 Mbit/s full duplex SCI
• SPI1 emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• Single wire half duplex mode
Note: USART1, USART2 and USART3 can be served by the DMA1 Controller.
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Functional overview STM8L052R8
3.15 Infrared (IR) interface
The high density value line STM8L05xxx devices contain an infrared interface which can be
used with an IR LED for remote control functions. Two timer output compare channels are
used to generate the infrared remote control signals.
3.16 Development support
Development tools
Development tools for the STM8 microcontrollers include:
• The STice emulation system offering tracing and code profiling
• The STVD high-level language debugger including C compiler, assembler and
integrated development environment
• The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real-
time by means of shadow registers.
Bootloader
A bootloader is available to reprogram the Flash memory using the USART1, USART2,
USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces. The reference
document for the bootloader is UM0560: STM8 bootloader user manual.
The bootloader is used to download application software into the device memories,
including RAM, program and data memory, using standard serial interfaces. It is a
complementary solution to programming via the SWIM debugging interface.
22/112 Doc ID023337 Rev 3
STM8L052R8 Pin description
4 Pin description
Figure 3. STM8L052R8 64-pin LQFP64 package pinout
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Doc ID023337 Rev 3 23/112
52
Pin description STM8L052R8
Table 3. Legend/abbreviation for Table 4
Type I= input, O = output, S = power supply
FT Five-volt tolerant
Level TT 3.6 V tolerant
Output HS = high sink/source (20 mA)
Port and control Input float = floating, wpu = weak pull-up
configuration Output T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Reset state Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Table 4. High density value line STM8L05xxx pin description
Pin Input Output
number
LQFP64 Pin name Type I/O level floating Ext. interrupt High sink/source Main function (after reset) Default alternate function
wpu OD PP
2 NRST/PA1(1) I/O - - X - HS X X Reset PA1
PA2/OSC_IN/ HSE oscillator input /
[USART1_TX](8)/
3 [SPI1_MISO] (8) I/O - X X X HS X X Port A2 [USART1 transmit] / [SPI1
master in- slave out]
PA3/OSC_OUT/[USART1_ HSE oscillator output /
4 RX](8)/[SPI1_MOSI](8) I/O - X X X HS X X Port A3 [USART1 receive]/ [SPI1
master out/slave in]/
PA4/TIM2_BKIN/ Timer 2 - break input
[TIM2_ETR](8)/ FT(2)
5 I/O X X X HS X X Port A4 /[Timer 2 - trigger]/
LCD_COM0/ADC1_IN2 LCD COM 0 / ADC1 input 2
PA5/TIM3_BKIN/ Timer 3 - break input
6 [TIM3_ETR](8)/ I/O FT(2) X X X HS X X Port A5 /[Timer 3 - trigger]/
LCD_COM1/ADC1_IN1 LCD_COM 1 / ADC1 input
1
PA6/[ADC1_TRIG]/ FT(2) [ADC1 - trigger] /
7 LCD_COM2/ADC1_IN0 I/O X X X HS X X Port A6 LCD_COM2 /
ADC1 input 0
8 PA7/LCD_SEG0(2) I/O FT(2) X X X HS X X Port A7 LCD segment 0/ TIM5
/TIM5_CH1 channel 1
31 PB0(3)/TIM2_CH1/ I/O FT(2) X X X HS X X Port B0 Timer 2 - channel 1 / LCD
LCD_SEG10/ADC1_IN18 segment 10 / ADC1_IN18
24/112 Doc ID023337 Rev 3
STM8L052R8 Pin description
Table 4. High density value line STM8L05xxx pin description (continued)
Pin Input Output
number
LQFP64 Pin name Type I/O level floating Ext. interrupt High sink/source Main function (after reset) Default alternate function
wpu OD PP
PB1/TIM3_CH1/ FT(2) Timer 3 - channel 1 / LCD
32 LCD_SEG11/ I/O X X X HS X X Port B1 segment 11 / ADC1_IN17
ADC1_IN17
PB2/ TIM2_CH2/ FT(2) Timer 2 - channel 2 / LCD
33 LCD_SEG12/ I/O X X X HS X X Port B2 segment 12 / ADC1_IN16
ADC1_IN16
PB3/TIM2_ETR/ FT(2) Timer 2 - trigger / LCD
34 LCD_SEG13/ I/O X X X HS X X Port B3 segment 13 /ADC1_IN15
ADC1_IN15
PB4(3)/[SPI1_NSS](8)/ FT(2) X(3) X(3) [SPI1 master/slave select] /
35 LCD_SEG14/ I/O X HS X X Port B4 LCD segment 14 /
ADC1_IN14 ADC1_IN14
PB5/[SPI1_SCK](8)/ FT(2) [SPI1 clock] / LCD segment
36 LCD_SEG15/ I/O X X X HS X X Port B5 15 / ADC1_IN13
ADC1_IN13
PB6/[SPI1_MOSI](8)/ FT(2) [SPI1 master out/slave in]/
37 LCD_SEG16/ I/O X X X HS X X Port B6 LCD segment 16 /
ADC1_IN12 ADC1_IN12
PB7/[SPI1_MISO](8)/ FT(2) [SPI1 master in- slave out]
38 LCD_SEG17/ I/O X X X HS X X Port B7 /LCD segment 17 /
ADC1_IN11 ADC1_IN11
53 PC0(2)/I2C1_SDA I/O FT(2) X - X T(4) Port C0 I2C1 data
54 PC1(2)/I2C1_SCL I/O FT(2) X - X T(4) Port C1 I2C1 clock
PC2/USART1_RX/ USART1 receive /
57 LCD_SEG22/ADC1_IN6/ I/O FT(2) X X X HS X X Port C2 LCD segment 22 /
VREFINT ADC1_IN6 /Internal voltage
reference output
PC3/USART1_TX/ FT(2) USART1 transmit /
58 LCD_SEG23/ I/O X X X HS X X Port C3 LCD segment 23 /
ADC1_IN5 ADC1_IN5
PC4/USART1_CK/ USART1 synchronous
59 I2C1_SMB/CCO/ I/O FT(2) X X X HS X X Port C4 clock / I2C1_SMB /
ADC1_IN4 Configurable clock output /
ADC1_IN4
Doc ID023337 Rev 3 25/112
52
Pin description STM8L052R8
Table 4. High density value line STM8L05xxx pin description (continued)
Pin Input Output
number
LQFP64 Pin name Type I/O level floating Ext. interrupt High sink/source Main function (after reset) Default alternate function
wpu OD PP
PC5/OSC32_IN LSE oscillator input / [SPI1
/[SPI1_NSS](8)/ FT(2)
60 [USART1_TX](8) I/O X X X HS X X Port C5 master/slave select] /
[USART1 transmit]
PC6/OSC32_OUT/ LSE oscillator output /
[SPI1_SCK](8)/ FT(2)
61 [USART1_RX](8) I/O X X X HS X X Port C6 [SPI1 clock] / [USART1
receive]
62 PC7/ADC1_IN3 I/O FT(2) X X X HS X X Port C7 ADC1_IN3
PD0/TIM3_CH2/ Timer 3 - channel 2 /
[ADC1_TRIG](8)/ FT(2)
25 I/O X X X HS X X Port D0 [ADC1_Trigger] / LCD
LCD_SEG7/ADC1_IN22/ segment 7 / ADC1_IN22
PD1/TIM3_ETR/ FT(2) Timer 3 - trigger /
26 LCD_COM3/ I/O X X X HS X X Port D1 LCD_COM3 / ADC1_IN21
ADC1_IN21
PD2/TIM1_CH1 FT(2) Timer 1 - channel 1 / LCD
27 /LCD_SEG8/ I/O X X X HS X X Port D2 segment 8 / ADC1_IN20
ADC1_IN20
28 PD3/ TIM1_ETR/ I/O FT(2) X X X HS X X Port D3 Timer 1 - trigger / LCD
LCD_SEG9/ADC1_IN19 segment 9 / ADC1_IN19
PD4/TIM1_CH2 FT(2) Timer 1 - channel 2 / LCD
45 /LCD_SEG18/ I/O X X X HS X X Port D4 segment 18 / ADC1_IN10
ADC1_IN10
PD5/TIM1_CH3 FT(2) Timer 1 - channel 3 / LCD
46 /LCD_SEG19/ I/O X X X HS X X Port D5 segment 19 / ADC1_IN9
ADC1_IN9
PD6/TIM1_BKIN Timer 1 - break input / LCD
47 /LCD_SEG20/ I/O FT(2) X X X HS X X Port D6 segment 20 / ADC1_IN8 /
ADC1_IN8/RTC_CALIB/ RTC calibration / Internal
/VREFINT voltage reference output
PD7/TIM1_CH1N Timer 1 - inverted channel
/LCD_SEG21/ FT(2) 1/ LCD segment 21 /
48 ADC1_IN7/RTC_ALARM/V I/O X X X HS X X Port D7 ADC1_IN7 / RTC alarm /
REFINT Internal voltage reference
output
26/112 Doc ID023337 Rev 3
STM8L052R8 Pin description
Table 4. High density value line STM8L05xxx pin description (continued)
Pin Input Output
number
LQFP64 Pin name Type I/O level floating Ext. interrupt High sink/source Main function (after reset) Default alternate function
wpu OD PP
49 PG4/SPI2_NSS I/O FT(2) X X X HS X X Port G4 SPI2
master/slave select
50 PG5/SPI2_SCK I/O FT(2) X X X HS X X Port G5 SPI2 clock
51 PG6/SPI2_MOSI I/O FT(2) X X X HS X X Port G6 SPI2
master out- slave in
52 PG7/SPI2_MISO I/O FT(2) X X X HS X X Port G7 SPI2
master in- slave out
19 PE0(2)/LCD_SEG1/TIM5_C I/O FT(2) X X X HS X X Port E0 LCD segment 1/Timer 5
H2/RTC_TAMP1 channel 2/RTC tamper 1
PE1/TIM1_CH2N/ FT(2) Timer 1 - inverted channel 2
20 LCD_SEG2/RTC_TAMP2 I/O X X X HS X X Port E1 / LCD segment 2/
RTC tamper 2
PE2/TIM1_CH3N/ FT(2) Timer 1 - inverted channel 3
21 LCD_SEG3/RTC_TAMP3 I/O X X X HS X X Port E2 / LCD segment 3/
RTC tamper 3
22 PE3/LCD_SEG4 I/O FT(2) X X X HS X X Port E3 LCD segment 4
/USART2_RX /USART2 receive
23 PE4/LCD_SEG5 I/O FT(2) X X X HS X X Port E4 LCD segment 5
/USART2_TX /USART2 transmit
PE5/LCD_SEG6/ FT(2) LCD segment 6 /
24 ADC1_IN23/USART2_CK I/O X X X HS X X Port E5 ADC1_IN23/USART2
synchronous clock
63 PE6/PVD_IN/TIM5_BKIN I/O FT(2) X X X HS X X Port E6 PVD_IN
/TIM5 break input
64 PE7 I/O FT(2) X X X HS X X Port E7 TIM5 trigger
/TIM5_ETR
39 PF0/ADC1_IN24 I/O - X X X HS X X Port F0 ADC1_IN24/
/[USART3_TX] [USART3 transmit]
40 PF1/ADC1_IN25/ I/O - X X X HS X X Port F1 ADC1_IN25/
[USART3_RX] [USART3 receive]
41 PF4/LCD_SEG36 I/O FT(2) X X X HS X X Port F4 LCD_SEG36/
/LCD_COM4(5)
LCD COM4(5)
Doc ID023337 Rev 3 27/112
52
Pin description STM8L052R8
Table 4. High density value line STM8L05xxx pin description (continued)
Pin Input Output
number
LQFP64 Pin name Type I/O level floating Ext. interrupt High sink/source Main function (after reset) Default alternate function
wpu OD PP
42 PF5/LCD_SEG37/ I/O FT(2) X X X HS X X Port F5 LCD_SEG37/
LCD_COM5(5)
LCD COM5(5)
43 PF6/LCD_SEG38/ I/O FT(2) X X X HS X X Port F6 LCD_SEG38/
LCD_COM6(5)
LCD COM6(5)
44 PF7/LCD_SEG39/ I/O FT(2) X X X HS X X Port F7 LCD_SEG39/
LCD_COM7(5)
LCD COM7(5)
18 VLCD S - - - - - - - LCD booster external capacitor
11 VDD1 S - - - - - - - Digital power supply
10 VSS1 - - - - - - - - I/O ground
12 VDDA S - - - - - - - Analog supply voltage
13 VREF+ S - - - - - - - ADC1 positive voltage reference
14 PG0/USART3_RX/ I/O FT(2) X X X HS X X Port G0 USART3 receive /
[TIM2_BKIN] [Timer 2 - break input]
15 PG1/USART3_TX/ I/O FT(2) X X X HS X X Port G1 USART3 transmit /
[TIM3_BKIN] [Timer 3 -break input]
16 PG2/USART3_CK I/O FT(2) X X X HS X X Port G2 USART 3 synchronous
clock
17 PG3[TIM3_ETR] I/O FT(2) X X X HS X X Port G3 [Timer 3 - trigger]
9 VSSA/VREF- S - - - - - - - Analog ground voltage /
ADC1 negative voltage reference
55 VDD2 S - - - - - - - IOs supply voltage
56 VSS2 S - - - - - - - IOs ground voltage
PA0(6)/[USART1_CK](8)/ [USART1 synchronous
HS clock](8) / SWIM input and
1 SWIM/BEEP/IR_TIM (7) I/O - X X X X X Port A0
output /Beep output
/ Infrared Timer output
29 VDD3 S - - - - - - - IOs supply voltage
30 VSS3 S - - - - - - - IOs ground voltage
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in the STM8L15x and STM8L16x reference manual (RM0031).
28/112 Doc ID023337 Rev 3
STM8L052R8 Pin description
2. In the 5 V tolerant I/Os, protection diode to VDD is not implemented.
3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
5. SEG/COM multiplexing available on medium+ and high density devices. SEG signals are available by default (see
reference manual for details).
6. The PA0 pin is in input pull-up during the reset phase and after reset release.
7. High Sink LED driver capability available on PA0.
8. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID023337 Rev 3 29/112
52
Pin description STM8L052R8
4.1 System configuration options
As shown in Table 4: High density value line STM8L05xxx pin description, some alternate
functions can be remapped on different I/O ports by programming one of the two remapping
registers described in the “Routing interface (RI) and system configuration controller”
section in the STM8L15x and STM8L16x reference manual (RM0031).
30/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 4.
Figure 4. Memory map
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1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end
address.
Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware
registers, and to Table 8 for information on CPU/SWIM/debug module controller registers.
Table 5. Flash and RAM boundary addresses
Memory area Size Start address End address
RAM 4 Kbytes 0x00 0000 0x00 0FFF
Flash program memory 64 Kbytes 0x00 8000 0x01 7FFF
Doc ID023337 Rev 3 31/112
52
Memory and register map STM8L052R8
5.2 Register map
Table 6. I/O port hardware register map
Address Block Register label Register name Reset
status
0x00 5000 PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x01
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00
0x00 500B PC_IDR Port C input pin value register 0xXX
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x00
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0xXX
0x00 5016 Port E PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
32/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 6. I/O port hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 501E PG_ODR Port F data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX
0x00 5020 Port G PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023 to Reserved area (10 bytes)
0x00 502C
Table 7. General hardware register map
Address Block Register label Register name Reset
status
0x00 502E to Reserved area (27 bytes)
0x00 5049
0x00 5050 FLASH_CR1 Flash control register 1 0x00
0x00 5051 FLASH_CR2 Flash control register 2 0x00
0x00 5052 FLASH _PUKR Flash program memory unprotection key 0x00
Flash register
0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00
0x00 5054 FLASH _IAPSR Flash in-application programming status 0x00
register
0x00 5055 to Reserved area (27 bytes)
0x00 506F
Doc ID023337 Rev 3 33/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5070 DMA1_GCSR DMA1 global configuration & status 0xFC
register
0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00
0x00 5072 to Reserved area (3 bytes)
0x00 5074
0x00 5075 DMA1_C0CR DMA1 channel 0 configuration register 0x00
0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00
0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register 0x00
(channel 0)
0x00 5078 DMA1_C0PARH DMA1 peripheral address high register 0x52
(channel 0)
0x00 5079 DMA1_C0PARL DMA1 peripheral address low register 0x00
(channel 0)
0x00 507A DMA1 Reserved area (1 byte)
0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register 0x00
(channel 0)
0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register 0x00
(channel 0)
0x00 507D Reserved area (2 bytes)
0x00 507E
0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00
0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00
0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register 0x00
(channel 1)
0x00 5082 DMA1_C1PARH DMA1 peripheral address high register 0x52
(channel 1)
0x00 5083 DMA1_C1PARL DMA1 peripheral address low register 0x00
(channel 1)
34/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5084 Reserved area (1 byte)
0x00 5085 DMA1_C1M0ARH DMA1 memory 0 address high register 0x00
(channel 1)
0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register 0x00
(channel 1)
0x00 5087 Reserved area (2 bytes)
0x00 5088
0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00
0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00
0x00 508B DMA1_C2NDTR DMA1 number of data to transfer register 0x00
(channel 2)
0x00 508C DMA1_C2PARH DMA1 peripheral address high register 0x52
(channel 2)
0x00 508D DMA1_C2PARL DMA1 peripheral address low register 0x00
(channel 2)
0x00 508E Reserved area (1 byte)
0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register 0x00
(channel 2)
0x00 5090 DMA1 DMA1_C2M0ARL DMA1 memory 0 address low register 0x00
(channel 2)
0x00 5091 Reserved area (2 bytes)
0x00 5092
0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00
0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00
0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register 0x00
(channel 3)
0x00 5096 DMA1_C3PARH_ DMA1 peripheral address high register 0x40
C3M1ARH (channel 3)
0x00 5097 DMA1_C3PARL_ DMA1 peripheral address low register 0x00
C3M1ARL (channel 3)
0x00 5098 Reserved area (1 byte)
0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register 0x00
(channel 3)
0x00 509A DMA1_C3M0ARL DMA1 memory 0 address low register 0x00
(channel 3)
0x00 509B to Reserved area (2 bytes)
0x00 509C
Doc ID023337 Rev 3 35/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 509D SYSCFG_RMPCR3 Remapping register 3 0x00
0x00 509E SYSCFG SYSCFG_RMPCR1 Remapping register 1 0x00
SYSCFG
0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00
0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 ITC - EXTI EXTI_CR3 External interrupt control register 3 0x00
0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00
0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00
0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00
0x00 50A6 WFE_CR1 WFE control register 1 0x00
0x00 50A7 WFE WFE_CR2 WFE control register 2 0x00
0x00 50A8 WFE_CR3 WFE control register 3 0x00
0x00 50A9 WFE_CR4 WFE control register 4 0x00
0x00 50AA ITC - EXTI EXTI_CR4 External interrupt control register 4 0x00
0x00 50AB EXTI_CONF2 External interrupt port select register 2 0x00
0x00 50A9 to Reserved area (7 bytes)
0x00 50AF
0x00 50B0 RST RST_CR Reset control register 0x00
0x00 50B1 RST_SR Reset status register 0x01
0x00 50B2 PWR PWR_CSR1 Power control and status register 1 0x00
0x00 50B3 PWR_CSR2 Power control and status register 2 0x00
0x00 50B4 to Reserved area (12 bytes)
0x00 50BF
36/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 50C0 CLK_CKDIVR Clock master divider register 0x03
0x00 50C1 CLK_CRTCR Clock RTC register 0x00(1)
0x00 50C2 CLK_ICKR Internal clock control register 0x11
0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00
0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x00
0x00 50C5 CLK_CCOR Configurable clock control register 0x00
0x00 50C6 CLK_ECKR External clock control register 0x00
0x00 50C7 CLK_SCSR System clock status register 0x01
0x00 50C8 CLK CLK_SWR System clock switch register 0x01
0x00 50C9 CLK_SWCR Clock switch control register 0xX0
0x00 50CA CLK_CSSR Clock security system register 0x00
0x00 50CB CLK_CBEEPR Clock BEEP register 0x00
0x00 50CC CLK_HSICALR HSI calibration register 0xXX
0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00
0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11100x
0x00 50D0 CLK_PCKENR3 Peripheral clock gating register 3 0x00
0x00 50D1 to Reserved area (2 bytes)
0x00 50D2
0x00 50D3 WWDG WWDG_CR WWDG control register 0x7F
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5 to Reserved area (11 bytes)
00 50DF
0x00 50E0 IWDG_KR IWDG key register 0xXX
0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to Reserved area (13 bytes)
0x00 50EF
0x00 50F0 BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1 BEEP Reserved area (2 bytes)
0x00 50F2
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4 to Reserved area (76 bytes)
0x00 513F
Doc ID023337 Rev 3 37/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5140 RTC_TR1 Time register 1 0x00
0x00 5141 RTC_TR2 Time register 2 0x00
0x00 5142 RTC_TR3 Time register 3 0x00
0x00 5143 Reserved area (1 byte)
0x00 5144 RTC_DR1 Date register 1 0x01
0x00 5145 RTC_DR2 Date register 2 0x21
0x00 5146 RTC_DR3 Date register 3 0x00
0x00 5147 Reserved area (1 byte)
0x00 5148 RTC_CR1 Control register 1 0x00(1)
0x00 5149 RTC_CR2 Control register 2 0x00(1)
0x00 514A RTC_CR3 Control register 3 0x00(1)
0x00 514B Reserved area (1 byte)
0x00 514C RTC_ISR1 Initialization and status register 1 0x01
0x00 514D RTC_ISR2 Initialization and Status register 2 0x00
0x00 514E Reserved area (2 bytes)
0x00 514F
0x00 5150 RTC RTC_SPRERH(1) Synchronous prescaler register high 0x00(1)
0x00 5151 RTC_SPRERL(1) Synchronous prescaler register low 0xFF(1)
0x00 5152 RTC_APRER(1) Asynchronous prescaler register 0x7F(1)
0x00 5153 Reserved area (1 byte)
0x00 5154 RTC_WUTRH(1) Wakeup timer register high 0xFF(1)
0x00 5155 RTC_WUTRL(1) Wakeup timer register low 0xFF(1)
0x00 5156 Reserved area (1 bytes)
0x00 5157 RTC_SSRL Subsecond register low 0x00
0x00 5158 RTC_SSRH Subsecond register high 0x00
0x00 5159 RTC_WPR Write protection register 0x00
0x00 515A RTC_SHIFTRH Shift register high 0x00
0x00 515B RTC_SHIFTRL Shift register low 0x00
0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00(1)
0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00(1)
0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00(1)
0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00(1)
0x00 5160 to Reserved area (4 bytes)
0x00 5163
38/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5164 RTC_ALRMASSRH Alarm A subsecond register high 0x00(1)
0x00 5165 RTC RTC_ALRMASSRL Alarm A subsecond register low 0x00(1)
0x00 5166 RTC_ALRMASSMS Alarm A masking register 0x00(1)
KR
0x00 5167 to Reserved area (3 bytes)
0x00 5169
0x00 516A RTC_CALRH Calibration register high 0x00(1)
0x00 516B RTC RTC_CALRL Calibration register low 0x00(1)
0x00 516C RTC_TCR1 Tamper control register 1 0x00(1)
0x00 516D RTC_TCR2 Tamper control register 2 0x00(1)
0x00 516E to Reserved area
0x00 518A
0x00 5190 CSSLSE CSSLSE_CSR CSS on LSE control and status register 0x00(1)
0x00 519A to Reserved area
0x00 51FF
0x00 5200 SPI1_CR1 SPI1 control register 1 0x00
0x00 5201 SPI1_CR2 SPI1 control register 2 0x00
0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00
0x00 5203 SPI1 SPI1_SR SPI1 status register 0x02
0x00 5204 SPI1_DR SPI1 data register 0x00
0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07
0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00
0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00
0x00 5208 to Reserved area (8 bytes)
0x00 520F
Doc ID023337 Rev 3 39/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5210 I2C1_CR1 I2C1 control register 1 0x00
0x00 5211 I2C1_CR2 I2C1 control register 2 0x00
0x00 5212 I2C1_FREQR I2C1 frequency register 0x00
0x00 5213 I2C1_OARL I2C1 own address register low 0x00
0x00 5214 I2C1_OARH I2C1 own address register high 0x00
0x00 5215 I2C1_OARH I2C1 own address register for dual mode 0x00
0x00 5216 I2C1_DR I2C1 data register 0x00
0x00 5217 I2C1 I2C1_SR1 I2C1 status register 1 0x00
0x00 5218 I2C1_SR2 I2C1 status register 2 0x00
0x00 5219 I2C1_SR3 I2C1 status register 3 0x0x
0x00 521A I2C1_ITR I2C1 interrupt control register 0x00
0x00 521B I2C1_CCRL I2C1 clock control register low 0x00
0x00 521C I2C1_CCRH I2C1 clock control register high 0x00
0x00 521D I2C1_TRISER I2C1 TRISE register 0x02
0x00 521E I2C1_PECR I2C1 packet error checking register 0x00
0x00 521F to Reserved area (17 bytes)
0x00 522F
0x00 5230 USART1_SR USART1 status register 0xC0
0x00 5231 USART1_DR USART1 data register 0xXX
0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00
0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00
0x00 5234 USART1_CR1 USART1 control register 1 0x00
0x00 5235 USART1 USART1_CR2 USART1 control register 2 0x00
0x00 5236 USART1_CR3 USART1 control register 3 0x00
0x00 5237 USART1_CR4 USART1 control register 4 0x00
0x00 5238 USART1_CR5 USART1 control register 5 0x00
0x00 5239 USART1_GTR USART1 guard time register 0x00
0x00 523A USART1_PSCR USART1 prescaler register 0x00
0x00 523B to Reserved area (21 bytes)
0x00 524F
40/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5250 TIM2_CR1 TIM2 control register 1 0x00
0x00 5251 TIM2_CR2 TIM2 control register 2 0x00
0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00
0x00 5253 TIM2_ETR TIM2 external trigger register 0x00
0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00
0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5256 TIM2_SR1 TIM2 status register 1 0x00
0x00 5257 TIM2_SR2 TIM2 status register 2 0x00
0x00 5258 TIM2_EGR TIM2 event generation register 0x00
0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 525B TIM2 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 525C TIM2_CNTRH TIM2 counter high 0x00
0x00 525D TIM2_CNTRL TIM2 counter low 0x00
0x00 525E TIM2_PSCR TIM2 prescaler register 0x00
0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
0x00 5262 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00
0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5265 TIM2_BKR TIM2 break register 0x00
0x00 5266 TIM2_OISR TIM2 output idle state register 0x00
0x00 5267 to Reserved area (25 bytes)
0x00 527F
Doc ID023337 Rev 3 41/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5280 TIM3_CR1 TIM3 control register 1 0x00
0x00 5281 TIM3_CR2 TIM3 control register 2 0x00
0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00
0x00 5283 TIM3_ETR TIM3 external trigger register 0x00
0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00
0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5286 TIM3_SR1 TIM3 status register 1 0x00
0x00 5287 TIM3_SR2 TIM3 status register 2 0x00
0x00 5288 TIM3_EGR TIM3 event generation register 0x00
0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00
0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00
0x00 528B TIM3 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00
0x00 528C TIM3_CNTRH TIM3 counter high 0x00
0x00 528D TIM3_CNTRL TIM3 counter low 0x00
0x00 528E TIM3_PSCR TIM3 prescaler register 0x00
0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF
0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF
0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00
0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00
0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00
0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00
0x00 5295 TIM3_BKR TIM3 break register 0x00
0x00 5296 TIM3_OISR TIM3 output idle state register 0x00
0x00 5297 to Reserved area (25 bytes)
0x00 52AF
42/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00
0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00
0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00
0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00
0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00
0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00
0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00
0x00 52B8 TIM1_EGR TIM1 event generation register 0x00
0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00
0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00
0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00
0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00
0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00
0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00
0x00 52BF TIM1_CNTRH TIM1 counter high 0x00
0x00 52C0 TIM1 TIM1_CNTRL TIM1 counter low 0x00
0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF
0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF
0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00
0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00
0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00
0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00
0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00
0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00
0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00
0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00
0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00
0x00 52CE TIM1_BKR TIM1 break register 0x00
0x00 52CF TIM1_DTR TIM1 dead-time register 0x00
0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00
0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00
Doc ID023337 Rev 3 43/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 52D2 TIM1 TIM1_DCR2 TIM1 DMA1 control register 2 0x00
0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00
0x00 52D4 to Reserved area (12 bytes)
0x00 52DF
0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00
0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00
0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00
0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00
0x00 52E4 TIM4 TIM4_IER TIM4 Interrupt enable register 0x00
0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00
0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00
0x00 52E7 TIM4_CNTR TIM4 counter 0x00
0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00
0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00
0x00 52EA to Reserved area (21 bytes)
0x00 52FE
0x00 52FF IRTIM IR_CR Infrared control register 0x00
0x00 5300 TIM5_CR1 TIM5 control register 1 0x00
0x00 5301 TIM5_CR2 TIM5 control register 2 0x00
0x00 5302 TIM5_SMCR TIM5 Slave mode control register 0x00
0x00 5303 TIM5_ETR TIM5 external trigger register 0x00
0x00 5304 TIM5_DER TIM5 DMA1 request enable register 0x00
0x00 5305 TIM5_IER TIM5 interrupt enable register 0x00
0x00 5306 TIM5_SR1 TIM5 status register 1 0x00
0x00 5307 TIM5_SR2 TIM5 status register 2 0x00
0x00 5308 TIM5 TIM5_EGR TIM5 event generation register 0x00
0x00 5309 TIM5_CCMR1 TIM5 Capture/Compare mode register 1 0x00
0x00 530A TIM5_CCMR2 TIM5 Capture/Compare mode register 2 0x00
0x00 530B TIM5_CCER1 TIM5 Capture/Compare enable register 1 0x00
0x00 530C TIM5_CNTRH TIM5 counter high 0x00
0x00 530D TIM5_CNTRL TIM5 counter low 0x00
0x00 530E TIM5_PSCR TIM5 prescaler register 0x00
0x00 530F TIM5_ARRH TIM5 Auto-reload register high 0xFF
0x00 5310 TIM5_ARRL TIM5 Auto-reload register low 0xFF
44/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5311 TIM5_CCR1H TIM5 Capture/Compare register 1 high 0x00
0x00 5312 TIM5_CCR1L TIM5 Capture/Compare register 1 low 0x00
0x00 5313 TIM5 TIM5_CCR2H TIM5 Capture/Compare register 2 high 0x00
0x00 5314 TIM5_CCR2L TIM5 Capture/Compare register 2 low 0x00
0x00 5315 TIM5_BKR TIM5 break register 0x00
0x00 5316 TIM5_OISR TIM5 output idle state register 0x00
0x00 5317
to Reserved area
0x00 533F
0x00 5340 ADC1_CR1 ADC1 configuration register 1 0x00
0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00
0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F
0x00 5343 ADC1_SR ADC1 status register 0x00
0x00 5344 ADC1_DRH ADC1 data register high 0x00
0x00 5345 ADC1_DRL ADC1 data register low 0x00
0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F
0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF
0x00 5348 ADC1 ADC1_LTRH ADC1 low threshold register high 0x00
0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00
0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00
0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00
0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00
0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00
0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00
0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00
0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00
0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00
0x00 5352 to Reserved area (110 bytes)
0x00 53BF
Doc ID023337 Rev 3 45/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 53C0 SPI2_CR1 SPI2 control register 1 0x00
0x00 53C1 SPI2_CR2 SPI2 control register 2 0x00
0x00 53C2 SPI2_ICR SPI2 interrupt control register 0x00
0x00 53C3 SPI2 SPI2_SR SPI2 status register 0x02
0x00 53C4 SPI2_DR SPI2 data register 0x00
0x00 53C5 SPI2_CRCPR SPI2 CRC polynomial register 0x07
0x00 53C6 SPI2_RXCRCR SPI2 Rx CRC register 0x00
0x00 53C7 SPI2_TXCRCR SPI2 Tx CRC register 0x00
0x00 53C8 to Reserved area
0x00 53DF
0x00 53E0 USART2_SR USART2 status register 0xC0
0x00 53E1 USART2_DR USART2 data register 0xXX
0x00 53E2 USART2_BRR1 USART2 baud rate register 1 0x00
0x00 53E3 USART2_BRR2 USART2 baud rate register 2 0x00
0x00 53E4 USART2_CR1 USART2 control register 1 0x00
0x00 53E5 USART2 USART2_CR2 USART2 control register 2 0x00
0x00 53E6 USART2_CR3 USART2 control register 3 0x00
0x00 53E7 USART2_CR4 USART2 control register 4 0x00
0x00 53E8 USART2_CR5 USART2 control register 5 0x00
0x00 53E9 USART2_GTR USART2 guard time register 0x00
0x00 53EA USART2_PSCR USART2 prescaler register 0x00
0x00 53EB to Reserved area
0x00 53EF
0x00 53F0 USART3_SR USART3 status register 0xC0
0x00 53F1 USART3_DR USART3 data register 0xXX
0x00 53F2 USART3_BRR1 USART3 baud rate register 1 0x00
0x00 53F3 USART3_BRR2 USART3 baud rate register 2 0x00
0x00 53F4 USART3_CR1 USART3 control register 1 0x00
0x00 53F5 USART3 USART3_CR2 USART3 control register 2 0x00
0x00 53F6 USART3_CR3 USART3 control register 3 0x00
0x00 53F7 USART3_CR4 USART3 control register 4 0x00
0x00 53F8 USART3_CR5 USART3 control register 5 0x00
0x00 53F9 USART3_GTR USART3 guard time register 0x00
0x00 53FA USART3_PSCR USART3 prescaler register 0x00
46/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 53FB to Reserved area
0x00 53FF
0x00 5400 LCD_CR1 LCD control register 1 0x00
0x00 5401 LCD_CR2 LCD control register 2 0x00
0x00 5402 LCD_CR3 LCD control register 3 0x00
0x00 5403 LCD LCD_FRQ LCD frequency selection register 0x00
0x00 5404 LCD_PM0 LCD Port mask register 0 0x00
0x00 5405 LCD_PM1 LCD Port mask register 1 0x00
0x00 5406 LCD_PM2 LCD Port mask register 2 0x00
0x00 5407 Reserved area
0x00 5408 LCD_PM4 LCD Port mask register 4 0x00
0x00 5409 to Reserved area (3 bytes)
0x00 540B
0x00 540C LCD_RAM0 LCD display memory 0 0x00
0x00 540D LCD_RAM1 LCD display memory 1 0x00
0x00 540E LCD_RAM2 LCD display memory 2 0x00
0x00 540F LCD_RAM3 LCD display memory 3 0x00
0x00 5410 LCD_RAM4 LCD display memory 4 0x00
0x00 5411 LCD_RAM5 LCD display memory 5 0x00
0x00 5412 LCD_RAM6 LCD display memory 6 0x00
0x00 5413 LCD_RAM7 LCD display memory 7 0x00
0x00 5414 LCD_RAM8 LCD display memory 8 0x00
0x00 5415 LCD_RAM9 LCD display memory 9 0x00
0x00 5416 LCD LCD_RAM10 LCD display memory 10 0x00
0x00 5417 LCD_RAM11 LCD display memory 11 0x00
0x00 5418 LCD_RAM12 LCD display memory 12 0x00
0x00 5419 LCD_RAM13 LCD display memory 13 0x00
0x00 541A Reserved area
0x00 541B LCD_RAM15 LCD display memory 15 0x00
0x00 541C Reserved area
0x00 541D LCD_RAM17 LCD display memory 17 0x00
0x00 541E Reserved area
0x00 541F LCD_RAM19 LCD display memory 19 0x00
0x00 5420 Reserved area
0x00 5421 LCD_RAM21 LCD display memory 21 0x00
Doc ID023337 Rev 3 47/112
52
Memory and register map STM8L052R8
Table 7. General hardware register map (continued)
Address Block Register label Register name Reset
status
0x00 5422 to Reserved area
0x00 542E
0x00 542F LCD LCD_CR4 LCD control register 4 0x00
0x00 5430 Reserved area (1 byte) 0x00
0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00
0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00
0x00 5433 RI_IOIR1 I/O input register 1 0xXX
0x00 5434 RI_IOIR2 I/O input register 2 0xXX
0x00 5435 RI_IOIR3 I/O input register 3 0xXX
0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00
0x00 5437 RI RI_IOCMR2 I/O control mode register 2 0x00
0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00
0x00 5439 RI_IOSR1 I/O switch register 1 0x00
0x00 543A RI_IOSR2 I/O switch register 2 0x00
0x00 543B RI_IOSR3 I/O switch register 3 0x00
0x00 543C RI_IOGCR I/O group control register 0x3F
0x00 543D RI_ASCR1 Analog switch register 1 0x00
0x00 543E RI_ASCR2 Analog switch register 2 0x00
0x00 543F RI_RCR Resistor control register 1 0x00
0x00 5440 to Reserved area (5 bytes)
0x00 5444
1. These registers are not impacted by a system reset. They are reset at power-on.
48/112 Doc ID023337 Rev 3
STM8L052R8 Memory and register map
Table 8. CPU/SWIM/debug module/interrupt controller registers
Address Block Register Label Register Name Reset
Status
0x00 7F00 A Accumulator 0x00
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
0x00 7F05 CPU(1) XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to Reserved area (85 bytes)
0x00 7F5F CPU
0x00 7F60 CFG_GCR Global configuration register 0x00
0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF
0x00 7F73 ITC-SPR ITC_SPR4 Interrupt Software priority register 4 0xFF
0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF
0x00 7F78 to Reserved area (2 bytes)
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81 to Reserved area (15 bytes)
0x00 7F8F
Doc ID023337 Rev 3 49/112
52
Memory and register map STM8L052R8
Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)
Address Block Register Label Register Name Reset
Status
0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM Debug module control register 1 0x00
0x00 7F97 DM_CR2 DM Debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to Reserved area (5 bytes)
0x00 7F9F
1. Accessible by debug module only
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STM8L052R8 Interrupt vector mapping
6 Interrupt vector mapping
Table 9. Interrupt mapping
Wakeup Wakeup Wakeup Wakeup
IRQ Source Description from Halt from from Wait from Wait Vector
No. block mode Active- (WFI (WFE address
mode)(1)
halt mode mode)
RESET Reset Yes Yes Yes Yes 0x00 8000
TRAP Software interrupt - - - - 0x00 8004
0 TLI(2) External Top level Interrupt - - - - 0x00 8008
1 FLASH EOP/WR_PG_DIS - - Yes Yes(5) 0x00 800C
2 DMA1 0/1 DMA1 channels 0/1 - - Yes Yes(5) 0x00 8010
3 DMA1 2/3 DMA1 channels 2/3 - - Yes Yes(5) 0x00 8014
4 RTC/LSE_ RTC alarm interrupt/LSE Yes Yes Yes Yes 0x00 8018
CSS CSS interrupt
5 EXTI E/F/ PortE/F interrupt/PVD Yes Yes Yes Yes(5) 0x00 801C
PVD(3)
interrupt
6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes(5) 0x00 8020
7 EXTID/H External interrupt port D Yes Yes Yes Yes(5) 0x00 8024
8 EXTI0 External interrupt 0 Yes Yes Yes Yes(5) 0x00 8028
9 EXTI1 External interrupt 1 Yes Yes Yes Yes(5) 0x00 802C
10 EXTI2 External interrupt 2 Yes Yes Yes Yes(5) 0x00 8030
11 EXTI3 External interrupt 3 Yes Yes Yes Yes(5) 0x00 8034
12 EXTI4 External interrupt 4 Yes Yes Yes Yes(5) 0x00 8038
13 EXTI5 External interrupt 5 Yes Yes Yes Yes(5) 0x00 803C
14 EXTI6 External interrupt 6 Yes Yes Yes Yes(5) 0x00 8040
15 EXTI7 External interrupt 7 Yes Yes Yes Yes(5) 0x00 8044
16 LCD LCD interrupt - - Yes Yes 0x00 8048
system clock switch/ Yes(5)
17 CLK/TIM1 CSS interrupt/ - - Yes 0x00 804C
TIM 1 break
18 ADC1 ACD1 Yes Yes Yes Yes(5) 0x00 8050
TIM2 update/overflow/
trigger/break
19 TIM2/USART2 USART2 transmission - - Yes Yes(5) 0x00 8054
complete/transmit data
register empty
interrupt
20 TIM2/USART2 capture/ - - Yes Yes(5) 0x00 8058
compare/USART2 interrupt
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Interrupt vector mapping STM8L052R8
Table 9. Interrupt mapping (continued)
Wakeup Wakeup Wakeup Wakeup
IRQ Source Description from Halt from from Wait from Wait Vector
No. block mode Active- (WFI (WFE address
mode)(1)
halt mode mode)
TIM3 update/overflow/
trigger/break USART3
21 TIM3/USART3 transmission - - Yes Yes(5) 0x00 805C
complete/transmit data
register empty
interrupt
TIM3
capture/compareUSART3
22 TIM3/USART3 Receive register - - Yes Yes(5) 0x00 8060
data full/overrun/idle line
detected/parity error/
interrupt
23 TIM1 Update /overflow/trigger/ - - - Yes(5) 0x00 8064
COM
24 TIM1 Capture/compare - - - Yes(5) 0x00 8068
25 TIM4 TIM4 update/overflow/ - - Yes Yes(5) 0x00 806C
trigger
26 SPI1 End of Transfer Yes Yes Yes Yes(5) 0x00 8070
USART1 transmission
complete/transmit data
27 USART1/TIM5 register empty/ - - Yes Yes(5) 0x00 8074
TIM5 update/overflow/
trigger/break
USART1 received data
ready/overrun error/ Yes(5)
28 USART1/TIM5 idle line detected/parity - - Yes 0x00 8078
error/TIM5
capture/compare
29 I2C1/SPI2 I2C1 interrupt(4)/SPI2 Yes Yes Yes Yes(5) 0x00 807C
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.
2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.
3. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
4. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
5. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
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STM8L052R8 Option bytes
7 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 10 for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8Lxx Flash programming manual (PM0054) and STM8 SWIM and Debug
Manual (UM0320) for information on SWIM programming procedures.
Table 10. Option byte addresses
Option Option bits Factory
Address Option name byte default
No. 7 6 5 4 3 2 1 0 setting
Read-out
00 4800 protection OPT0 ROP[7:0] 0x00
(ROP)
00 4802 UBC (User OPT1 UBC[7:0] 0x00
Boot code size)
00 4807 PCODESIZE OPT2 PCODE[7:0] 0x00
Independent OPT3 WWDG WWDG IWDG IWDG
00 4808 watchdog [3:0] Reserved _HALT _HW _HALT _HW 0x00
option
Number of
stabilization
00 4809 clock cycles for OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00
HSE and LSE
oscillators
00 480A Brownout reset OPT5 Reserved BOR_TH BOR_ 0x01
(BOR) [3:0] ON
00 480B Bootloader OPTBL 0x00
00 480C option bytes [15:0] OPTBL[15:0] 0x00
(OPTBL)
Doc ID023337 Rev 3 53/112
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Option bytes STM8L052R8
Table 11. Option byte description
Option Option description
byte no.
ROP[7:0] Memory readout protection (ROP)
OPT0 0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L reference manual (RM0031).
UBC[7:0] Size of the user boot code area
UBC[7:0] Size of the user boot code area
0x00: No UBC
OPT1 0x01: Page 0 reserved for the UBC and write protected.
...
0xFF: Page 0 to 254 reserved for the UBC and write-protected.
Refer to User boot code section in the STM8L reference manual (RM0031).
PCODESIZE[7:0] Size of the proprietary code area
0x00: No proprietary code area
0x01: Page 0 reserved for the proprietary code and read/write protected.
OPT2 ...
0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.
Refer to Proprietary code area (PCODE) section in the STM8L reference manual
(RM0031) for more details.
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent watchdog off in Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
OPT3 1: Independent watchdog stopped in Halt/Active-halt mode
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
OPT4 0x11 - 4096 clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
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STM8L052R8 Option bytes
Table 11. Option byte description (continued)
Option Option description
byte no.
BOR_ON:
0: Brownout reset off
OPT5 1: Brownout reset on
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 16 for details on the thresholds
according to the value of BOR_TH bits.
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on the content of
OPTBL addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the
bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.
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Electrical parameters STM8L052R8
8 Electrical parameters
8.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
8.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
8.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
8.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
8.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 5.
Figure 5. Pin loading conditions
670/3,1
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06Y9
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STM8L052R8 Electrical parameters
8.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 6.
Figure 6. Pin input voltage
670/3,1
9,1
06Y9
8.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics,
Table 13: Current characteristics and Table 14: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
The device’s mission profile (application conditions) is compliant with the JEDEC JESD47
Qualification Standard, the extended mission profiles are available on demand.
Table 12. Voltage characteristics
Symbol Ratings Min Max Unit
VDD- VSS External supply voltage - 0.3 4.0
(including VDDA)(1)
Input voltage on true open-drain pins VSS - 0.3 VDD + 4.0
(PC0 and PC1)
VIN(2) Input voltage on five-volt tolerant (FT) VSS - 0.3 VDD + 4.0 V
pins
Input voltage on any other pin VSS - 0.3 4.0
see Absolute maximum
VESD Electrostatic discharge voltage ratings (electrical sensitivity)
on page 105
1. All pcoonwneerc(tVeDdDto1, tVhDeDe2x,tVerDnDa3l,pVoDwDe4r, sVuDpDpAly) .and ground (VSS1, VSS2, VSS3, VSS4, VSSA) pins must always
be
2. VIN maximum must always be respected. Refer to Table 13. for maximum allowed injected current values.
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Electrical parameters STM8L052R8
Table 13. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD power line (source) 80
IVSS Total current out of VSS ground line (sink) 80
Output current sunk by IR_TIM pin 80
(with high sink LED driver capability)
IIO Output current sunk by any other I/O and control pin 25
Output current sourced by any I/Os and control pin - 25 mA
Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0
IINJ(PIN) Injected current on five-volt tolerant (FT) pins(1) - 5 / +0
Injected current on any other pin (2) - 5 / +5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) (3) ± 25
1. Positive injection is not possible on 1th2e. sfoerIm/Oasx.imA unmegaaltliovweeindjeincptiuotnviosltiangdeucveadlubeys.VIN
never be exceeded. Refer to Table
2. A positive injection isReinfdeur ctoedTabbyleV1IN2>.VfoDrDmwahxiilme uamneagllaotwiveedininjepcuttiovnolitsaigneduvcaeludebs.y VIN
never be exceeded.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 14. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature 150
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STM8L052R8 Electrical parameters
8.3 Operating conditions
Subject to general operating conditions for VDD and TA.
8.3.1 General operating conditions
Table 15. General operating conditions
Symbol Parameter Conditions Min. Max. Unit
fSYSCLK(1) System clock 1.8 V ≤VDD < 3.6 V 0 16 MHz
frequency
VDD Standard operating - 1.8 3.6 V
voltage
VDDA Analog operating Must be at the same 1.8 3.6 V
voltage potential as VDD
PD(2) Power dissipation at LQFP64 - 288 mW
TA= 85 °C
TA Temperature range 1.8 V ≤VDD < 3.6 V -40 85
TJ Junction temperature -40 °C ≤TA < 85 °C -40 105(3) °C
range
1. fSYSCLK = fCPU
2. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in “Thermal characteristics”
table.
3. TJmax is given by the test limit. Above this value the product behavior is not guaranteed.
Doc ID023337 Rev 3 59/112
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Electrical parameters STM8L052R8
8.3.2 Embedded reset and power control block characteristics
Table 16. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
BOR detector 0(1) - ∞(1) µs/V
VDD rise time rate enabled
BOR detector 0(1) - 1(1) ms/V
tVDD disabled
BOR detector 20(1) - ∞(1) µs/V
VDD fall time rate enabled
BOR detector Reset below voltage functional range
disabled
VDD rising
BOR detector - 3 -
tTEMP Reset release delay enabled ms
VDD rising
BOR detector - 1 -
disabled
VPOR Power-on reset threshold Rising edge 1.3(2) 1.5 1.65
VPDR Power-down reset threshold Falling edge 1.3(2) 1.5 1.65
VBOR0 Brown-out reset threshold 0 Falling edge 1.67 1.7 1.74
(BOR_TH[2:0]=000) Rising edge 1.69 1.75 1.80
VBOR1 Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97
(BOR_TH[2:0]=001) Rising edge 1.96 2.04 2.07
Falling edge 2.22 2.3 2.35 V
VBOR2 Brown-out reset threshold 2
(BOR_TH[2:0]=010) Rising edge 2.31 2.41 2.44
VBOR3 Brown-out reset threshold 3 Falling edge 2.45 2.55 2.60
(BOR_TH[2:0]=011) Rising edge 2.54 2.66 2.7
VBOR4 Brown-out reset threshold 4 Falling edge 2.68 2.80 2.85
(BOR_TH[2:0]=100) Rising edge 2.78 2.90 2.95
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STM8L052R8 Electrical parameters
Table 16. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
VPVD0 PVD threshold 0 Falling edge 1.80 1.84 1.88
Rising edge 1.88 1.94 1.99
VPVD1 PVD threshold 1 Falling edge 1.98 2.04 2.09
Rising edge 2.08 2.14 2.18
VPVD2 PVD threshold 2 Falling edge 2.2 2.24 2.28
Rising edge 2.28 2.34 2.38
VPVD3 PVD threshold 3 Falling edge 2.39 2.44 2.48 V
Rising edge 2.47 2.54 2.58
VPVD4 PVD threshold 4 Falling edge 2.57 2.64 2.69
Rising edge 2.68 2.74 2.79
VPVD5 PVD threshold 5 Falling edge 2.77 2.83 2.88
Rising edge 2.87 2.94 2.99
VPVD6 PVD threshold 6 Falling edge 2.97 3.05 3.09
Rising edge 3.08 3.15 3.20
BOR0 threshold - 40 -
Vhyst Hysteresis voltage All BOR and PVD mV
thresholds - 100 -
excepting BOR0
1. Guaranteed by design.
2. Guaranteed by characterization results.
Doc ID023337 Rev 3 61/112
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Electrical parameters STM8L052R8
Figure 7. Power supply thresholds
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62/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
8.3.3 Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
• All I/O pins in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled except if explicitly mentioned.
In the following table, data are based on characterization results, unless otherwise
specified.
Subject to general operating conditions for VDD and TA.
Table 17. Total current consumption in Run mode
Max.
Symbol Parameter Conditions(1) Typ. Unit
55°C 85 °C
fCPU = 125 kHz 0.22 0.28 0.39
fCPU = 1 MHz 0.32 0.38 0.49
HSI RC osc. fCPU = 4 MHz 0.59 0.65 0.76
(16 MHz)(3)
fCPU = 8 MHz 0.93 0.99 1.1
fCPU = 16 MHz 1.62 1.68 1.79(4)
All peripherals fCPU = 125 kHz
OFF, 0.21 0.25 0.35
Supply code executed fCPU = 1 MHz 0.3 0.34 0.44
IDD(RUN) current in from RAM, HSE external mA
run mode(2) VDD from 1.8 V clock fCPU = 4 MHz 0.57 0.61 0.71
to (fCPU=fHSE)(5) fCPU = 8 MHz 0.95 0.99 1.09
3.6 V
fCPU = 16 MHz 1.73 1.77 1.87(4)
LSI RC osc. fCPU = fLSI 0.029 0.035 0.039
(typ. 38 kHz)
LSE external
clock fCPU = fLSE 0.028 0.034 0.038
(32.768 kHz)
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Electrical parameters STM8L052R8
Table 17. Total current consumption in Run mode (continued)
Max.
Symbol Parameter Conditions(1) Typ. Unit
55°C 85 °C
fCPU = 125 kHz 0.35 0.46 0.48
fCPU = 1 MHz 0.54 0.65 0.67
HSI RC fCPU = 4 MHz 1.16 1.27 1.29
osc.(6)
fCPU = 8 MHz 1.97 2.08 2.1
fCPU = 16 MHz 3.54 3.65 3.67
All peripherals fCPU = 125 kHz 0.35 0.44 0.46
Supply OFF, code
IDD(RUN) current executed from fCPU = 1 MHz 0.53 0.62 0.64 mA
in Run Flash, HSE external
mode VDD from 1.8 V clock fCPU = 4 MHz 1.13 1.22 1.24
to 3.6 V (fCPU=fHSE) (5) fCPU = 8 MHz 2 2.09 2.11
fCPU = 16 MHz 3.69 3.78 3.8
LSI RC osc. fCPU = fLSI 0.110 0.123 0.130
LSE external
clock fCPU = fLSE 0.100 0.101 0.104
(32.768 kHz)(7)
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., fCPU=fSYSCLK
2. CPU executing typical data processing
3. The run from RAM consumption can be approximated with the linear formula:
IDD(run_from_RAM) = Freq. * 95 µA/MHz + 250 µA
4. Tested in production.
5. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 28.
6. The run from Flash consumption can be approximated with the linear formula:
IDD(run_from_Flash) = Freq. * 200 µA/MHz + 330 µA
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29
64/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 8. Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz 1)
,''5XQ +6,0+] P$
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&
&
9'' 9
06 9
1. Typical current consumption measured with code executed from RAM.
Figure 9. Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz1)
,''5XQ +6,((30+] P$
&
&
&
9'' 9
06 9
1. Typical current consumption measured with code executed from Flash.
Doc ID023337 Rev 3 65/112
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Electrical parameters STM8L052R8
In the following table, data are based on characterization results, unless otherwise
specified.
Table 18. Total current consumption in Wait mode
Max
Symbol Parameter Conditions(1) Typ Unit
55°C 85 °C
fCPU = 125 kHz 0.21 0.29 0.33
fCPU = 1 MHz 0.25 0.33 0.37
HSI fCPU = 4 MHz 0.32 0.4 0.44
CPU not fCPU = 8 MHz 0.42 0.496 0.54
clocked, fCPU = 16 MHz 0.66 0.736 0.78(3)
all peripherals
OFF, fCPU = 125 kHz 0.19 0.21 0.3
code executed mA
from RAM fCPU = 1 MHz 0.2 0.23 0.32
with Flash in IDDQ HSE external clock fCPU = 4 MHz 0.27 0.3 0.39
mode,(2) (fCPU=fHSE)(4)
VDD from fCPU = 8 MHz 0.37 0.4 0.49
1.8 V to 3.6 V fCPU = 16 MHz 0.63 0.66 0.75(3)
LSI fCPU = fLSI 0.028 0.037 0.039
Supply LSE(5) external clock fCPU = fLSE 0.027 0.035 0.038
IDD(Wait) current in (32.768 kHz)
Wait mode fCPU = 125 kHz 0.27 0.36 0.42
fCPU = 1 MHz 0.29 0.38 0.44
HSI fCPU = 4 MHz 0.37 0.46 0.52
fCPU = 8 MHz 0.45 0.55 0.61
CPU not fCPU = 16 MHz 0.69 0.79 0.85
clocked,
all peripherals fCPU = 125 kHz 0.23 0.29 0.32
OFF, fCPU = 1 MHz mA
code executed HSE(4) external clock 0.24 0.31 0.34
from Flash, (fCPU= fCPU = 4 MHz 0.32 0.39 0.42
VDD from HSE)
1.8 V to 3.6 V fCPU = 8 MHz 0.42 0.49 0.51
fCPU = 16 MHz 0.7 0.77 0.79
LSI fCPU = fLSI 0.037 0.085 0.105
LSE(5) external clock fCPU = fLSE 0.036 0.082 0.095
(32.768 kHz)
1. All peripherals OFF, VDD from 1.8 V to 3.6 V, HSI internal RC osc., fCPU = fSYSCLK
2. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
3. Tested in production.
4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 28.
66/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD HSE) must be added. Refer to Table 29
Figure 10. Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz 1)
,'' :DLW +6,0+] P$
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1. Typical current consumption measured with code executed from RAM.
Figure 11. Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz 1)
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9'' 9
06 9
1. Typical current consumption measured with code executed from Flash.
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Electrical parameters STM8L052R8
In the following table, data are based on characterization results, unless otherwise
specified.
Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to
3.6 V
Symbol Parameter Conditions(1) Typ. Max. Unit
TA = -40 °C 5.86 6.38
to 25 °C
all peripherals OFF TA = 55 °C 6.52 7.06
LSI RC osc. TA = 85 °C 7.68 8.7
(at 38 kHz) TA = -40 °C 6.2 6.73
to 25 °C
with TIM2 active(2) TA = 55 °C 6.86 7.41
IDD(LPR) Supply current in Low TA = 85 °C 9.71 10.81 μA
power run mode TA = -40 °C 5.42 5.94
to 25 °C
all peripherals OFF TA = 55 °C 5.9 6.52
LSE (3) external TA = 85 °C 6.14 6.8
clock TA = -40 °C
(32.768 kHz) to 25 °C 5.87 6.48
with TIM2 active (2) TA = 55 °C 6.44 6.95
TA = 85 °C 6.7 7.65
1. No floating I/Os
2. Timer 2 clock enabled and counter running
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29
68/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 12. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF
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Electrical parameters STM8L052R8
In the following table, data are based on characterization results, unless otherwise
specified.
Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V
Symbol Parameter Conditions(1) Typ. Max. Unit
TA = -40 °C to 25 °C 3.03 3.41
all peripherals OFF TA = 55 °C 3.38 3.78
LSI RC osc. TA = 85 °C 4.6 5.34
(at 38 kHz) TA = -40 °C to 25 °C 3.78 4.21
with TIM2 active(2) TA = 55 °C 4.13 4.57
Supply current in TA = 85 °C 5.29 6.08
IDD(LPW) Low power wait TA = -40 °C to 25 °C 2.46 2.89 μA
mode
all peripherals OFF TA = 55 °C 2.58 3.07
LSE external TA = 85 °C 3.32 4.05
clock(3) TA = -40 °C to 25 °C 2.88 3.29
(32.768 kHz)
with TIM2 active (2) TA = 55 °C 2.97 3.42
TA = 85 °C 3.69 4.55
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29.
Figure 13. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF (1)
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1. Typical current consumption measured with code executed from RAM.
70/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
In the following table, data are based on characterization results, unless otherwise
specified.
Table 21. Total current consumption and timing in Active-halt mode
at VDD = 1.8 V to 3.6 V
Symbol Parameter Conditions(1) Typ. Max. Unit
TA = -40 °C to 25 °C 0.92 2.25
LCD OFF(2) TA = 55 °C 1.32 3.44
TA = 85 °C 1.63 3.87
LCD ON TA = -40 °C to 25 °C 1.56 3.6
(static duty/ TA = 55 °C 1.64 3.8
external
IDD(AH) Supply current in LSI RC VLCD) (3) TA = 85 °C 2.12 5.03
Active-halt mode (at 38 kHz) LCD ON TA = -40 °C to 25 °C 1.92 4.56 μA
(1/4 duty/ TA = 55 °C 2.1 4.97
external
VLCD) (4) TA = 85 °C 2.6 6.14
LCD ON TA = -40 °C to 25 °C 4.2 9.88
(1/4 duty/ TA = 55 °C 4.39 10.32
internal
VLCD) (5) TA = 85 °C 4.84 11.5
TA = -40 °C to 25 °C 0.54 1.35
LCD OFF(7) TA = 55 °C 0.61 1.44
TA = 85 °C 0.91 2.27
LCD ON TA = -40 °C to 25 °C 0.91 2.13
(static duty/ TA = 55 °C 1.05 2.55
LSE external external
IDD(AH) Supply current in clock VLCD) (3) TA = 85 °C 1.42 3.65
Active-halt mode (32.768 kHz) LCD ON TA = -40 °C to 25 °C 1.6 2.84 μA
(6) (1/4 duty/
external TA = 55 °C 1.76 4.37
VLCD) (4) TA = 85 °C 2.14 5.23
LCD ON TA = -40 °C to 25 °C 3.89 9.15
(1/4 duty/ TA = 55 °C 3.89 9.15
internal
VLCD) (5) TA = 85 °C 4.25 10.49
Supply current during
IDD(WUFAH) wakeup time from - - - 2.4 - mA
Active-halt mode
(using HSI)
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Electrical parameters STM8L052R8
Table 21. Total current consumption and timing in Active-halt mode
at VDD = 1.8 V to 3.6 V (continued)
Symbol Parameter Conditions(1) Typ. Max. Unit
tWU_HSI(AH)(8)(9) Wakeup time from
Active-halt mode to - - - 4.7 7 μs
Run mode (using HSI)
tWU_LSI(AH)(8)(9) Wakeup time from
Active-halt mode to - - - 150 - μs
Run mode (using LSI)
1. No floating I/O, unless otherwise specified.
2. RTC enabled. Clock source = LSI
3. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 29
7. RTC enabled. Clock source = LSE
8. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE
external crystal
Symbol Parameter Condition(1) Typ. Unit
VDD = 1.8 V LSE 1.2
LSE/32(3) 0.9
IDD(AH) (2) Supply current in Active-halt VDD = 3 V LSE 1.4 µA
mode LSE/32(3) 1.1
VDD = 3.6 V LSE 1.6
LSE/32(3) 1.3
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
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STM8L052R8 Electrical parameters
Figure 14. Typical IDD(AH) vs. VDD (LSI clock source)
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9'' 9
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Electrical parameters STM8L052R8
In the following table, data are based on characterization results, unless otherwise
specified.
Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V
Symbol Parameter Condition(1) Typ. Max. Unit
Supply current in Halt mode TA = -40 °C to 25 °C 400 1600(2)
IDD(Halt) (Ultra low power ULP bit =1 in TA = 55 °C 810 2400 nA
the PWR_CSR2 register) TA = 85 °C 1600 4500(2)
Supply current during wakeup
IDD(WUHalt) time from Halt mode (using - 2.4 - mA
HSI)
tWU_HSI(Halt)(3)(4) Wakeup time from Halt to Run - 4.7 7 µs
mode (using HSI)
tWU_LSI(Halt) (3)(4) Wakeup time from Halt mode - 150 - µs
to Run mode (using LSI)
1. TA = -40 to 85 °C, no floating I/O, unless otherwise specified
2. Tested in production
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
Figure 15. Typical IDD(Halt) vs. VDD (internal reference voltage OFF)
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74/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Current consumption of on-chip peripherals
Table 24. Peripheral current consumption
Symbol Parameter Typ. Unit
VDD = 3.0 V
IDD(ALL) Peripherals ON (1) 63
IDD(TIM1) TIM1 supply current(2) 10
IDD(TIM2) TIM2 supply current (2) 7
IDD(TIM3) TIM3 supply current (2) 7
IDD(TIM5) TIM5 supply current (2) 7
IDD(TIM4) TIM4 timer supply current (2) 3
IDD(USART1) USART1 supply current (3) 5
IDD(USART2) USART2 supply current (3) 5 µA/MHz
IDD(USART3) USART3 supply current (3) 5
IDD(SPI1) SPI1 supply current (3) 3
IDD(SPI2) SPI2 supply current (3) 3
IDD(I2C1) I2C1 supply current (3) 4
IDD(DMA1) DMA1 supply current 3
IDD(WWDG) WWDG supply current 1
IDD(ADC1) ADC1 supply current(4) 1500
IDD(PVD/BOR) Power voltage detector and brownout Reset unit supply 2.6
current (5)
IDD(BOR) Brownout Reset unit supply current (5) 2.4 µA
including LSI supply 0.45
IDD(IDWDG) Independent watchdog supply current current
excluding LSI 0.05
supply current
1. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1,
SPI2, I2C1, DMA1, WWDG.
2. Data based on ma oddifefeirnenbtoiathl IcDaDsmese.aNsourIeCm/OenCt between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait programmed, no I/O pins toggling. Not tested in production.
3. Data based on a differential cIDloDcmkeedaasunrdenmoetnktebpet tuwnedeenr the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
5. Including supply current of internal reference voltage.
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Electrical parameters STM8L052R8
Table 25. Current consumption under external reset
Symbol Parameter Conditions Typ. Unit
VDD = 1.8 V 48
IDD(RST) Supply current under PB1/PB3/PA5 pins are VDD = 3 V 80 µA
external reset (1) externally tied to VDD
VDD = 3.6 V 95
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
8.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 26. HSE external clock characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fHSE_ext(1) External clock source 1 - 16 MHz
frequency
VHSEH OSC_IN input pin high level - 0.7 x VDD - VDD
voltage V
VHSEL OSC_IN input pin low level VSS - 0.3 x VDD
voltage
Cin(HSE)(1) OSC_IN input capacitance - - 2.6 - pF
ILEAK_HSE OSC_IN input leakage VSS < VIN < VDD - - ±1 µA
current
1. Guaranteed by design.
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STM8L052R8 Electrical parameters
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 27. LSE external clock characteristics
Symbol Parameter Min. Typ. Max. Unit
fLSE_ext(1) External clock source frequency - 32.768 - kHz
VLSEH(2) OSC32_IN input pin high level voltage 0.7 x VDD - VDD
VLSEL(2) V
OSC32_IN input pin low level voltage VSS - 0.3 x VDD
Cin(LSE)(1) OSC32_IN input capacitance - 0.6 - pF
ILEAK_LSE OSC32_IN input leakage current - - ±1 µA
1. Guaranteed by design.
2. Guaranteed by characterization results.
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 28. HSE oscillator characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fHSE High speed external oscillator - 1 16 MHz
frequency
RF Feedback resistor - - 200 - kΩ
C(1)(2) Recommended load capacitance - - 20 - pF
C = 20 pF, - - 2.5 (startup)
0.7 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption fOSC = 16 MHz mA
C = 10 pF, - - 2.5 (startup)
0.46 (stabilized)(3)
fOSC =16 MHz
gm Oscillator transconductance - 3.5(3) - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 1 - ms
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Guaranteed by design.
4. tvSaUlu(HeSiEs) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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Electrical parameters STM8L052R8
Figure 16. HSE oscillator circuit diagram
Rm fHSE to core
CO RF
Lm
CL1
Cm OSC_IN gm
Resonator
Consumption
Resonator control
STM8
OSC_OUT
CL2
HSE oscillator critical gm formula
gmcrit = (2 × Π× fHSE)2 × Rm(2Co + C)2
Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),
Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 29. LSE oscillator characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fLSE Low speed external oscillator - - 32.768 - kHz
frequency
RF Feedback resistor ΔV = 200 mV - 1.2 - MΩ
C(1)(2) Recommended load capacitance - - 8 - pF
VDD = 1.8 V - 450 -
IDD(LSE) LSE oscillator power consumption VDD = 3 V - 600 - nA
VDD = 3.6 V - 750 -
gm Oscillator transconductance - 3(3) - - µA/V
tSU(LSE)(4) Startup time VDD is stabilized - 1 - s
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Guaranteed by design.
4. TtShUis(LvSaEl)uies the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
78/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 17. LSE oscillator circuit diagram
Rm fLSE
CO RF
Lm
CL1
Cm OSC_IN gm
Resonator
Consumption
Resonator control
STM8
OSC_OUT
CL2
Internal clock sources
Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 30. HSI oscillator characteristics
Symbol Parameter Conditions(1) Min. Typ. Max. Unit
fHSI Frequency VDD = 3.0 V - 16 MHz
Accuracy of HSI VDD = 3.0 V, TA = 25 °C -1 (2) - 1 (2) %
ACCHSI oscillator (factory 1.8 V ≤VDD ≤ 3.6 V, -5 - 5 %
calibrated) -40 °C ≤TA ≤ 85 °C
TRIM HSI user trimming Trimming code ≠ multiple of 16 - 0.4 0.7 %
step(3) Trimming code = multiple of 16 - ± 1.5 %
tsu(HSI) HSI oscillator setup - - 3.7 6 (4) µs
time (wakeup time)
IDD(HSI) HSI oscillator power - - 100 140(4) µA
consumption
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Tested in production.
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
4. Guaranteed by design.
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Electrical parameters STM8L052R8
Figure 18. Typical HSI frequency vs. VDD
Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production.
Table 31. LSI oscillator characteristics
Symbol Parameter Conditions(1) Min. Typ. Max. Unit
fLSI Frequency - 26 38 56 kHz
tsu(LSI) LSI oscillator wakeup time - - - 200(2) µs
D(LSI) LSI oscillator frequency 0 °C ≤TA ≤ 85 °C -12 - 11 %
drift(3)
1. VDD = 1.8 V to 3.6 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by design..
3. This is a deviation for an individual part, once the initial frequency has been measured.
80/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 19. Typical LSI clock source frequency vs. VDD
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8.3.5 Memory characteristics
TA = -40 to 85 °C unless otherwise specified.
Table 32. RAM and hardware registers
Symbol Parameter Conditions Min. Typ. Max. Unit
VRM Data retention mode (1) Halt mode (or Reset) 1.8 - - V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization results.
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Electrical parameters STM8L052R8
Flash memory
Table 33. Flash program and data EEPROM memory
Symbol Parameter Conditions Min. Typ. Max. Unit
(1)
VDD Operating voltage fSYSCLK = 16 MHz 1.8 - 3.6 V
(all modes, read/write/erase)
Programming time for 1 or 128 bytes (block) - - 6 - ms
tprog erase/write cycles (on programmed byte)
Programming time for 1 to 128 bytes (block) - - 3 - ms
write cycles (on erased byte)
Iprog Programming/ erasing consumption TA=+25 °C, VDD = 3.0 V - 0.7 - mA
TA=+25 °C, VDD = 1.8 V - -
Data retention (program memory) after 100 TRET=+85 °C 30(1) - -
tRET(2) erase/write cycles at TA=−40 to +85 °C years
Data retention (data memory) after 100000 TRET=+85 °C 30(1) - -
erase/write cycles at TA=−40 to +85 °C
Erase/write cycles (program memory) 100(1) - - cycles
NRW (3) Erase/write cycles (data memory) TA=−40 to +85 °C 100(1) - - kcycles
(4)
1. Guaranteed by characterization results.
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.
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STM8L052R8 Electrical parameters
8.3.6 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 34. I/O current injection susceptibility
Functional susceptibility
Symbol Description Negative Positive Unit
injection injection
Injected current on true open-drain pins -5 +0
IINJ Injected current on all 5 V tolerant (FT) pins -5 +0 mA
Injected current on any other pin -5 +5
8.3.7 I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
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Electrical parameters STM8L052R8
Table 35. I/O static characteristics
Symbol Parameter Conditions(1) Min. Typ. Max. Unit
Input voltage on true
open-drain pins (PC0 Vss-0.3 - 0.3 x VDD
and PC1)
VIL Input low level voltage(2) Input voltage on five- Vss-0.3 - 0.3 x VDD V
volt tolerant (FT) pins
Input voltage on any Vss-0.3 - 0.3 x VDD
other pin
Input voltage on true
open-drain pins (PC0 - 5.2
and PC1)
with VDD < 2 V 0.70 x VDD
Input voltage on true
open-drain pins (PC0 - 5.5
and PC1)
with VDD ≥ 2 V
VIH Input high level voltage (2) Input voltage on five- V
volt tolerant (FT) pins - 5.2
with VDD < 2 V 0.70 x VDD
Input voltage on five-
volt tolerant (FT) pins - 5.5
with VDD ≥ 2 V
Input voltage on any 0.70 x VDD - VDD+0.3
other pin
Vhys Schmitt trigger voltage hysteresis (3) Standard I/Os - 200 - mV
True open drain I/Os - 200 -
VSS≤VIN≤VDD - - 50 (5)
Standard I/Os
Input leakage current (4) VSS≤VIN≤VDD - - 200(5)
Ilkg True open drain I/Os nA
VSS≤VIN≤VDD 200(5)
PA0 with high sink LED - -
driver capability
RPU Weak pull-up equivalent VIN=VSS 30 45 60 kΩ
resistor(2)(6)
CIO I/O pin capacitance - - 5 - pF
1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RFiPgUurpeu2ll3-u).p equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
84/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 20. Typical VIL and VIH vs. VDD (standard I/Os)
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9''>9@
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Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os)
&
&
&
9,/DQG9,+>9@
9''>9@
DL9
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Electrical parameters STM8L052R8
Figure 22. Typical pull-up resistance RPU vs. VDD with VIN=VSS
&
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3XOO8SUHVLVWDQFH>N7@ &
9''>9@
DL9
Figure 23. Typical pull-up current Ipu vs. VDD with VIN=VSS
&
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&
3XOO8SFXUUHQW>$@
9''>9@
DL9
Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
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STM8L052R8 Electrical parameters
Table 36. Output driving current (high sink ports)
I/O Symbol Parameter Conditions Min. Max. Unit
Type
IIO = +2 mA, - 0.45 V
VDD = 3.0 V
VOL (1) Output low level voltage for an I/O pin IIO = +2 mA, - 0.45 V
VDD = 1.8 V
Standard IIO = +10 mA, - 0.7 V
VDD = 3.0 V
IIO = -2 mA, VDD-0.45 - V
VDD = 3.0 V
VOH (2) Output high level voltage for an I/O pin IIO = -1 mA, VDD-0.45 - V
VDD = 1.8 V
IIO = -10 mA, VDD-0.7 - V
VDD = 3.0 V
1. TofhIeIOIIO(I/Ocuprroerntst sunk must always respect the absolute maximum rating specified in Table 13 and the sum
and control pins) must not exceed IVSS.
2. The IoIOf current sourced must always respect the absolute maximum rating specified in Table 13 and the
sum IIO (I/O ports and control pins) must not exceed IVDD.
Table 37. Output driving current (true open drain ports)
I/O Symbol Parameter Conditions Min. Max. Unit
Type
Open drain IIO = +3 mA, - 0.45
VOL (1) Output low level voltage for an I/O pin VDD = 3.0 V V
IIO = +1 mA, - 0.45
VDD = 1.8 V
1. TofhIeIOIIO(I/Ocuprroerntst sunk must always respect the absolute maximum rating specified in Table 13 and the sum
and control pins) must not exceed IVSS.
Table 38. Output driving current (PA0 with high sink LED driver capability)
I/O Symbol Parameter Conditions Min. Max. Unit
Type
IR VOL (1) Output low level voltage for an I/O pin IIO = +20 mA, - 0.45 V
VDD = 2.0 V
1. TofhIeIOIIO(I/Ocuprroerntst sunk must always respect the absolute maximum rating specified in Table 13 and the sum
and control pins) must not exceed IVSS.
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Electrical parameters STM8L052R8
Figure 24. Typical VOL @ VDD = 3.0 V (high sink Figure 25. Typical VOL @ VDD = 1.8 V (high sink
ports) ports)
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& &
92/>9@ 92/>9@
,2/>P$@ DL9 ,2/>P$@
DL9
Figure 26. Typical VOL @ VDD = 3.0 V (true open Figure 27. Typical VOL @ VDD = 1.8 V (true open
drain ports) drain ports)
&
&
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& &
&
92/>9@ 92/>9@
,2/>P$@ ,2/>P$@
DL9 BJ7
Figure 28. Typical VDD - VOH @ VDD = 3.0 V (high Figure 29. Typical VDD - VOH @ VDD = 1.8 V (high
sink ports) sink ports)
&
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9''92+>9@ & 9''92+>9@
,2+>P$@ ,2+>P$@
DL9 BJ7
NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.
88/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Table 39. NRST pin characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VIL(NRST) NRST input low level voltage (1) - VSS - 0.8
VIH(NRST) NRST input high level voltage (1) - 1.4 - VDD
IOL = 2 mA - - V
VOL(NRST) NRST output low level voltage (1) for 2.7 V ≤VDD ≤ 3.6 V
IOL = 1.5 mA 0.4
for VDD < 2.7 V - -
VHYST NRST input hysteresis(3) - 10%VDD - - mV
(2)
RPU(NRST) NRST pull-up equivalent - 30 45 60 kΩ
resistor(1)
VF(NRST) NRST input filtered pulse (3) - - - 50
VNF(NRST) NRST input not filtered pulse (3) ns
- 300 - -
1. Guaranteed by characterization results.
2. 200 mV min.
3. Guaranteed by design.
Figure 30. Typical NRST pull-up resistance RPU vs. VDD
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3XOOXS UHVLVWDQFH >N7@ &
9''>9@
DL9
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Electrical parameters STM8L052R8
Figure 31. Typical NRST pull-up current Ipu vs. VDD
&
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9''>9@
DL9
The reset network shown in Figure 32 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 39. Otherwise the reset is not taken into account internally. For power consumption-
sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF.
90/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 32. Recommended NRST pin configuration
VDD
RPU
EXTERNAL RSTIN Filter INTERNAL RESET
RESET
CIRCUIT
0.1 µF STM8L
Doc ID023337 Rev 3 91/112
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Electrical parameters STM8L052R8
8.3.8 Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 8.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI1 characteristics
Symbol Parameter Conditions(1) Min. Max. Unit
fSCK SPI1 clock frequency Master mode 0 8
1/tc(SCK) Slave mode 0 8 MHz
tr(SCK) SPI1 clock rise and fall Capacitive load: C = 30 pF - 30 ns
tf(SCK) time
tsu(NSS)(2) NSS setup time Slave mode 4 x 1/fSYSCLK - -
th(NSS)(2) NSS hold time Slave mode 80 - -
ttww((SSCCKKHL))((22)) SCK high and low time Master mode, 105 145 -
fMASTER = 8 MHz, fSCK= 4 MHz
ttssuu((MSII))((22)) Data input setup time Master mode 30 - -
Slave mode 3 - -
tthh((MSII))((22)) Data input hold time Master mode 15 - -
Slave mode 0 - -
ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK -
tdis(SO)(2)(4) Data output disable time Slave mode 30 - -
tv(SO) (2) Data output valid time Slave mode (after enable edge) - 60 -
tv(MO)(2) Data output valid time Master mode (after enable - 20 -
edge)
th(SO)(2) Slave mode (after enable edge) 15 - -
th(MO)(2) Data output hold time Master mode (after enable 1 - -
edge)
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
92/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 33. SPI1 timing diagram - slave mode and CPHA=0
.33 INPUT
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Doc ID023337 Rev 3 93/112
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Electrical parameters STM8L052R8
Figure 35. SPI1 timing diagram - master mode(1)
(IGH
.33 INPUT
TC3#+
3#+ OUTPUT #0(!
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
94/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
I2C - Inter IC control interface
Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 41. I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol Parameter Unit
Min.(2) Max. (2) Min. (2) Max. (2)
tw(SCLL) SCL clock low time 4.7 - 1.3 - μs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time 0 - 0 900
tr(SDA) SDA and SCL rise time - 1000 - 300 ns
tr(SCL)
tf(SDA) SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) START condition hold time 4.0 - 0.6 -
tsu(STA) Repeated START condition setup 4.7 - 0.6 - μs
time
tsu(STO) STOP condition setup time 4.0 - 0.6 - μs
tw(STO:STA) STOP to START condition time (bus 4.7 - 1.3 - μs
free)
Cb Capacitive load for each bus line - 400 - 400 pF
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
Note: For speeds around 200 kHz, the achieved speed can have a ± 5% tolerance.
For other speed ranges, the achieved speed can have a ± 2% tolerance.
The above variations depend on the accuracy of the external components used.
Doc ID023337 Rev 3 95/112
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Electrical parameters STM8L052R8
Figure 36. Typical application with I2C bus and timing diagram 1)
VDD VDD
4.7kΩ 4.7kΩ 100Ω SDA
I2C BUS 100Ω SCL
STM8L REPEATED START
START
tsu(STA) tw(STO:STA) START
SDA
tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP
SCL
th(STA) tw(SCLH) tw(SCLL) tr(SCL) tf(SCL) tsu(STO)
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
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STM8L052R8 Electrical parameters
8.3.9 LCD controller
In the following table, data are guaranteed by design, not tested in production.
Table 42. LCD characteristics
Symbol Parameter Min. Typ. Max. Unit
VLCD LCD external voltage - - 3.6
VLCD0 LCD internal reference voltage 0 - 2.6 -
VLCD1 LCD internal reference voltage 1 - 2.7 -
VLCD2 LCD internal reference voltage 2 - 2.8 -
VLCD3 LCD internal reference voltage 3 - 3.0 - V
VLCD4 LCD internal reference voltage 4 - 3.1 -
VLCD5 LCD internal reference voltage 5 - 3.2 -
VLCD6 LCD internal reference voltage 6 - 3.4 -
VLCD7 LCD internal reference voltage 7 - 3.5 -
CEXT VLCD external capacitance 0.1 1 2 µF
IDD Supply current(1) at VDD = 1.8 V - 3 - µA
Supply current(1) at VDD = 3 V - 3 -
RHN(2) High value resistive network (low drive) - 6.6 - MΩ
RLN(3) Low value resistive network (high drive) - 240 - kΩ
V33 Segment/Common higher level voltage - - VLCDx
V34 Segment/Common 3/4 level voltage - 3/4VLCDx -
V23 Segment/Common 2/3 level voltage - 2/3VLCDx -
V12 Segment/Common 1/2 level voltage - 1/2VLCDx - V
V13 Segment/Common 1/3 level voltage - 1/3VLCDx -
V14 Segment/Common 1/4 level voltage - 1/4VLCDx -
V0 Segment/Common lowest level voltage 0 - -
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.
VLCD external capacitor
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 42.
Doc ID023337 Rev 3 97/112
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Electrical parameters STM8L052R8
8.3.10 Embedded reference voltage
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 43. Reference voltage characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
IREFINT Internal reference voltage - - 1.4 - µA
consumption
TS_VREFINT(1)(2) ADC sampling time when reading the - - 5 10 µs
internal reference voltage
IBUF(1) Internal reference voltage buffer - - 13.5 25 µA
consumption (used for ADC)
VREFINT out Reference voltage output - 1.202 1.224 1.242 V
(3) (3)
ILPBUF(1) Internal reference voltage low power
buffer consumption (used for - - 730 1200 nA
comparators or output)
IREFOUT(1)(4) Buffer output current - - - 1 µA
CREFOUT Reference voltage output load - - - 50 pF
tVREFINT(1) Internal reference voltage startup - - 2 3 ms
time
tBUFEN(1)(2) Internal reference voltage buffer - - - 10 µs
startup time once enabled
STABVREFINT Stability of VREFINT over temperature -40 °C ≤TA ≤ 85 °C - 20 50 ppm/°C
Stability of VREFINT over temperature 0 °C ≤TA ≤ 50 °C - - 20 ppm/°C
STABVREFINT Stability of VREFINT after 1000 hours - - - TBD ppm
1. Guaranteed by design.
2. Defined when ADC output reaches its final value ±1/2LSB
3. Tested in production at VDD = 3 V ±10 mV.
4. To guarantee less than 1% VREFOUT deviation
98/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
8.3.11 12-bit ADC1 characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 44. ADC1 characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDA Analog supply voltage - 1.8 - 3.6 V
VREF+ Reference supply 2.4 V ≤VDDA≤ 3.6 V 2.4 - VDDA V
voltage 1.8 V≤VDDA≤ 2.4 V VDDA V
VREF- Lower reference voltage - VSSA V
IVDDA Current on the VDDA - - 1000 1450 µA
input pin
- - 700 µA
IVREF+ Current on the VREF+ 400 (peak)(1)
input pin - - 450 µA
(average)(1)
VAIN Conversion voltage - 0(2) - VREF+ -
range
TA Temperature range - -40 - 85 °C
External resistance on on PF0/1/2/3 fast - -
RAIN VAIN channels 50(3) kΩ
on all other channels - -
Internal sample and hold on PF0/1/2/3 fast - -
CADC capacitor channels 16 pF
on all other channels - -
2.4 V≤VDDA≤3.6 V 0.320 - 16 MHz
fADC ADC sampling clock without zooming
frequency 1.8 V≤VDDA≤2.4 V 0.320 - 8 MHz
with zooming
VAIN on PF0/1/2/3 fast - - 1(3)(4) MHz
channels
fCONV 12-bit conversion rate
VAIN on all other
channels - - 760(3)(4) kHz
fTRIG External trigger - - - tconv 1/fADC
frequency
tLAT External trigger latency - - - 3.5 1/fSYSCLK
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Electrical parameters STM8L052R8
Table 44. ADC1 characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
VAIN PF0/1/2/3 fast 0.43(3)(4) - - µs
channels
VDDA < 2.4 V
VAIN PF0/1/2/3 fast 0.22(3)(4) - - µs
channels
tS Sampling time
2.4 V ≤VDDA≤ 3.6 V
VAIN on slow channels 0.86(3)(4) - - µs
VDDA < 2.4 V
VAIN on slow channels 0.41(3)(4) - - µs
2.4 V ≤VDDA≤ 3.6 V
tconv 12-bit conversion time - 12 + tS 1/fADC
16 MHz 1(3) µs
tWKUP Wakeup time from OFF - - - 3 µs
state
tIDLE(5) Time before a new - - - ∞ s
conversion
tVREFINT Internal reference - - - refer to ms
voltage startup time Table 43
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- must be tied to ground.
3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 kΩ..
4. Value obtained for continuous conversion on fast channel.
5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.
100/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
In the following three tables, data are guaranteed by characterization result, not tested in
production.
Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V
Symbol Parameter Conditions Typ. Max. Unit
fADC = 16 MHz 1 1.6
DNL Differential non linearity fADC = 8 MHz 1 1.6
fADC = 4 MHz 1 1.5
fADC = 16 MHz 1.2 2
INL Integral non linearity fADC = 8 MHz 1.2 1.8 LSB
fADC = 4 MHz 1.2 1.7
fADC = 16 MHz 2.2 3.0
TUE Total unadjusted error fADC = 8 MHz 1.8 2.5
fADC = 4 MHz 1.8 2.3
fADC = 16 MHz 1.5 2
Offset Offset error fADC = 8 MHz 1 1.5
fADC = 4 MHz 0.7 1.2 LSB
fADC = 16 MHz
Gain Gain error fADC = 8 MHz 1 1.5
fADC = 4 MHz
Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V
Symbol Parameter Typ. Max. Unit
DNL Differential non linearity 1 2 LSB
INL Integral non linearity 1.7 3 LSB
TUE Total unadjusted error 2 4 LSB
Offset Offset error 1 2 LSB
Gain Gain error 1.5 3 LSB
Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V
Symbol Parameter Typ. Max. Unit
DNL Differential non linearity 1 2 LSB
INL Integral non linearity 2 3 LSB
TUE Total unadjusted error 3 5 LSB
Offset Offset error 2 3 LSB
Gain Gain error 2 3 LSB
Doc ID023337 Rev 3 101/112
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Electrical parameters STM8L052R8
Figure 37. ADC1 accuracy characteristics
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1. Refer to Table 44 for the values of RAIN and CADC.
2. pCapdaracsaitpicarceitparnecseen(rtsouthgehlcya7papcFi)ta. nAcheigohf the PCB (dependent on soldering and PCB layout quality) plus the
Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 39 or Figure 40,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
102/112 Doc ID023337 Rev 3
STM8L052R8 Electrical parameters
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA)
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Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA)
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