STM8L052R8
Value Line, 8-bit ultralow power MCU, 64-KB Flash,
256-byte data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC
Datasheet - production data
Features
• Operating conditions
– Operating power supply: 1.8 V to 3.6 V
– Temperature range: -40 °C to 85 °C
• Low power features
– 5 low power modes: Wait, Low power run LQFP64
(5.9 µA), Low power wait (3 µA), Active-halt
with full RTC (1.4 µA), Halt (400 nA) • DMA
– Dynamic power consumption: – 4 channels supporting ADC, SPIs, I2C,
200 µA/MHz + 330 µA USARTs, timers
– Ultra-low leakage per I/0: 50 nA – 1 channel for memory-to-memory
– Fast wakeup from Halt: 4.7 µs • 12-bit ADC up to 1 Msps/27 channels
• Advanced STM8 core – Internal reference voltage
– Harvard architecture and 3-stage pipeline • Timers
– Max freq. 16 MHz, 16 CISC MIPS peak – Three 16-bit timers with 2 channels (used
– Up to 40 external interrupt sources as IC, OC, PWM), quadrature encoder
• Reset and supply management – One 16-bit advanced control timer with 3
– Low power, ultra-safe BOR reset with 5 channels, supporting motor control
programmable thresholds – One 8-bit timer with 7-bit prescaler
– Ultra low power POR/PDR – 2 watchdogs: 1 Window, 1 Independent
– Programmable voltage detector (PVD) – Beeper timer with 1, 2 or 4 kHz frequencies
• Clock management • Communication interfaces
– 32 kHz and 1 to 16 MHz crystal oscillators – Two synchronous serial interfaces (SPI)
– Internal 16 MHz factory-trimmed RC – Fast I2C 400 kHz SMBus and PMBus
– 38 kHz low consumption RC – Three USARTs (ISO 7816 interface + IrDA)
– Clock security system • Up to 54 I/Os, all mappable on interrupt vectors
• Low power RTC • Development support
– BCD calendar with alarm interrupt – Fast on-chip programming and non-
– Digital calibration with +/- 0.5ppm accuracy intrusive debugging with SWIM
– Advanced anti-tamper detection – Bootloader using USART
• LCD: 8x24 or 4x28 w/ step-up converter
• Memories
– 64 KB Flash program memory and 256
bytes data EEPROM with ECC, RWW
– Flexible write and read protection modes
– 4 KB of RAM
February 2017 Doc ID023337 Rev 3 1/112
This is information on a product in full production. www.st.com
Contents STM8L052R8
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Central processing unit STM8 ................................. 14
3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Reset and supply management ................................ 15
3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Low power real-time clock .................................... 17
3.6 LCD (Liquid crystal display) ................................... 18
3.7 Memories ................................................. 18
3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Analog-to-digital converter .................................... 19
3.10 System configuration controller and routing interface ............... 19
3.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.1 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Beeper ................................................... 21
3.14 Communication interfaces .................................... 21
3.14.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/112 Doc ID023337 Rev 3
STM8L052R8 Contents
3.14.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 System configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Memory mapping ........................................... 31
5.2 Register map .............................................. 32
6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3.2 Embedded reset and power control block characteristics . . . . . . . . . . 60
8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.3.9 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.11 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.4 Thermal characteristics ..................................... 106
Doc ID023337 Rev 3 3/112
4
Contents STM8L052R8
9 Package characteristics . . . . . . . . . . . . . . . . . . .... . . . . . . . . . . . . . . 107
9.1 Package mechanical data ........ . . . . . . . ..... . . . . . . . . . . . . . . . 107
10 Ordering information scheme ...... . . . . . . . .... . . . . . . . . . . . . . . 110
11 Revision history ................. . . . . . . . .... . . . . . . . . . . . . . . 111
4/112 Doc ID023337 Rev 3
STM8L052R8 List of tables
List of tables
Table 1. High density value line STM8L05xxx low power device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Legend/abbreviation for Table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. High density value line STM8L05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 16. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 18. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 19. Total current consumption and timing in Low power run mode at VDD = 1.8 V to
3.6 V ............................................................... . . 68
Table 20. Total current consumption in Low power wait mode at VDD = 1.8 V to 3.6 V . . . . . . . . . . 70
Table 21. Total current consumption and timing in Active-halt mode
at VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 22. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 72
Table 23. Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V . . . . . . . . . . . . 74
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 25. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 26. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 27. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 32. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 33. Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 36. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 38. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 87
Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 40. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 41. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 42. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 43. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 44. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 45. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Doc ID023337 Rev 3 5/112
6
List of tables STM8L052R8
Table 46. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 47. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 48. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 49. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 53. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 108
Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6/112 Doc ID023337 Rev 3
STM8L052R8 List of figures
List of figures
Figure 1. High density value line STM8L05xxx device block diagram .......... . . .... .. . . . . 12
Figure 2. High density value line STM8L05xxx clock tree diagram ............. . . .... .. . . . . 17
Figure 3. STM8L052R8 64-pin LQFP64 package pinout ..................... . . .... .. . . . . 23
Figure 4. Memory map ............................................... . . .... .. . . . . 31
Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 56
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 57
Figure 7. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 62
RFRFlAlAaaMsMshhvv(vsHss..S.VVVIDDcDDDlDo((cH(HHkSSSsIIoIccuclloroloccceckkk),sssofoCouuPurrUcrccee=e)),),1,ff6CfCCPPMPUUUH===z111166)6.MMM.HH.Hz.zz.111.)))...
Figure 8. Typical IDD(RUN) from . . .... .. . . . . 65
Figure 9. Typical IDD(RUN) from . . .... .. . . . . 65
Figure 10. Typical IDD(Wait) from . . .... .. . . . . 67
Figure 11. Typical IDD(Wait) from . . .... .. . . . . 67
Figure 12. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . .... .. . . . . 69
source), all peripherals OFF (1)
Figure 13. Typical IDD(LPW) vs. VDD (LSI clock . . . . . . . .... .. . . . . 70
Figure 14. Typical IDD(AH) vs. VDD (LSI clock source) ....................... . . .... .. . . . . 73
Figure 15. Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . .... .. . . . . 74
Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 78
Figure 17. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 79
Figure 18. Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 80
Figure 19. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 81
Figure 20. Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 85
Figure 21. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . .... .. . . . . 85
Figure 22. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . .... .. . . . . 86
Figure 23. Typical pull-up current Ipu vs. VDD with VIN=VSS ................... . . .... .. . . . . 86
Figure 24. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 25. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 26. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 27. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 28. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 29. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . .... .. . . . . 88
Figure 30. Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 89
Figure 31. Typical NRST pull-up current Ipu vs. VDD ......................... . . .... .. . . . . 90
Figure 32. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 91
Figure 33. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 93
SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . .
Figure 34. SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . 93
Figure 35. . . .... .. . . . . 94
Figure 36. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . .... .. . . . . 96
Figure 37. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 102
Figure 38. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 102
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . .... .. . . . 103
Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . .... .. . . . 103
Figure 41. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . .... .. . . . 108
Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 109
Figure 43. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . 110
Doc ID023337 Rev 3 7/112
7
Introduction STM8L052R8
1 Introduction
This document describes the features, pinout, mechanical data and ordering information of
the high density value line STM8L052R8 microcontroller with a Flash memory density of
64 Kbytes.
For further details on the whole STMicroelectronics high density family please refer to
Section 2.2: Ultra low power continuum.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
High density value line devices provide the following benefits:
• Integrated system
– 64 Kbytes of high density embedded Flash program memory
– 256 bytes of data EEPROM
– 4 Kbytes of RAM
– Internal high speed and low-power low speed RC
– Embedded reset
• Ultra low power consumption
– 1 µA in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low power wait mode and low power run
mode
• Advanced features
– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access
• Short development cycles
– Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals
– Wide choice of development tools
These features make the value line STM8L05xxx ultra low power microcontroller family
suitable for a wide range of consumer and mass market applications.
Refer to Table 1: High density value line STM8L05xxx low power device features and
peripheral counts and Section 3: Functional overview for an overview of the complete range
of peripherals proposed in this family.
Figure 1 shows the block diagram of the high density value line STM8L05xxx family.
8/112 Doc ID023337 Rev 3
STM8L052R8 Description
2 Description
The high density value line STM8L05xxx devices are members of the STM8L ultra low
power 8-bit family.
The value line STM8L05xxx ultra low power family features the enhanced STM8 CPU core
providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive In-application debugging and ultra-fast Flash programming.
High density value line STM8L05xxx microcontrollers feature embedded data EEPROM and
low-power, low-voltage, single-supply program Flash memory.
All devices offer 12-bit ADC, real-time clock, four 16-bit timers, one 8-bit timer as well as
standard communication interface such as two SPIs, I2C, three USARTs and 8x24 or 4x28-
segment LCD. The 8x24 or 4x 28-segment LCD is available on the high density value line
STM8L05xxx.
The STM8L05xxx family operates from 1.8 V to 3.6 V and is available in the -40 to +85 °C
temperature range.
The modular design of the peripheral set allows the same peripherals to be found in
different ST microcontroller families including 32-bit families. This makes any transition to a
different family very easy, and simplified even more by the use of a common set of
development tools.
All value line STM8L ultra low power products are based on the same architecture with the
same memory mapping and a coherent pinout.
Doc ID023337 Rev 3 9/112
52
Description STM8L052R8
2.1 Device overview
Table 1. High density value line STM8L05xxx low power device features and
peripheral counts
Features STM8L052R8
Flash (Kbytes) 64
Data EEPROM (bytes) 256
RAM (Kbytes) 4
LCD 8x24 or 4x28
Basic 1
(8-bit)
Timers General purpose 3
(16-bit)
Advanced control 1
(16-bit)
SPI 2
Communication I2C 1
interfaces
USART 3
GPIOs 54(1)
12-bit synchronized ADC 1
(number of channels) (26)
RTC, window watchdog, independent watchdog,
Others 16-MHz and 38-kHz internal RC,
1- to 16-MHz and 32-kHz external oscillator
CPU frequency 16 MHz
Operating voltage 1.8 V to 3.6 V
Operating temperature -40 to +85 °C
Package LQFP64
1. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the
NRST/PA1 pin as general purpose output only (PA1).
10/112 Doc ID023337 Rev 3
STM8L052R8 Description
2.2 Ultra low power continuum
The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin-to-pin, software
and feature compatible. Besides the full compatibility within the STM8L family, the devices
are part of STMicroelectronics microcontrollers ultra low power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm ultra-low leakage process.
Note: 1 The STM8L05xxx is pin-to-pin compatible with STM8L101xx devices.
2 The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15x documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra low power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L05x, STM8L15x and STM32L15xx share identical peripherals which ensure a very
easy migration from one family to another:
• Analog peripheral: ADC1
• Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L and STM32L devices use a
common architecture:
• Same power supply range from 1.8 to 3.6 V
• Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
• Fast startup strategy from low power modes
• Flexible system clock
• Ultra-safe reset: same reset strategy for both STM8L and STM32L including power-on
reset, power-down reset, brownout reset and programmable voltage detector
Features
ST ultra low power continuum also lies in feature compatibility:
• More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
• Memory density ranging from 4 to 128 Kbytes
Doc ID023337 Rev 3 11/112
52
Functional overview STM8L052R8
3 Functional overview
Figure 1. High density value line STM8L05xxx device block diagram
/3#?).
-(Z OSCILLATOR 6$$
/3#?/54 6$$ 0 OWER 6$$ 6
-(Z INTERNAL 2# #LOCK 633 TO 6
/3#?). CONTROLLER 6/,4 2%'
/3#?/54 K(Z OSCILLATOR AND #33 #LOCKS
K(Z INTERNAL 2# TO CORE AND
PERIPHERALS 2%3%4 .234
)NTERRUPT CONTROLLER
34- #ORE 0/20$2
37)- $EBUG MODULE "/2
37)-
CHANNELS 06$ 06$?).
BIT 4IMER
CHANNELS
BIT 4IMER
UP TO
CHANNELS
BIT 4IMER
+BYTE
! D D RESS CO N T ROL AN D D AT A B U SES 0ROGRAM MEMORY
BIT 4IMER BYTES
CHANNELS
BIT 4IMER $ATA %%02/-
)2?4)- )NFRARED INTERFACE UP TO
$-! CHANNELS
+BYTE 2!-
3#, 3$! )£# 0ORT ! 0!;=
3-"
30)?-/3) 30)?-)3/ 30) 0ORT " 0";=
30)?3#+ 30)?.33 0#;=
30)?-/3) 30)?-)3/ 30) 0ORT #
30)?3#+ 30)?.33 0ORT $ 0$;=
53!24?28 53!24?48 53!24
53!24?#+ 0ORT % 0%;=
53!24?28 53!24?48 53!24
53!24?#+ 0ORT & 0&;=
53!24?28 53!24?48 53!24
53!24?#+ 0ORT ' 0';=
6$$! 633! 6 $$! 6 33! "EEPER "%%0
!$#?).X
BIT !$# 24# !,!2- #!,)"
62%& 4!-0
62%&
)7$'
K(Z CLOCK
62%&).4 OUT )NTERNAL REFERENCE 77$'