STM32F303xB STM32F303xC
ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+
48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V
Datasheet - production data
Features
• Core: ARM® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and LQFP48 (7 × 7 mm)
HW division, 90 DMIPS (from CCM), DSP LQFP64 (10 × 10 mm) WLCSP100 (0.4 mm pitch)
instruction and MPU (memory protection unit) LQFP100 (14 × 14 mm)
• Operating conditions: • Up to 13 timers
– VDD, VDDA voltage range: 2.0 V to 3.6 V – One 32-bit timer and two 16-bit timers with
• Memories up to 4 IC/OC/PWM or pulse counter and
– 128 to 256 Kbytes of Flash memory quadrature (incremental) encoder input
– Up to 40 Kbytes of SRAM, with HW parity – Two 16-bit 6-channel advanced-control
check implemented on the first 16 Kbytes. timers, with up to 6 PWM channels,
– Routine booster: 8 Kbytes of SRAM on deadtime generation and emergency stop
instruction and data bus, with HW parity – One 16-bit timer with 2 IC/OCs, 1
check (CCM) OCN/PWM, deadtime generation and
• CRC calculation unit emergency stop
• Reset and supply management – Two 16-bit timers with IC/OC/OCN/PWM,
– Power-on/Power-down reset (POR/PDR) deadtime generation and emergency stop
– Programmable voltage detector (PVD) – Two watchdog timers (independent, window)
– Low-power modes: Sleep, Stop and Standby – SysTick timer: 24-bit downcounter
– VBAT supply for RTC and backup registers – Two 16-bit basic timers to drive the DAC
• Clock management • Calendar RTC with Alarm, periodic wakeup
– 4 to 32 MHz crystal oscillator from Stop/Standby
– 32 kHz oscillator for RTC with calibration • Communication interfaces
– Internal 8 MHz RC with x 16 PLL option – CAN interface (2.0B Active)
Two I2C Fast mode plus (1 Mbit/s) with
– Internal 40 kHz oscillator –
• Up to 87 fast I/Os 20 mA current sink, SMBus/PMBus, wakeup
– All mappable on external interrupt vectors from STOP
– Several 5 V-tolerant – Up to five USART/UARTs (ISO 7816
• Interconnect matrix interface, LIN, IrDA, modem control)
• 12-channel DMA controller – Up to three SPIs, two with multiplexed
Four ADCs 0.20 µS (up to 39 channels) with half/full duplex I2S interface, 4 to 16
• programmable bit frames
selectable resolution of 12/10/8/6 bits, 0 to – USB 2.0 full speed interface
3.6 V conversion range, single – Infrared transmitter
ended/differential input, separate analog supply • Serial wire debug, Cortex®-M4 with FPU ETM,
from 2 to 3.6 V JTAG
• Two 12-bit DAC channels with analog supply • 96-bit unique ID
from 2.4 to 3.6 V
• Seven fast rail-to-rail analog comparators with Table 1. Device summary
analog supply from 2 to 3.6 V Reference Part number
• Four operational amplifiers that can be used in
PGA mode, all terminals accessible with analog STM32F303xB STM32F303CB, STM32F303RB, STM32F303VB
supply from 2.4 to 3.6 V STM32F303xC STM32F303CC, STM32F303RC, STM32F303VC
• Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
May 2016 DocID023353 Rev 13 1/148
This is information on a product in full production. www.st.com
Contents STM32F303xB STM32F303xC
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . 13
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Embedded Flash memory .................................... 13
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Boot modes ............................................... 14
3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.2 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Clocks and startup .......................................... 17
3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Interrupts and events ........................................ 19
3.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Operational amplifier (OPAMP) ................................ 21
3.16 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 23
3.17.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Real-time clock (RTC) and backup registers ...................... 24
3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 26
3.21 Universal asynchronous receiver transmitter (UART) ............... 26
3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 27
3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.25 Infrared Transmitter ......................................... 28
3.26 Touch sensing controller (TSC) ................................ 28
3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.27.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 60
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6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.5 Supply current characteristics ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.9 PLL characteristics ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.10 Memory characteristics .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.16 Timer characteristics ............ . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.17 Communications interfaces ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.20 Comparator characteristics ....... . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.23 VBAT monitoring characteristics .... . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1 LQFP100 – 14 x 14 mm, low-profile quad flat package
information ............................................... 125
7.2 LQFP64 – 10 x 10 mm, low-profile quad flat package
information ............................................... 128
7.3 LQFP48 – 7 x 7 mm, low-profile quad flat package
information ............................................... 131
7.4 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 134
7.5 Thermal characteristics ..................................... 138
7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 139
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 11
Table 3. External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F303xB/STM32F303xC I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7.
Table 8. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 29
Table 11. No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices . 29
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. STM32F303xB/STM32F303xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 15. Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16. Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 18. Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19. Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 53
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 63
Table 31. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 64
Table 32. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 65
Table 33. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 65
Table 34. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 66
Table 35. Typical current consumption in Run mode, code with data processing running from Flash 67
Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 68
Table 37. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 38. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 43. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 44. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 45. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 46. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 48. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 55. Output voltage characteristics ................................... . . . . . . . . . . . 89
Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 59. IWDG min/max timeout period at 40 kHz (LSI) ...................... . . . . . . . . . . . 93
Table 60. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 61. I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 94
Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 64. . . . . . . . . . . . 99
Table 65. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 66. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 67. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 68. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 69. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 70. ADC accuracy - limited test conditions, 100-pin packages ............. . . . . . . . . . . 108
Table 71. ADC accuracy, 100-pin packages ................................ . . . . . . . . . . 110
Table 72. ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 73. ADC accuracy, 64-pin packages ................................. . . . . . . . . . . 114
Table 74. ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 75. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 76. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 77. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 78. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 80. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 125
Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 128
Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 131
Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 136
Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 87. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 88. Document revision history ...................................... . . . . . . . . . . 142
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STM32F303xB STM32F303xC List of figures
List of figures
Figure 1. STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 18
Figure 3. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 28
Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout ....................... . . .. . . . . 31
Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout ....................... . . .. . . . . 32
Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout ....................... . . .. . . . . 33
Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 34
Figure 8. STM32F303xB/STM32F303xC memory map .......................... . . .. . . . . 52
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 55
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 55
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 56
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 57
Figure 13. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . .. . . . . 66
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . .. . . . . 74
Figure 15. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 75
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 77
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 79
Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . .. . . . . 80
Figure 19. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 87
Figure 20. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 87
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . .. . . . . 88
Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . .. . . . . 88
Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 91
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 92
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. . . .. . . . . 95
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 97
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . .
Figure 27. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 97
Figure 28. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 98
Figure 29. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 100
Figure 30. . . .. . . . 100
Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . .. . . . 101
Figure 32. ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 106
Figure 33. ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 106
Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 116
Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 116
Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 118
Figure 37. Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . .. . . . 120
Figure 38. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 123
Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . .. . . . 125
Figure 40. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . .. . . . 126
Figure 41. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . .. . . . 127
Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline .............. . . .. . . . 128
Figure 43. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . .. . . . 129
Figure 44. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . .. . . . 130
Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . .. . . . 131
Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . .. . . . 132
Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . .. . . . 133
Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
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8
List of figures STM32F303xB STM32F303xC
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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STM32F303xB STM32F303xC Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F303xB/STM32F303xC microcontrollers.
This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the
STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The
reference manual is available from the STMicroelectronics website www.st.com.
For information on the Cortex®-M4 core with FPU, please refer to:
• Cortex®-M4 with FPU Technical Reference Manual, available from ARM website
www.arm.com.
• STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214)
available from our website www.st.com.
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Description STM32F303xB STM32F303xC
2 Description
The STM32F303xB/STM32F303xC family is based on the high-performance
ARM® Cortex®-M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz,
and embedding a floating point unit (FPU), a memory protection unit (MPU) and an
embedded trace macrocell (ETM). The family incorporates high-speed embedded
memories (up to 256 Kbytes of Flash memory, up to 40 Kbytes of SRAM) and an extensive
range of enhanced I/Os and peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational
amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit
timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They
also feature standard and advanced communication interfaces: up to two I2Cs, up to three
SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN
and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an
external PLL.
The STM32F303xB/STM32F303xC family operates in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F303xB/STM32F303xC family offers devices in four packages ranging from
48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
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STM32F303xB STM32F303xC Description
Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts
Peripheral STM32F303Cx STM32F303Rx STM32F303Vx
Flash (Kbytes) 128 256 128 256 128 256
SRAM (Kbytes) on data bus 32 40 32 40 32 40
CCM (Core Coupled Memory) 8
RAM (Kbytes)
Advanced 2 (16-bit)
control
Timers General purpose 5 (16-bit)
1 (32-bit)
Basic 2 (16-bit)
PWM channels (all) (1) 31 33
PWM channels (except 22 24
complementary)
SPI (I2S)(2) 3(2)
I2C 2
Communication USART 3
interfaces UART 0 2
CAN 1
USB 1
Normal I/Os 20 27 45 in LQFP100
GPIOs (TC, TTa) 37 in WLCSP100
5-volt tolerant 17 25 42 in LQFP100
I/Os (FT, FTf) 40 in WLCSP100
DMA channels 12
Capacitive sensing channels 17 18 24
12-bit ADCs 4
Number of channels 15 22 39 in LQFP100
32 in WLCSP100
12-bit DAC channels 2
Analog comparator 7
Operational amplifiers 4
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C
Junction temperature: - 40 to 125 °C
Packages LQFP48 LQFP64 LQFP100
WLCSP100
1. This total number considers also the PWMs generated on the complementary output channels
2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
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54
Description STM32F303xB STM32F303xC
Figure 1. STM32F303xB/STM32F303xC block diagram
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STM32F303xB STM32F303xC Functional overview
3 Functional overview
3.1 ARM® Cortex®-M4 core with FPU with embedded Flash and
SRAM
The ARM Cortex-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F303xB/STM32F303xC family is compatible with
all ARM tools and software.
Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family
devices.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memory
All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash
memory available for storing programs and data. The Flash memory access time is adjusted
to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz
and 2 wait states above).
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Functional overview STM32F303xB STM32F303xC
3.4 Embedded SRAM
STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with
hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running
code from the CCM (Core Coupled Memory) RAM).
• 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute
critical routines or to access data (parity check on all of CCM RAM).
• 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
3.5 Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU
(device firmware upgrade).
3.6 Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
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STM32F303xB STM32F303xC Functional overview
3.7 Power management
3.7.1 Power supply schemes
• VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
• VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied
to VDDA differs from one analog peripheral to another. Table 3 provides the summary of
the VDDA ranges for analog peripherals. The VDDA voltage level must be always
greater or equal to the VDD voltage level and must be provided first.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Table 3. External analog supply values for analog peripherals
Analog peripheral Minimum VDDA supply Maximum VDDA supply
ADC / COMP 2.0 V 3.6 V
DAC / OPAMP 2.4 V 3.6V
3.7.2 Power supply supervision
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
• The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
• The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.7.3 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.
• The MR mode is used in the nominal regulation mode (Run)
• The LPR mode is used in Stop mode.
• The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.
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Functional overview STM32F303xB STM32F303xC
3.7.4 Low-power modes
The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC
alarm, COMPx, I2Cx or U(S)ARTx.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.
Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.8 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix
Interconnect source Interconnect Interconnect action
destination
TIMx Timers synchronization or chaining
ADCx Conversion triggers
TIMx DAC1
DMA Memory to memory transfer trigger
Compx Comparator output blanking
COMPx TIMx Timer input: OCREF_CLR input, input capture
ADCx TIMx Timer triggered by analog watchdog
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STM32F303xB STM32F303xC Functional overview
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued)
Interconnect source Interconnect Interconnect action
destination
GPIO
RTCCLK TIM16 Clock source used as input channel for HSI and
HSE/32 LSI calibration
MC0
CSS
CPU (hard fault) TIM1, TIM8,
COMPx TIM15, 16, 17 Timer break
PVD
GPIO
TIMx External trigger, timer break
GPIO ADCx Conversion external trigger
DAC1
DAC1 COMPx Comparator inverting input
Note: For more details about the interconnect actions, please refer to the corresponding sections
in the reference manual (RM0316).
3.9 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
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Functional overview STM32F303xB STM32F303xC
Figure 2. Clock tree
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18/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Functional overview
3.10 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.11 Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-
memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
3.12 Interrupts and events
3.12.1 Nested vectored interrupt controller (NVIC)
The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller
(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
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Functional overview STM32F303xB STM32F303xC
3.13 Fast analog-to-digital converter (ADC)
four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6
bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up
to 39 external channels. Some of the external channels are shared between ADC1&2 and
between ADC3&4. Channels can be configured to be either single-ended input or differential
input. The ADCs can perform conversions in single-shot or scan modes. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 4
ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4
connected to ADC4 channel 17.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
• Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timers
(TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger,
respectively, to allow the application to synchronize A/D conversion and timers.
3.13.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.13.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADCx_IN18, x=1...4 input
channel. The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.
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3.13.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.13.4 OPAMP reference voltage (VREFOPAMP)
Every OPAMP reference voltage can be measured using a corresponding ADC internal
channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17, VREFOPAMP4
connected to ADC4 channel 17.
3.14 Digital-to-analog converter (DAC)
Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
This digital interface supports the following features:
• Two DAC output channels
• 8-bit or 10-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability (for each channel)
• External triggers for conversion
3.15 Operational amplifier (OPAMP)
The STM32F303xB/STM32F303xC embeds four operational amplifiers with external or
internal follower routing and PGA capability (or even amplifier and filter capability with
external components). When an operational amplifier is selected, an external ADC channel
is used to enable output measurement.
The operational amplifier features:
• 8.2 MHz bandwidth
• 0.5 mA output capability
• Rail-to-rail input/output
• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
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Functional overview STM32F303xB STM32F303xC
3.16 Fast comparators (COMP)
The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with
programmable reference voltage (internal or external), hysteresis and speed (low speed for
low-power) and with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output pin
• Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded
internal reference voltage on page 62 for the value and precision of the internal
reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined per pair into a window comparator
3.17 Timers and watchdogs
The STM32F303xB/STM32F303xC includes two advanced control timers, up to six general-
purpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below
compares the features of the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Counter Counter Prescaler DMA Capture/ Complementary
Timer type Timer resolution type factor request compare outputs
generation Channels
TIM1, Up, Down, Any integer
Advanced TIM8 16-bit Up/Down between 1 Yes 4 Yes
and 65536
General- Up, Down, Any integer
purpose TIM2 32-bit Up/Down between 1 Yes 4 No
and 65536
General- Up, Down, Any integer
purpose TIM3, TIM4 16-bit Up/Down between 1 Yes 4 No
and 65536
General- Any integer
purpose TIM15 16-bit Up between 1 Yes 2 1
and 65536
General- Any integer
purpose TIM16, TIM17 16-bit Up between 1 Yes 1 1
and 65536
TIM6, Any integer
Basic TIM7 16-bit Up between 1 Yes 0 No
and 65536
Note: TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.
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3.17.1 Advanced timers (TIM1, TIM8)
The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM
multiplexed on six channels. They have complementary PWM outputs with programmable
inserted dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.17.2 using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)
There are up to six synchronizable general-purpose timers embedded in the
STM32F303xB/STM32F303xC (see Table 5 for differences). Each general-purpose timer
can be used to generate PWM outputs, or act as a simple time base.
• TIM2, 3, and TIM4
These are full-featured general-purpose timers:
– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.17.3 Basic timers (TIM6, TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
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Functional overview STM32F303xB STM32F303xC
3.17.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.17.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source
3.18 Real-time clock (RTC) and backup registers
The RTC and the 16 backup registers are supplied through a switch that takes power from
either the VDD supply when present or the VBAT pin. The backup registers are sixteen 32-bit
registers used to store 64 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter.It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
• Two programmable alarms with wake up from Stop and Standby mode capability.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stopand Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
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• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 40 kHz)
• The high-speed external clock divided by 32.
3.19 Inter-integrated circuit interface (I2C)
Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support
standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2 addresses, 1 with configurable mask). They also include programmable analog and
digital noise filters.
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of 50 ns Programmable length from 1 to 15
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Variations depending on Wakeup from Stop on address
Drawbacks temperature, voltage, process match is not available when digital
filter is enabled.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the features available in I2C1 and I2C2.
Table 7. STM32F303xB/STM32F303xC I2C implementation
I2C features(1) I2C1 I2C2
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X
Independent clock X X
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Functional overview STM32F303xB STM32F303xC
Table 7. STM32F303xB/STM32F303xC I2C implementation (continued)
I2C features(1) I2C1 I2C2
SMBus X X
Wakeup from STOP X X
1. X = supported.
3.20 Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F303xB/STM32F303xC devices have three embedded universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.
3.21 Universal asynchronous receiver transmitter (UART)
The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous
receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR
ENDEC, multiprocessor communication mode and single-wire half-duplex communication
mode. The UART4 interface can be served by the DMA controller.
Refer to Table 8 for the features available in all U(S)ART interfaces.
Table 8. USART features
USART modes/features(1) USART1 USART2 USART3 UART4 UART5
Hardware flow control for modem X X X - -
Continuous communication using DMA X X X X -
Multiprocessor communication X X X X X
Synchronous mode X X X - -
Smartcard mode X X X - -
Single-wire half-duplex communication X X X X X
IrDA SIR ENDEC block X X X X X
LIN mode X X X X X
Dual clock domain and wakeup from Stop mode X X X X X
Receiver timeout interrupt X X X X X
Modbus communication X X X X X
Auto baud rate detection X X X - -
Driver Enable X X X - -
1. X = supported.
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3.22 Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different
audio standards can operate as master or slave at half-duplex and full duplex
communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit
or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency
from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When
operating in master mode it can output a clock for an external audio component at 256 times
the sampling frequency.
Refer to Table 9 for the features available in SPI1, SPI2 and SPI3.
Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation
SPI features(1) SPI1 SPI2 SPI3
Hardware CRC calculation X X X
Rx/Tx FIFO X X X
NSS pulse mode X X X
I2S mode - X X
TI mode X X X
1. X = supported.
3.23 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.24 Universal serial bus (USB)
The STM32F303xB/STM32F303xC devices embed an USB device peripheral compatible
with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s)
function interface. It has software-configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM
memory for data transmission and reception.
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Functional overview STM32F303xB STM32F303xC
3.25 Infrared Transmitter
The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The
solution is based on internal connections between TIM16 and TIM17 as shown in the figure
below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 3. Infrared transmitter
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3.26 Touch sensing controller (TSC)
The STM32F303xB/STM32F303xC devices provide a simple solution for adding capacitive
sensing functionality to any application. These devices offer up to 24 capacitive sensing
channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
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Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC
devices
Group Capacitive sensing Pin Group Capacitive sensing Pin
signal name name signal name name
TSC_G1_IO1 PA0 TSC_G5_IO1 PB3
1 TSC_G1_IO2 PA1 5 TSC_G5_IO2 PB4
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
TSC_G2_IO1 PA4 TSC_G6_IO1 PB11
2 TSC_G2_IO2 PA5 6 TSC_G6_IO2 PB12
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
TSC_G3_IO1 PC5 TSC_G7_IO1 PE2
3 TSC_G3_IO2 PB0 7 TSC_G7_IO2 PE3
TSC_G3_IO3 PB1 TSC_G7_IO3 PE4
TSC_G3_IO4 PB2 TSC_G7_IO4 PE5
TSC_G4_IO1 PA9 TSC_G8_IO1 PD12
4 TSC_G4_IO2 PA10 8 TSC_G8_IO2 PD13
TSC_G4_IO3 PA13 TSC_G8_IO3 PD14
TSC_G4_IO4 PA14 TSC_G8_IO4 PD15
Table 11. No. of capacitive sensing channels available on
STM32F303xB/STM32F303xC devices
Number of capacitive sensing channels
Analog I/O group
STM32F303Vx STM32F303Rx STM32F303Cx
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive 24 18 17
sensing channels
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Functional overview STM32F303xB STM32F303xC
3.27 Development support
3.27.1 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.27.2 Embedded trace macrocell™
The ARM embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F303xB/STM32F303xC through a small number of ETM pins to an external
hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using
a high-speed channel. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer running debugger software. TPA hardware is
commercially available from common development tool vendors. It operates with third party
debugger software tools.
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4 Pinouts and pin description
Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout
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Pinouts and pin description STM32F303xB STM32F303xC
Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout
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3)26&B287 3$
1567 3$
3& 3$
3& /4)3 3&
3& 3&
3& 3&
966$95() 3&
9''$ 3%
3$ 3%
3$ 3%
3$ 3%
3$ 3) 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9''
06 9
32/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Pinouts and pin description
Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout
9'' 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$
3( 9''
3( 966
3( 3)
3( 3$
3( 3$
9%$7 3$
3& 3$
3&26&B,1 3$
3&26&B287 3$
3) 3&
3) 3&
3)26&B,1 3&
3)26&B287 /4)3 3&
1567 3'
3& 3'
3& 3'
3& 3'
3& 3'
3) 3'
966$95() 3'
95() 3'
9''$ 3%
3$ 3%
3$ 3%
3$ 3%
3$ 3) 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966 9''
069
DocID023353 Rev 13 33/148
54
Pinouts and pin description STM32F303xB STM32F303xC
Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout
$ 966 966 3& 3' 3% 3% %227 3( 9'' 9''
% 966 3$ 3' 3' 3% 3% 3( 9'' 3( 9''
& 3) 3$ 3' 3' 3% 3% 966 3( 3& 3&
26&,1
' 3$ 9'' 3& 3' 3% 3( 3( 9%$7 3& 3)
26&287
( 3$ 3$ 3$ 3& 3$ 3( 3( 3) 1567 3)
) 3& 3& 3& 3& 3$ 3& 3$ 3( 3) 3)
26&287 26&,1
* 3' 3' 3' 3' 3( 3& 3$ 3& 3& 3&
+ 3' 3' 3' 3% 3( 3$ 3$ 966$ 3$ 3&
- 966 3% 3% 3% 9'' 3% 3$ 95() 3$ 9''$
. 966 966 3% 3% 3% 3% 3$ 9'' 966 966
06Y9
34/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Pinouts and pin description
Table 12. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
I/O structure TTa 3.3 V tolerant I/O directly connected to ADC
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional Functions directly selected/enabled through peripheral registers
functions
Table 13. STM32F303xB/STM32F303xC pin definitions
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
D6 1 - - PE2 I/O FT (1) TRACECK, TIM3_CH1, -
TSC_G7_IO1, EVENTOUT
D7 2 - - PE3 I/O FT (1) TRACED0, TIM3_CH2, -
TSC_G7_IO2, EVENTOUT
C8 3 - - PE4 I/O FT (1) TRACED1, TIM3_CH3, -
TSC_G7_IO3, EVENTOUT
B9 4 - - PE5 I/O FT (1) TRACED2, TIM3_CH4, -
TSC_G7_IO4, EVENTOUT
E7 5 - - PE6 I/O FT (1) TRACED3, EVENTOUT WKUP3, RTC_TAMP3
D8 6 1 1 VBAT S - - Backup power supply
DocID023353 Rev 13 35/148
54
Pinouts and pin description STM32F303xB STM32F303xC
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
C9 7 2 2 PC13(2) I/O TC - TIM1_CH1N WKUP2, RTC_TAMP1,
RTC_TS, RTC_OUT
PC14(2)
C10 8 3 3 OSC32_IN I/O TC - - OSC32_IN
(PC14)
PC15(2)
D9 9 4 4 OSC32_ I/O TC - - OSC32_OUT
OUT
(PC15)
D10 10 - - PF9 I/O FT (1) TIM15_CH1, SPI2_SCK, -
EVENTOUT
E10 11 - - PF10 I/O FT (1) TIM15_CH2, SPI2_SCK, -
EVENTOUT
PF0-
F10 12 5 5 OSC_IN I/O FTf - TIM1_CH3N, I2C2_SDA, OSC_IN
(PF0)
PF1-
F9 13 6 6 OSC_OUT I/O FTf - I2C2_SCL OSC_OUT
(PF1)
E9 14 7 7 NRST I/O RS Device reset input / internal reset output (active low)
T
G10 15 8 - PC0 I/O TTa (1) EVENTOUT ADC12_IN6, COMP7_INM
G9 16 9 - PC1 I/O TTa (1) EVENTOUT ADC12_IN7, COMP7_INP
G8 17 10 - PC2 I/O TTa (1) COMP7_OUT, EVENTOUT ADC12_IN8
H10 18 11 - PC3 I/O TTa (1) TIM1_BKIN2, EVENTOUT ADC12_IN9
E8 19 - - PF2 I/O TTa (1) EVENTOUT ADC12_IN10
H8 20 12 8 VSSA/ S - - Analog ground/Negative reference voltage
VREF-
J8 21 - - VREF+(3) S - - Positive reference voltage
J10 22 - - VDDA S - - Analog power supply
- - 13 9 VDDA/ S - - Analog power supply/Positive reference voltage
VREF+
USART2_CTS, ADC1_IN1, COMP1_INM,
H9 23 14 10 PA0 I/O TTa (4) TIM2_CH1_ETR,TIM8_BKIN, RTC_ TAMP2, WKUP1,
TIM8_ETR,TSC_G1_IO1, COMP7_INP
COMP1_OUT, EVENTOUT
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STM32F303xB STM32F303xC Pinouts and pin description
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
USART2_RTS_DE, ADC1_IN2, COMP1_INP,
J9 24 15 11 PA1 I/O TTa (4) TIM2_CH2, TSC_G1_IO2, OPAMP1_VINP,
TIM15_CH1N, RTC_REFIN, OPAMP3_VINP
EVENTOUT
(4) USART2_TX, TIM2_CH3, ADC1_IN3, COMP2_INM,
F7 25 16 12 PA2 I/O TTa (5) TIM15_CH1, TSC_G1_IO3, OPAMP1_VOUT
COMP2_OUT, EVENTOUT
(4) USART2_RX, TIM2_CH4, ADC1_IN4, OPAMP1_VINP,
G7 26 17 13 PA3 I/O TTa TIM15_CH2, TSC_G1_IO4, COMP2_INP,
EVENTOUT OPAMP1_VINM
- 27 18 - PF4 I/O TTa (1) COMP1_OUT, EVENTOUT ADC1_IN5
(4)
K9, - - - VSS S - - Digital ground
K10
K8 28 19 - VDD S - - Digital power supply
ADC2_IN1, DAC1_OUT1,
(4) SPI1_NSS, OPAMP4_VINP,
J7 29 20 14 PA4 I/O TTa (5) SPI3_NSS,I2S3_WS, COMP1_INM, COMP2_INM,
USART2_CK, TSC_G2_IO1, COMP3_INM, COMP4_INM,
TIM3_CH2, EVENTOUT COMP5_INM, COMP6_INM,
COMP7_INM
ADC2_IN2, DAC1_OUT2
OPAMP1_VINP,
(4) OPAMP2_VINM,
H7 30 21 15 PA5 I/O TTa (5) SPI1_SCK, TIM2_CH1_ETR, OPAMP3_VINP
TSC_G2_IO2, EVENTOUT COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM, COMP6_INM,
COMP7_INM
(4) SPI1_MISO, TIM3_CH1,
H6 31 22 16 PA6 I/O TTa (5) TIM8_BKIN, TIM1_BKIN, ADC2_IN3, OPAMP2_VOUT
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3, EVENTOUT
SPI1_MOSI, TIM3_CH2, ADC2_IN4, COMP2_INP,
K7 32 23 17 PA7 I/O TTa (4) TIM17_CH1, TIM1_CH1N, OPAMP2_VINP,
TIM8_CH1N, TSC_G2_IO4, OPAMP1_VINP
COMP2_OUT, EVENTOUT
G6 33 24 - PC4 I/O TTa (1) USART1_TX, EVENTOUT ADC2_IN5
(4)
DocID023353 Rev 13 37/148
54
Pinouts and pin description STM32F303xB STM32F303xC
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
F6 34 25 - PC5 I/O TTa (1) USART1_RX, TSC_G3_IO1, ADC2_IN11, OPAMP2_VINM,
EVENTOUT OPAMP1_VINM
TIM3_CH3, TIM1_CH2N, ADC3_IN12, COMP4_INP,
J6 35 26 18 PB0 I/O TTa - TIM8_CH2N,TSC_G3_IO2, OPAMP3_VINP,
EVENTOUT OPAMP2_VINP
(4) TIM3_CH4, TIM1_CH3N,
K6 36 27 19 PB1 I/O TTa (5) TIM8_CH3N, COMP4_OUT, ADC3_IN1, OPAMP3_VOUT-
TSC_G3_IO3, EVENTOUT
K5 37 28 20 PB2 I/O TTa - TSC_G3_IO4, EVENTOUT ADC2_IN12, COMP4_INM,
OPAMP3_VINM
F8 38 - - PE7 I/O TTa (1) TIM1_ETR, EVENTOUT ADC3_IN13, COMP4_INP
E6 39 - - PE8 I/O TTa (1) TIM1_CH1N, EVENTOUT COMP4_INM, ADC34_IN6
- 40 - - PE9 I/O TTa (4) TIM1_CH1, EVENTOUT ADC3_IN2
(1)
- 41 - - PE10 I/O TTa (1) TIM1_CH2N, EVENTOUT ADC3_IN14
H5 42 - - PE11 I/O TTa (1) TIM1_CH2, EVENTOUT ADC3_IN15
G5 43 - - PE12 I/O TTa (1) TIM1_CH3N, EVENTOUT ADC3_IN16
- 44 - - PE13 I/O TTa (1) TIM1_CH3, EVENTOUT ADC3_IN3
- 45 - - PE14 I/O TTa (4) TIM1_CH4, TIM1_BKIN2, ADC4_IN1
(1) EVENTOUT
- 46 - - PE15 I/O TTa (4) USART3_RX, TIM1_BKIN, ADC4_IN2
(1) EVENTOUT
USART3_TX, TIM2_CH3, COMP5_INM,
K4 47 29 21 PB10 I/O TTa - TSC_SYNC, EVENTOUT OPAMP4_VINM,
OPAMP3_VINM
K3 48 30 22 PB11 I/O TTa - USART3_RX, TIM2_CH4, COMP6_INP, OPAMP4_VINP
TSC_G6_IO1, EVENTOUT
K1,
J1, 49 31 23 VSS S - - Digital ground
K2
J5 50 32 24 VDD S - - Digital power supply
(4) SPI2_NSS,I2S2_WS,I2C2_S
J4 51 33 25 PB12 I/O TTa (5) MBA, USART3_CK, ADC4_IN3, COMP3_INM,
TIM1_BKIN, TSC_G6_IO2, OPAMP4_VOUT
EVENTOUT
38/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Pinouts and pin description
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
(4) SPI2_SCK,I2S2_CK,USART3 ADC3_IN5, COMP5_INP,
J3 52 34 26 PB13 I/O TTa _CTS, TIM1_CH1N, OPAMP4_VINP,
TSC_G6_IO3, EVENTOUT OPAMP3_VINP
SPI2_MISO,I2S2ext_SD,
J2 53 35 27 PB14 I/O TTa (4) USART3_RTS_DE, COMP3_INP, ADC4_IN4,
TIM1_CH2N, TIM15_CH1, OPAMP2_VINP
TSC_G6_IO4, EVENTOUT
SPI2_MOSI, I2S2_SD,
H4 54 36 28 PB15 I/O TTa (4) TIM1_CH3N, RTC_REFIN, ADC4_IN5, COMP6_INM
TIM15_CH1N, TIM15_CH2,
EVENTOUT
- 55 - - PD8 I/O TTa (1) USART3_TX, EVENTOUT ADC4_IN12, OPAMP4_VINM
G4 56 - - PD9 I/O TTa (1) USART3_RX, EVENTOUT ADC4_IN13
H3 57 - - PD10 I/O TTa (1) USART3_CK, EVENTOUT ADC34_IN7, COMP6_INM
H2 58 - - PD11 I/O TTa (1) USART3_CTS, EVENTOUT ADC34_IN8, COMP6_INP,
OPAMP4_VINP
(1) USART3_RTS_DE,
H1 59 - - PD12 I/O TTa TIM4_CH1, TSC_G8_IO1, ADC34_IN9, COMP5_INP
EVENTOUT
G3 60 - - PD13 I/O TTa (1) TIM4_CH2, TSC_G8_IO2, ADC34_IN10, COMP5_INM
EVENTOUT
G2 61 - - PD14 I/O TTa (1) TIM4_CH3, TSC_G8_IO3, COMP3_INP, ADC34_IN11,
EVENTOUT OPAMP2_VINP
G1 62 - - PD15 I/O TTa (1) SPI2_NSS, TIM4_CH4, COMP3_INM
TSC_G8_IO4, EVENTOUT
(1) I2S2_MCK, COMP6_OUT,
F4 63 37 - PC6 I/O FT TIM8_CH1, TIM3_CH1, -
EVENTOUT
(1) I2S3_MCK, TIM8_CH2,
F2 64 38 - PC7 I/O FT TIM3_CH2, COMP5_OUT, -
EVENTOUT
F1 65 39 - PC8 I/O FT (1) TIM8_CH3, TIM3_CH3, -
COMP3_OUT, EVENTOUT
(1) TIM8_CH4,
F3 66 40 - PC9 I/O FT TIM8_BKIN2,TIM3_CH4, -
I2S_CKIN, EVENTOUT
DocID023353 Rev 13 39/148
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Pinouts and pin description STM32F303xB STM32F303xC
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
I2C2_SMBA,I2S2_MCK,
F5 67 41 29 PA8 I/O FT - USART1_CK, TIM1_CH1, -
TIM4_ETR, MCO,
COMP3_OUT, EVENTOUT
I2C2_SCL,I2S3_MCK,
USART1_TX, TIM1_CH2,
E5 68 42 30 PA9 I/O FTf - TIM2_CH3, TIM15_BKIN, -
TSC_G4_IO1, COMP5_OUT,
EVENTOUT
I2C2_SDA, USART1_RX,
TIM1_CH3, TIM2_CH4,
E1 69 43 31 PA10 I/O FTf - TIM8_BKIN, TIM17_BKIN, -
TSC_G4_IO2, COMP6_OUT,
EVENTOUT
USART1_CTS, USB_DM,
CAN_RX, TIM1_CH1N,
E2 70 44 32 PA11 I/O FT - TIM1_CH4, TIM1_BKIN2, -
TIM4_CH1, COMP1_OUT,
EVENTOUT
USART1_RTS_DE, USB_DP,
CAN_TX, TIM1_CH2N,
D1 71 45 33 PA12 I/O FT - TIM1_ETR, TIM4_CH2, -
TIM16_CH1, COMP2_OUT,
EVENTOUT
USART3_CTS, TIM4_CH3,
E3 72 46 34 PA13 I/O FT - TIM16_CH1N, TSC_G4_IO3, -
IR_OUT, SWDIO-JTMS,
EVENTOUT
(1) I2C2_SCL,
C1 73 - - PF6 I/O FTf USART3_RTS_DE, -
TIM4_CH4, EVENTOUT
A1,
A2, 74 47 35 VSS S - - Ground
B1
D2 75 48 36 VDD S - - Digital power supply
I2C1_SDA, USART2_TX,
C2 76 49 37 PA14 I/O FTf - TIM8_CH2,TIM1_BKIN, -
TSC_G4_IO4, SWCLK-JTCK,
EVENTOUT
40/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Pinouts and pin description
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
I2C1_SCL, SPI1_NSS,
SPI3_NSS, I2S3_WS, JTDI,
B2 77 50 38 PA15 I/O FTf - USART2_RX, TIM1_BKIN, -
TIM2_CH1_ETR, TIM8_CH1,
EVENTOUT
(1) SPI3_SCK, I2S3_CK,
E4 78 51 - PC10 I/O FT USART3_TX, UART4_TX, -
TIM8_CH1N, EVENTOUT
(1) SPI3_MISO, I2S3ext_SD,
D3 79 52 - PC11 I/O FT USART3_RX, UART4_RX, -
TIM8_CH2N, EVENTOUT
(1) SPI3_MOSI, I2S3_SD,
A3 80 53 - PC12 I/O FT USART3_CK, UART5_TX, -
TIM8_CH3N, EVENTOUT
B3 81 - - PD0 I/O FT (1) CAN_RX, EVENTOUT -
C3 82 - - PD1 I/O FT (1) CAN_TX, TIM8_CH4, -
TIM8_BKIN2,EVENTOUT
A4 83 54 - PD2 I/O FT (1) UART5_RX, TIM3_ETR, -
TIM8_BKIN, EVENTOUT
(1) USART2_CTS,
B4 84 - - PD3 I/O FT TIM2_CH1_ETR, -
EVENTOUT
C4 85 - - PD4 I/O FT (1) USART2_RTS_DE, -
TIM2_CH2, EVENTOUT
- 86 - - PD5 I/O FT (1) USART2_TX, EVENTOUT -
- 87 - - PD6 I/O FT (1) USART2_RX, TIM2_CH4, -
EVENTOUT
D4 88 - - PD7 I/O FT (1) USART2_CK, TIM2_CH3, -
EVENTOUT
SPI3_SCK, I2S3_CK,
SPI1_SCK, USART2_TX,
A5 89 55 39 PB3 I/O FT - TIM2_CH2, TIM3_ETR, -
TIM4_ETR, TIM8_CH1N,
TSC_G5_IO1, JTDO-
TRACESWO, EVENTOUT
DocID023353 Rev 13 41/148
54
Pinouts and pin description STM32F303xB STM32F303xC
Table 13. STM32F303xB/STM32F303xC pin definitions (continued)
Pin number Pin functions
WLCSP100 Pin name Pin type I/O structure
LQFP100 LQFP64 LQFP48 (function Notes
after Alternate functions Additional functions
reset)
SPI3_MISO, I2S3ext_SD,
SPI1_MISO, USART2_RX,
B5 90 56 40 PB4 I/O FT - TIM3_CH1, TIM16_CH1, -
TIM17_BKIN, TIM8_CH2N,
TSC_G5_IO2, NJTRST,
EVENTOUT
SPI3_MOSI, SPI1_MOSI,
I2S3_SD, I2C1_SMBA,
A6 91 57 41 PB5 I/O FT - USART2_CK, TIM16_BKIN, -
TIM3_CH2, TIM8_CH3N,
TIM17_CH1, EVENTOUT
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
B6 92 58 42 PB6 I/O FTf - TIM8_CH1,TSC_G5_IO3, -
TIM8_ETR, TIM8_BKIN2,
EVENTOUT
I2C1_SDA, USART1_RX,
C5 93 59 43 PB7 I/O FTf - TIM3_CH4, TIM4_CH2, -
TIM17_CH1N, TIM8_BKIN,
TSC_G5_IO4, EVENTOUT
A7 94 60 44 BOOT0 I B - Boot memory selection
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
D5 95 61 45 PB8 I/O FTf - TIM8_CH2, TIM1_BKIN, -
TSC_SYNC, COMP1_OUT,
EVENTOUT
I2C1_SDA, CAN_TX,
C6 96 62 46 PB9 I/O FTf - TIM17_CH1, TIM4_CH4, -
TIM8_CH3, IR_OUT,
COMP2_OUT, EVENTOUT
B7 97 - - PE0 I/O FT (1) USART1_TX, TIM4_ETR, -
TIM16_CH1, EVENTOUT
A8 98 - - PE1 I/O FT (1) USART1_RX, TIM17_CH1, -
EVENTOUT
C7 99 63 47 VSS S - - Ground
A9,
A10, 100 64 48 VDD S - - Digital power supply
B10,
B8
42/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Pinouts and pin description
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must
not be configured in analog mode.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the RM0316 reference manual.
3. The VREF+ functionality is available only on the 100 pin package. On the 64-pin and 48-pin packages, the VREF+ is
internally connected to VDDA.
4. Fast ADC channel.
5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.
DocID023353 Rev 13 43/148
54
44/148 Table 14. Alternate functions for port A Pinouts
Port
& AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15 and
Pin
Name pin
TIM2_ TSC_ USART2_ COMP1 TIM8_ TIM8_ EVENT description
PA0 - CH1_ - G1_IO1 - - - CTS _OUT BKIN ETR - - - OUT
ETR
PA1 RTC_ TIM2_ - TSC_ - - - USART2_ TIM15_ - - - - EVENT
REFIN CH2 G1_IO2 RTS_DE CH1N OUT
PA2 - TIM2_ - TSC_ - - - USART2_ COMP2 TIM15_ - - - - EVENT
CH3 G1_IO3 TX _OUT CH1 OUT
PA3 - TIM2_ - TSC_ - - - USART2_ - TIM15_ - - - - EVENT
DocID023353 Rev 13 CH4 G1_IO4 RX CH2 OUT
PA4 - - TIM3_ TSC_ - SPI1_ SPI3_NSS, USART2_ - - - - - - EVENT
CH2 G2_IO1 NSS I2S3_WS CK OUT
TIM2_ TSC_ SPI1_ EVENT
PA5 - CH1_ - G2_IO2 - SCK - - - - - - - - OUT
ETR
PA6 - TIM16_ TIM3_ TSC_ TIM8_ SPI1_ TIM1_BKIN - COMP1 - - - - - EVENT
CH1 CH1 G2_IO3 BKIN MISO _OUT OUT
PA7 - TIM17_ TIM3_ TSC_ TIM8_ SPI1_ TIM1_CH1N - COMP2 - - - - - EVENT
CH1 CH2 G2_IO4 CH1N MOSI _OUT OUT
PA8 MCO - - - I2C2_ I2S2_ TIM1_CH1 USART1_ COMP3 - TIM4_ - - - EVENT STM32F303xB STM32F303xC
SMBA MCK CK _OUT ETR OUT
PA9 - - - TSC_ I2C2_ I2S3_ TIM1_CH2 USART1_ COMP5 TIM15_ TIM2_ - - - EVENT
G4_IO1 SCL MCK TX _OUT BKIN CH3 OUT
PA10 - TIM17_ - TSC_ I2C2_ - TIM1_CH3 USART1_ COMP6 - TIM2_ TIM8_BKIN - - EVENT
BKIN G4_IO2 SDA RX _OUT CH4 OUT
PA11 - - - - - - TIM1_CH1N USART1_ COMP1 CAN_RX TIM4_ TIM1_CH4 TIM1_ USB_ EVENT
CTS _OUT CH1 BKIN2 DM OUT
Table 14. Alternate functions for port A (continued) STM32F303xB STM32F303xC
Port
& AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15
Pin
Name
PA12 - TIM16_ - - - - TIM1_CH2N USART1_ COMP2 CAN_TX TIM4_ TIM1_ETR - USB_ EVENT
CH1 RTS_DE _OUT CH2 DP OUT
PA13 SWDIO TIM16_ - TSC_ - IR_ - USART3_ - - TIM4_ - - - EVENT
-JTMS CH1N G4_IO3 OUT CTS CH3 OUT
PA14 SWCLK - - TSC_ I2C1_ TIM8_ TIM1_BKIN USART2_ - - - - - - EVENT
-JTCK G4_IO4 SDA CH2 TX OUT
TIM2_ TIM8_ I2C1_ SPI1_ SPI3_NSS, USART2_ TIM1_ EVENT
PA15 JTDI CH1_ CH1 - SCL NSS I2S3_WS RX - BKIN - - - - OUT
ETR
DocID023353 Rev 13
Pinouts
and
pin
45/148 description
46/148 Table 15. Alternate functions for port B Pinouts
Port
& AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 and
Pin
Name pin
PB0 - - TIM3_ TSC_ TIM8_ - TIM1_CH2N - - - - - EVENT description
CH3 G3_IO2 CH2N OUT
PB1 - - TIM3_ TSC_ TIM8_ - TIM1_CH3N - COMP4_ - - - EVENT
CH4 G3_IO3 CH3N OUT OUT
PB2 - - - TSC_ - - - - - - - - EVENT
G3_IO4 OUT
JTDO- TIM2_ TIM4_ TSC_ TIM8_ SPI1_ SPI3_SCK, USART2_ TIM3_ EVENT
PB3 TRACES CH2 ETR G5_IO1 CH1N SCK I2S3_CK TX - - ETR - OUT
DocID023353 Rev 13 WO
PB4 NJTRST TIM16_ TIM3_ TSC_ TIM8_ SPI1_ SPI3_MISO, USART2_ - - TIM17_ - EVENT
CH1 CH1 G5_IO2 CH2N MISO I2S3ext_SD RX BKIN OUT
PB5 - TIM16_ TIM3_ TIM8_ I2C1_ SPI1_ SPI3_MOSI, USART2_ - - TIM17_ - EVENT
BKIN CH2 CH3N SMBA MOSI I2S3_SD CK CH1 OUT
PB6 - TIM16_ TIM4_ TSC_ I2C1_SCL TIM8_CH1 TIM8_ USART1_ - - TIM8_ - EVENT
CH1N CH1 G5_IO3 ETR TX BKIN2 OUT
PB7 - TIM17_ TIM4_ TSC_ I2C1_ TIM8_ - USART1_ - - TIM3_ - EVENT
CH1N CH2 G5_IO4 SDA BKIN RX CH4 OUT
PB8 - TIM16_ TIM4_ TSC_ I2C1_SCL - - - COMP1_ CAN_RX TIM8_ TIM1_ EVENT STM32F303xB STM32F303xC
CH1 CH3 SYNC OUT CH2 BKIN OUT
PB9 - TIM17_ TIM4_ I2C1_ - IR_OUT - COMP2_ CAN_TX TIM8_ - EVENT
CH1 CH4 SDA OUT CH3 OUT
PB10 - TIM2_ - TSC_ - - - USART3_ - - - - EVENT
CH3 SYNC TX OUT
PB11 - TIM2_ - TSC_ - - - USART3_ - - - - EVENT
CH4 G6_IO1 RX OUT
PB12 - - - TSC_ I2C2_ SPI2_NSS, TIM1_ USART3_ - - - - EVENT
G6_IO2 SMBA I2S2_WS BKIN CK OUT
Table 15. Alternate functions for port B (continued) STM32F303xB STM32F303xC
Port
& AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15
Pin
Name
PB13 - - - TSC_ - SPI2_SCK, TIM1_ USART3_ - - - - EVENT
G6_IO3 I2S2_CK CH1N CTS OUT
PB14 - TIM15_ - TSC_ - SPI2_MISO, TIM1_ USART3_ - - - - EVENT
CH1 G6_IO4 I2S2ext_SD CH2N RTS_DE OUT
PB15 RTC_ TIM15_ TIM15_ - TIM1_ SPI2_MOSI, - - - - - - EVENT
REFIN CH2 CH1N CH3N I2S2_SD OUT
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Pinouts
and
pin
47/148 description
48/148 Table 16. Alternate functions for port C Pinouts
Port &
Pin AF1 AF2 AF3 AF4 AF5 AF6 AF7 and
Name
PC0 EVENTOUT - - - - - - pin
PC1 EVENTOUT - - - - - - description
PC2 EVENTOUT - COMP7_OUT - - - -
PC3 EVENTOUT - - - - TIM1_BKIN2 -
PC4 EVENTOUT - - - - - USART1_TX
PC5 EVENTOUT - TSC_G3_IO1 - - - USART1_RX
PC6 EVENTOUT TIM3_CH1 - TIM8_CH1 - I2S2_MCK COMP6_OUT
DocID023353 Rev 13 PC7 EVENTOUT TIM3_CH2 - TIM8_CH2 - I2S3_MCK COMP5_OUT
PC8 EVENTOUT TIM3_CH3 - TIM8_CH3 - - COMP3_OUT
PC9 EVENTOUT TIM3_CH4 - TIM8_CH4 I2S_CKIN TIM8_BKIN2 -
PC10 EVENTOUT - - TIM8_CH1N UART4_TX SPI3_SCK, I2S3_CK USART3_TX
PC11 EVENTOUT - - TIM8_CH2N UART4_RX SPI3_MISO, I2S3ext_SD USART3_RX
PC12 EVENTOUT - - TIM8_CH3N UART5_TX SPI3_MOSI, I2S3_SD USART3_CK
PC13 - - - TIM1_CH1N - - -
PC14 - - - - - - -
PC15 - - - - - - - STM32F303xB STM32F303xC
Table 17. Alternate functions for port D STM32F303xB STM32F303xC
Port & AF1 AF2 AF3 AF4 AF5 AF6 AF7
Pin Name
PD0 EVENTOUT - - - - - CAN_RX
PD1 EVENTOUT - - TIM8_CH4 - TIM8_BKIN2 CAN_TX
PD2 EVENTOUT TIM3_ETR - TIM8_BKIN UART5_RX - -
PD3 EVENTOUT TIM2_CH1_ETR - - - - USART2_CTS
PD4 EVENTOUT TIM2_CH2 - - - - USART2_RTS_DE
PD5 EVENTOUT - - - - - USART2_TX
PD6 EVENTOUT TIM2_CH4 - - - - USART2_RX
PD7 EVENTOUT TIM2_CH3 - - - - USART2_CK
DocID023353 Rev 13 PD8 EVENTOUT - - - - - USART3_TX
PD9 EVENTOUT - - - - - USART3_RX
PD10 EVENTOUT - - - - - USART3_CK
PD11 EVENTOUT - - - - - USART3_CTS
PD12 EVENTOUT TIM4_CH1 TSC_G8_IO1 - - - USART3_RTS_DE
PD13 EVENTOUT TIM4_CH2 TSC_G8_IO2 - - - -
PD14 EVENTOUT TIM4_CH3 TSC_G8_IO3 - - - -
PD15 EVENTOUT TIM4_CH4 TSC_G8_IO4 - - SPI2_NSS -
Pinouts
and
pin
49/148 description
50/148 Table 18. Alternate functions for port E Pinouts
Port & AF0 AF1 AF2 AF3 AF4 AF6 AF7
Pin Name and
PE0 - EVENTOUT TIM4_ETR - TIM16_CH1 - USART1_TX pin
PE1 - EVENTOUT - - TIM17_CH1 - USART1_RX description
PE2 TRACECK EVENTOUT TIM3_CH1 TSC_G7_IO1 - - -
PE3 TRACED0 EVENTOUT TIM3_CH2 TSC_G7_IO2 - - -
PE4 TRACED1 EVENTOUT TIM3_CH3 TSC_G7_IO3 - - -
PE5 TRACED2 EVENTOUT TIM3_CH4 TSC_G7_IO4 - - -
PE6 TRACED3 EVENTOUT - - - -
PE7 - EVENTOUT TIM1_ETR - - - -
DocID023353 Rev 13 PE8 - EVENTOUT TIM1_CH1N - - - -
PE9 - EVENTOUT TIM1_CH1 - - - -
PE10 - EVENTOUT TIM1_CH2N - - - -
PE11 - EVENTOUT TIM1_CH2 - - - -
PE12 - EVENTOUT TIM1_CH3N - - - -
PE13 - EVENTOUT TIM1_CH3 - - - -
PE14 - EVENTOUT TIM1_CH4 - - TIM1_BKIN2 -
PE15 - EVENTOUT TIM1_BKIN - - - USART3_RX
STM32F303xB STM32F303xC
Table 19. Alternate functions for port F STM32F303xB STM32F303xC
Port & AF1 AF2 AF3 AF4 AF5 AF6 AF7
Pin Name
PF0 - - - I2C2_SDA - TIM1_CH3N -
PF1 - - - I2C2_SCL - - -
PF2 EVENTOUT - - - - - -
PF4 EVENTOUT COMP1_OUT - - - - -
PF6 EVENTOUT TIM4_CH4 - I2C2_SCL - - USART3_RTS_DE
PF9 EVENTOUT - TIM15_CH1 - SPI2_SCK - -
PF10 EVENTOUT - TIM15_CH2 - SPI2_SCK - -
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pin
51/148 description
Memory mapping STM32F303xB STM32F303xC
5 Memory mapping
Figure 8. STM32F303xB/STM32F303xC memory map
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52/148 DocID023353 Rev 13
STM32F303xB STM32F303xC Memory mapping
Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary
addresses
Bus Boundary address Size Peripheral
(bytes)
AHB3 0x5000 0400 - 0x5000 07FF 1K ADC3 - ADC4
0x5000 0000 - 0x5000 03FF 1K ADC1 - ADC2
0x4800 1800 - 0x4FFF FFFF ~132 M Reserved
0x4800 1400 - 0x4800 17FF 1K GPIOF
0x4800 1000 - 0x4800 13FF 1K GPIOE
AHB2 0x4800 0C00 - 0x4800 0FFF 1K GPIOD
0x4800 0800 - 0x4800 0BFF 1K GPIOC
0x4800 0400 - 0x4800 07FF 1K GPIOB
0x4800 0000 - 0x4800 03FF 1K GPIOA
0x4002 4400 - 0x47FF FFFF ~128 M Reserved
0x4002 4000 - 0x4002 43FF 1K TSC
0x4002 3400 - 0x4002 3FFF 3K Reserved
0x4002 3000 - 0x4002 33FF 1K CRC
0x4002 2400 - 0x4002 2FFF 3K Reserved
AHB1 0x4002 2000 - 0x4002 23FF 1K Flash interface
0x4002 1400 - 0x4002 1FFF 3K Reserved
0x4002 1000 - 0x4002 13FF 1K RCC
0x4002 0800 - 0x4002 0FFF 2K Reserved
0x4002 0400 - 0x4002 07FF 1K DMA2
0x4002 0000 - 0x4002 03FF 1K DMA1
0x4001 8000 - 0x4001 FFFF 32 K Reserved
0x4001 4C00 - 0x4001 7FFF 13 K Reserved
0x4001 4800 - 0x4001 4BFF 1K TIM17
0x4001 4400 - 0x4001 47FF 1K TIM16
0x4001 4000 - 0x4001 43FF 1K TIM15
0x4001 3C00 - 0x4001 3FFF 1K Reserved
0x4001 3800 - 0x4001 3BFF 1K USART1
APB2 0x4001 3400 - 0x4001 37FF 1K TIM8
0x4001 3000 - 0x4001 33FF 1K SPI1
0x4001 2C00 - 0x4001 2FFF 1K TIM1
0x4001 0800 - 0x4001 2BFF 9K Reserved
0x4001 0400 - 0x4001 07FF 1K EXTI
0x4001 0000 - 0x4001 03FF 1K SYSCFG + COMP + OPAMP
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Memory mapping STM32F303xB STM32F303xC
Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary
addresses (continued)
Bus Boundary address Size Peripheral
(bytes)
0x4000 8000 - 0x4000 FFFF 32 K Reserved
0x4000 7800 - 0x4000 7FFF 2K Reserved
0x4000 7400 - 0x4000 77FF 1K DAC (dual)
0x4000 7000 - 0x4000 73FF 1K PWR
0x4000 6800 - 0x4000 6FFF 2K Reserved
0x4000 6400 - 0x4000 67FF 1K bxCAN
0x4000 6000 - 0x4000 63FF 1K USB SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF 1K USB device FS
0x4000 5800 - 0x4000 5BFF 1K I2C2
0x4000 5400 - 0x4000 57FF 1K I2C1
0x4000 5000 - 0x4000 53FF 1K UART5
0x4000 4C00 - 0x4000 4FFF 1K UART4
0x4000 4800 - 0x4000 4BFF 1K USART3
0x4000 4400 - 0x4000 47FF 1K USART2
APB1 0x4000 4000 - 0x4000 43FF 1K I2S3ext
0x4000 3C00 - 0x4000 3FFF 1K SPI3/I2S3
0x4000 3800 - 0x4000 3BFF 1K SPI2/I2S2
0x4000 3400 - 0x4000 37FF 1K I2S2ext
0x4000 3000 - 0x4000 33FF 1K IWDG
0x4000 2C00 - 0x4000 2FFF 1K WWDG
0x4000 2800 - 0x4000 2BFF 1K RTC
0x4000 1800 - 0x4000 27FF 4K Reserved
0x4000 1400 - 0x4000 17FF 1K TIM7
0x4000 1000 - 0x4000 13FF 1K TIM6
0x4000 0C00 - 0x4000 0FFF 1K Reserved
0x4000 0800 - 0x4000 0BFF 1K TIM4
0x4000 0400 - 0x4000 07FF 1K TIM3
0x4000 0000 - 0x4000 03FF 1K TIM2
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6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions Figure 10. Pin input voltage
0&8SLQ 0&8SLQ
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Electrical characteristics STM32F303xB STM32F303xC
6.1.6 Power supply scheme
Figure 11. Power supply scheme
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1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply
pins.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
56/148 DocID023353 Rev 13
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6.1.7 Current consumption measurement
Figure 12. Current consumption measurement scheme
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6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics, and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 21. Voltage characteristics(1)
Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage (including VDDA, VBAT -0.3 4.0
and VDD)
VDD–VDDA Allowed voltage difference for VDD > VDDA - 0.4
VREF+–VDDA(2) Allowed voltage difference for VREF+ > VDDA - 0.4
Input voltage on FT and FTf pins VSS −0.3 VDD + 4.0 V
VIN(3) Input voltage on TTa pins VSS −0.3 4.0
Input voltage on any other pin VSS −0.3 4.0
Input voltage on Boot0 pin 0 9
|ΔVDDx| Variations between different VDD power pins - 50 mV
|VSSX −VSS| Variations between all the different ground pins(4) - 50
VESD(HBM) Electrostatic discharge voltage (human body see Section 6.3.12: Electrical -
model) sensitivity characteristics
1. pVVAelDDlrDDmmAAaitmmitneuudpssorttawbpneoegwreg(e.rVerTDaohDtnee,rbVfotehDlflaDoonAwre)ionaorgnredraqetuglatarhotlieuotonnsdsaVhmD(iVpDeS.mtSim,uVsetSabSseA)VrepDsiDnpsiencmttheuedstpbaoelwwtweaeryesunpbVesDecDqoAunenanenccdeteV. dDDto: the external power supply, in the
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Electrical characteristics STM32F303xB STM32F303xC
2. VREF+ must be always lower or equal than VDDA (VREF+ ≤VDDA). If unused then it must be connected to VDDA.
3. VcuINrremnatxvimaluuems.must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected
4. Include VREF- pin.
Table 22. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD power lines (source) 160
ΣIVSS Total current out of sum of all VSS ground lines (sink) − 160
IVDD Maximum current into each VDD power line (source)(1) 100
IVSS Maximum current out of each VSS ground line (sink)(1) − 100
IIO(PIN) Output current sunk by any I/O and control pin 25
Output current source by any I/O and control pin −25 mA
ΣIIO(PIN) Total output current sunk by sum of all IOs and control pins(2) 80
Total output current sourced by sum of all IOs and control pins(2) − 80
Injected current on FT, FTf and B pins(3) -5/+0
IINJ(PIN) Injected current on TC and RST pin(4) ±5
Injected current on TTa pins(5) ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. pAellrmmaititnedporawnegre(.VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection iTsainbdleu2ce1d: VboyltVagINe>chVaDrDacwtehriilsetiacsnefogratthiveeminajexicmtiounmisalilnodwuecdedinpbuytVvIoNl
exceeded. Refer to
5. A positive injection is induced b2y1:VVINol>taVgeDDcAhawrahciletearisntiecgsaftoivrethienjemcatixoinmiusminadlulocweeddbiynpVuINt
exceeded. Refer also to Table
disturbs the analog performance of the device. See note (2) below Table 70.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 23. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJ Maximum junction temperature 150 °C
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6.3 Operating conditions
6.3.1 General operating conditions
Table 24. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 72
fPCLK1 Internal APB1 clock frequency - 0 36 MHz
fPCLK2 Internal APB2 clock frequency - 0 72
VDD Standard operating voltage - 2 3.6 V
Analog operating voltage Must have a potential 2 3.6
VDDA (OPAMP and DAC not used) equal to or higher than V
Analog operating voltage VDD 2.4 3.6
(OPAMP and DAC used)
VBAT Backup operating voltage - 1.65 3.6 V
TC I/O –0.3 VDD+0.3
VIN I/O input voltage TTa I/O –0.3 VDDA+0.3 V
FT and FTf I/O(1) –0.3 5.5
BOOT0 0 5.5
WLCSP100 - 500
Power dissipation at TA = LQFP100 - 488 mW
PD 81505°C°Cfofrorsusfufifxfix67o(2r )TA =
LQFP64 - 444
LQFP48 - 364
Ambient temperature for 6 Maximum power –40 85
suffix version dissipation °C
TA Low-power dissipation(3) –40 105
Ambient temperature for 7 Maximum power –40 105
suffix version dissipation °C
Low-power dissipation(3) –40 125
TJ Junction temperature range 6 suffix version –40 105 °C
7 suffix version –40 125
1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. cIfhTaAraisctleorwisetric, sh)i.gher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal
3. ISnelcotwio-npo7w.5e:rTdhisesrmipaatliochnasrtaactete,rTisAticcsa)n. be extended to this range as long as TJ does not exceed TJmax (see
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Electrical characteristics STM32F303xB STM32F303xC
6.3.2 Operating conditions at power-up / power-down
The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.
Table 25. Operating conditions at power-up / power-down
Symbol Parameter Conditions Min Max Unit
VDD rise time rate 0 ∞
tVDD -
VDD fall time rate 20 ∞
µs/V
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 20 ∞
6.3.3 Embedded reset and power control block characteristics
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 24.
Table 26. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPOR/PDR(1) Power on/power down Falling edge 1.8(2) 1.88 1.96 V
reset threshold Rising edge 1.84 1.92 2.0 V
VPDRhyst(1) PDR hysteresis - - 40 - mV
tRSTTEMPO(3) POR reset - 1.5 2.5 4.5 ms
temporization
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design.
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Table 27. Programmable voltage detector characteristics
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
VPVD0 PVD threshold 0 Rising edge 2.1 2.18 2.26
Falling edge 2 2.08 2.16
VPVD1 PVD threshold 1 Rising edge 2.19 2.28 2.37
Falling edge 2.09 2.18 2.27
VPVD2 PVD threshold 2 Rising edge 2.28 2.38 2.48
Falling edge 2.18 2.28 2.38
VPVD3 PVD threshold 3 Rising edge 2.38 2.48 2.58
Falling edge 2.28 2.38 2.48 V
VPVD4 PVD threshold 4 Rising edge 2.47 2.58 2.69
Falling edge 2.37 2.48 2.59
VPVD5 PVD threshold 5 Rising edge 2.57 2.68 2.79
Falling edge 2.47 2.58 2.69
VPVD6 PVD threshold 6 Rising edge 2.66 2.78 2.9
Falling edge 2.56 2.68 2.8
VPVD7 PVD threshold 7 Rising edge 2.76 2.88 3
Falling edge 2.66 2.78 2.9
VPVDhyst(2) PVD hysteresis - - 100 - mV
IDD(PVD) PVD current - - 0.15 0.26 µA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.
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Electrical characteristics STM32F303xB STM32F303xC
6.3.4 Embedded reference voltage
The parameters given in Table 28 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 24.
Table 28. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.2 1.23 1.25 V
–40 °C < TA < +85 °C 1.2 1.23 1.24(1) V
ADC sampling time when
TS_vrefint reading the internal - 2.2 - - µs
reference voltage
Internal reference voltage
VRERINT spread over the VDD = 3 V ±10 mV - - 10(2) mV
temperature range
TCoeff Temperature coefficient - - - 100(2) ppm/°C
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 29. Internal reference voltage calibration values
Calibration value name Description Memory address
Raw data acquired at
VREFINT_CAL temperature of 30 °C 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V
6.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2
• When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
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The parameters given in Table 30 to Table 34 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24.
Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions fHCLK Max @ TA(1) Max @ TA(1) Unit
Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
72 MHz 61.2 65.8 67.6 68.5 27.8 30.3 30.7 31.5
64 MHz 54.7 59.1 60.2 61.1 24.6 27.2 27.6 28.3
External 48 MHz 41.7 45.1 46.2 47.2 19.2 21.1 21.4 21.8
clock (HSE 32 MHz 28.1 31.5 32.5 32.7 12.9 14.6 14.8 15.3
Supply bypass) 24 MHz 21.4 23.7 24.4 25.2 10.0 11.4 11.4 12.1
current in 8 MHz 7.4 8.4 8.6 9.4 3.6 4.1 4.4 5.0
Run mode, 1 MHz 1.3 1.6 1.8 2.6 0.8 1.0 1.2 2.1
executing
from Flash 64 MHz 49.7 54.4 55.4 56.3 24.5 27.2 27.4 28.1
48 MHz 37.9 42.2 43.0 43.5 18.9 21.4 21.5 21.6
Internal 32 MHz 25.8 29.2 29.2 30.0 12.7 14.2 14.6 15.2
clock (HSI)
24 MHz 19.7 22.3 22.6 23.2 6.7 7.7 7.9 8.5
IDD 8 MHz 6.9 7.8 8.3 8.8 3.5 4.0 4.4 5.0 mA
72 MHz 60.8 66.2(2) 69.7 70.4(2) 27.4 31.7(2) 32.2 32.5(2)
64 MHz 54.3 59.1 62.2 63.3 24.3 28.3 28.7 28.8
External 48 MHz 41.0 45.6 47.3 47.9 18.3 21.6 21.9 22.1
clock (HSE 32 MHz 27.6 32.4 32.4 32.9 12.3 15.0 15.2 15.4
Supply bypass) 24 MHz 20.8 23.9 24.3 25.0 9.3 11.3 11.4 12.0
current in 8 MHz 6.9 7.8 8.7 9.0 3.1 3.7 4.2 4.9
Run mode, 1 MHz 0.9 1.2 1.5 2.3 0.4 0.6 1.0 1.8
executing
from RAM 64 MHz 49.2 53.9 55.2 57.4 23.9 27.8 28.2 28.4
48 MHz 37.3 40.8 41.4 44.1 18.2 21.0 21.6 21.9
Internal 32 MHz 25.1 27.6 29.1 30.1 12.0 14.0 14.5 15.1
clock (HSI)
24 MHz 19.0 21.6 22.1 22.9 6.3 7.2 7.7 8.1
8 MHz 6.4 7.3 7.9 8.4 3.0 3.5 4.0 4.7
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Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued)
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions fHCLK Max @ TA(1) Max @ TA(1) Unit
Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
72 MHz 44.0 48.4 49.4 50.5 6.6 7.5 7.9 8.7
64 MHz 39.2 43.3 44.0 45.2 6.0 6.8 7.2 7.9
External 48 MHz 29.6 32.7 33.3 34.3 4.5 5.2 5.6 6.3
Supply clock (HSE 32 MHz 19.7 23.3 23.3 23.5 3.1 3.5 4.0 4.8
current in bypass) 24 MHz 14.9 17.6 17.8 18.3 2.4 2.8 3.3 3.9
Sleep 8 MHz 4.9 5.7 6.1 6.9 0.8 1.0 1.4 2.2
IDD mode, 1 MHz 0.6 0.9 1.2 2.1 0.1 0.3 0.6 1.5 mA
executing
from Flash 64 MHz 34.2 38.1 39.2 40.3 5.7 6.3 6.8 7.5
or RAM 48 MHz 25.8 28.7 29.6 30.3 4.3 4.8 5.2 5.9
Internal 32 MHz 17.4 19.4 19.9 20.7 2.9 3.2 3.7 4.5
clock (HSI)
24 MHz 13.2 15.1 15.6 15.9 1.5 1.8 2.2 2.9
8 MHz 4.5 5.0 5.6 6.2 0.7 0.9 1.2 2.1
1. Guaranteed by characterization results unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
Table 31. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Symbol Parameter Conditions fHCLK Max @ TA(2) Max @ TA(2) Unit
(1)
Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
72 MHz 225 276 289 297 245 302 319 329
64 MHz 198 249 261 268 216 270 284 293
48 MHz 149 195 204 211 159 209 222 230
Supply HSE 32 MHz 102 145 152 157 110 154 162 169
current in bypass
Run/Sleep 24 MHz 80 119 124 128 86 126 131 135
IDDA mode, 8 MHz 2 3 4 6 3 4 5 9 µA
code 1 MHz 2 3 5 7 3 4 6 9
executing 64 MHz 270 323 337 344 299 354 371 381
from Flash
or RAM 48 MHz 220 269 280 286 244 293 309 318
HSI clock 32 MHz 173 218 228 233 193 239 251 257
24 MHz 151 194 200 204 169 211 219 225
8 MHz 73 97 99 103 88 105 110 116
1. Current consumption from the VfrDoDmA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent the frequency.
2. Guaranteed by characterization results.
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Table 32. Typical and maximum VDD consumption in Stop and Standby modes
Typ @VDD (VDD=VDDA) Max(1)
Symbol Parameter Conditions TA = TA = TA = Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V 25 °C 85 °C 105 °C
Supply Regulator in run mode, 20.05 20.33 20.42 20.50 20.67 20.80 44.2(2) 350 735(2)
current in all oscillators OFF
Stop mode Regulator in low-power 7.63 7.77 7.90 8.07 8.17 8.33 30.6(2) 335 720(2)
IDD mode, all oscillators OFF µA
Supply LSI ON and IWDG ON 0.80 0.96 1.09 1.23 1.37 1.51 - - -
current in
Standby LSI OFF and IWDG OFF 0.60 0.74 0.83 0.93 1.02 1.11 5.0(2) 7.8 13.3(2)
mode
1. Guaranteed by characterization results unless otherwise specified.
2. Data based on characterization results and tested in production.
Table 33. Typical and maximum VDDA consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Symbol Parameter Conditions TA = TA = TA = Unit
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V 25 °C 85 °C 105 °C
Regulator in run mode, 1.81 1.95 2.07 2.20 2.35 2.52 3.7 5.5 8.8
Supply VDDA monitoring ON all oscillators OFF
current in Regulator in low-power
Stop mode mode, all oscillators 1.81 1.95 2.07 2.20 2.35 2.52 3.7 5.5 8.8
OFF
Supply LSI ON and IWDG ON 2.22 2.42 2.59 2.78 3.0 3.24 - - -
current in LSI OFF and IWDG
Standby OFF 1.69 1.82 1.94 2.08 2.23 2.40 3.5 5.4 9.2
IDDA mode µA
Regulator in run mode, 1.05 1.08 1.10 1.15 1.22 1.29 - - -
Supply VDDA monitoring OFF all oscillators OFF
current in Regulator in low-power
Stop mode mode, all oscillators 1.05 1.08 1.10 1.15 1.22 1.29 - - -
OFF
Supply LSI ON and IWDG ON 1.44 1.52 1.60 1.71 1.84 1.98 - - -
current in LSI OFF and IWDG
Standby OFF 0.93 0.95 0.98 1.02 1.08 1.15 - - -
mode
1. Guaranteed by characterization results.
The total consumption is the sum of IDD and IDDA.
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Electrical characteristics STM32F303xB STM32F303xC
Table 34. Typical and maximum current consumption from VBAT supply
Typ @VBAT Max
@VBAT = 3.6 V(2)
Symbol Para Conditions Unit
(1)
meter TA = TA = TA =
1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V 25°C 85°C 105°C
LSE & RTC
ON; "Xtal
mode"
lower 0.48 0.50 0.52 0.58 0.65 0.72 0.80 0.90 1.1 1.5 2.0
driving
capability;
Backup LSEDRV[1:
IDD_VBAT domain 0] = '00' µA
supply LSE & RTC
current ON; "Xtal
mode"
higher 0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5 2.2 2.9
driving
capability;
LSEDRV[1:
0] = '11'
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
Figure 13. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
6
6
6
)6"!4 ! 6
6
6
6
6
# # # #
4! #
-36
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Typical current consumption
The MCU is placed under the following conditions:
• VDD = VDDA = 3.3 V
• All I/O pins available on each package are in analog input configuration
• The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
• When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
Table 35. Typical current consumption in Run mode, code with data processing running from
Flash
Typ
Symbol Parameter Conditions fHCLK Peripherals Peripherals Unit
enabled disabled
72 MHz 61.3 28.0
64 MHz 54.8 25.4
48 MHz 41.9 19.3
32 MHz 28.5 13.3
24 MHz 21.8 10.4
Supply current in 16 MHz 14.9 7.2
IDD Run mode from 8 MHz 7.7 3.9 mA
VDD supply 4 MHz 4.5 2.5
2 MHz 2.8 1.7
1 MHz 1.9 1.3
Running from HSE 500 kHz 1.4 1.1
crystal clock 8 MHz, 125 kHz 1.1 0.9
code executing from 72 MHz 240.3 239.5
Flash 64 MHz 210.9 210.3
48 MHz 155.8 155.6
32 MHz 105.7 105.6
24 MHz 82.1 82.0
IDDA(1) (2) Supply current in 16 MHz 58.8 58.8
Run mode from 8 MHz 2.4 2.4 µA
VDDA supply 4 MHz 2.4 2.4
2 MHz 2.4 2.4
1 MHz 2.4 2.4
500 kHz 2.4 2.4
125 kHz 2.4 2.4
1. VDDA monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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Electrical characteristics STM32F303xB STM32F303xC
Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol Parameter Conditions fHCLK Peripherals Peripherals Unit
enabled disabled
72 MHz 44.1 7.0
64 MHz 39.7 6.3
48 MHz 30.3 4.9
32 MHz 20.5 3.5
24 MHz 15.4 2.8
Supply current in 16 MHz 10.6 2.0
IDD Sleep mode from 8 MHz 5.4 1.1 mA
VDD supply
4 MHz 3.2 1.0
2 MHz 2.1 0.9
1 MHz 1.5 0.8
Running from HSE 500 kHz 1.2 0.8
crystal clock 8 MHz, 125 kHz 1.0 0.8
code executing from 72 MHz 239.7 238.5
Flash or RAM 64 MHz 210.5 209.6
48 MHz 155.0 155.6
32 MHz 105.3 105.2
24 MHz 81.9 81.8
IDDA(1) (2) Supply current in 16 MHz 58.7 58.6
Sleep mode from 8 MHz 2.4 2.4 µA
VDDA supply
4 MHz 2.4 2.4
2 MHz 2.4 2.4
1 MHz 2.4 2.4
500 kHz 2.4 2.4
125 kHz 2.4 2.4
1. VDDA monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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STM32F303xB STM32F303xC Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (seeTable 38: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics STM32F303xB STM32F303xC
Table 37. Switching output I/O current consumption
Symbol Parameter Conditions(1) I/O toggling Typ Unit
frequency (fSW)
2 MHz 0.90
4 MHz 0.93
VDD = 3.3 V 8 MHz 1.16
Cext = 0 pF
C = CINT + CEXT+ CS 18 MHz 1.60
36 MHz 2.51
48 MHz 2.97
2 MHz 0.93
4 MHz 1.06
VDD = 3.3 V 8 MHz 1.47
Cext = 10 pF
C = CINT + CEXT +CS 18 MHz 2.26
36 MHz 3.39
48 MHz 5.99
2 MHz 1.03
ISW I/O current 4 MHz 1.30 mA
consumption VDD = 3.3 V
Cext = 22 pF 8 MHz 1.79
C = CINT + CEXT +CS 18 MHz 3.01
36 MHz 5.99
2 MHz 1.10
VDD = 3.3 V 4 MHz 1.31
Cext = 33 pF 8 MHz 2.06
C = CINT + CEXT+ CS 18 MHz 3.47
36 MHz 8.35
2 MHz 1.20
VDD = 3.3 V 4 MHz 1.54
Cext = 47 pF 8 MHz 2.46
C = CINT + CEXT+ CS 18 MHz 4.51
36 MHz 9.98
1. CS = 5 pF (estimated value).
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
• all I/O pins are in analog input configuration
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• ambient operating temperature at 25°C and VDD = VDDA = 3.3 V.
Table 38. Peripheral current consumption
Peripheral Typical consumption(1)
Unit
IDD
BusMatrix (2) 12.6
DMA1 7.6
DMA2 6.1
CRC 2.1
GPIOA 10.0
GPIOB 10.3
GPIOC 2.2
GPIOD 8.8
GPIOE 3.3
GPIOF 3.0
TSC 5.5
ADC1&2 17.3
ADC3&4 18.8 µA/MHz
APB2-Bridge (3) 3.6
SYSCFG 7.3
TIM1 40.0
SPI1 8.8
TIM8 36.4
USART1 23.3
TIM15 17.1
TIM16 10.1
TIM17 11.0
APB1-Bridge (3) 6.1
TIM2 49.1
TIM3 38.8
TIM4 38.3
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Electrical characteristics STM32F303xB STM32F303xC
Table 38. Peripheral current consumption (continued)
Peripheral Typical consumption(1)
Unit
IDD
TIM6 9.7
TIM7 12.1
WWDG 6.4
SPI2 40.4
SPI3 40.0
USART2 41.9
USART3 40.2
UART4 36.5 µA/MHz
UART5 30.8
I2C1 10.5
I2C2 10.4
USB 26.2
CAN 33.4
PWR 5.7
DAC 15.4
1. The ipsonwoetrinccolnusduemd.pRtioenfeor ftothteheantaablolegspoafrtch(IaDrDaAc)teorfispteicrsipihnetrhaelsssuubcsheqauseAnDt Cse,cDtiAoCns,.Comparators, OpAmp
etc.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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6.3.6 Wakeup time from low-power mode
The wakeup times given in Table 39 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep mode: the wakeup event is WFE.
• WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 24.
Table 39. Low-power mode wakeup timings
Symbol Parameter Conditions Typ @VDD, VDD = VDDA Max Unit
2.0 V 2.4 V 2.7 V 3V 3.3 V 3.6 V
Regulator in 4.1 3.9 3.8 3.7 3.6 3.5 4.5
Wakeup from run mode
tWUSTOP Stop mode Regulator in
low-power 7.9 6.7 6.1 5.7 5.4 5.2 9 µs
mode
tWUSTANDBY(1) Wakeup from LSI and 69.2 60.3 56.4 53.7 51.7 50 100
Standby mode IWDG OFF
Wakeup from CPU
tWUSLEEP Sleep mode - 6 - clock
cycles
1. Guaranteed by characterization results.
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Electrical characteristics STM32F303xB STM32F303xC
6.3.7 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 14.
Table 40. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext User external clock source 1 8 32 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3VDD
tw(HSEH) OSC_IN high or low time(1) 15 - -
tw(HSEL)
ns
tr(HSE)
tf(HSE) OSC_IN rise or fall time(1) - - 20
1. Guaranteed by design.
Figure 14. High-speed external clock source AC timing diagram
WZ +6(+
9+6(+
9+6(/
WU +6( WI +6( WZ +6(/ W
7+6(
06 9
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Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the
recommended clock input waveform is shown in Figure 15
Table 41. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext User External clock source - 32.768 1000 kHz
frequency(1)
VLSEH OSC32_IN input pin high level 0.7VDD - VDD
voltage V
VLSEL OSC32_IN input pin low level - VSS - 0.3VDD
voltage
tw(LSEH) OSC32_IN high or low time(1) 450 - -
tw(LSEL)
ns
tr(LSE)
tf(LSE) OSC32_IN rise or fall time(1) - - 50
1. Guaranteed by design.
Figure 15. Low-speed external clock source AC timing diagram
WZ /6(+
9/6(+
9/6(/
WU /6( WI /6( W
WZ /6(/
7/6(
06 9
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Electrical characteristics STM32F303xB STM32F303xC
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 42. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 42. HSE oscillator characteristics
Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency - 4 8 32 MHz
RF Feedback resistor - - 200 kΩ
During startup(3) - - 8.5
VDD=3.3 V, Rm= 30Ω, - 0.4 -
CL=10 pF@8 MHz
VDD=3.3 V, Rm= 45Ω, - 0.5 -
CL=10 pF@8 MHz
IDD HSE current consumption VDD=3.3 V, Rm= 30Ω, - 0.8 - mA
CL=5 pF@32 MHz
VDD=3.3 V, Rm= 30Ω, - 1 -
CL=10 pF@32 MHz
VDD=3.3 V, Rm= 30Ω, - 1.5 -
CL=20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. otSsUc(iHllaSEtio) nis the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
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STM32F303xB STM32F303xC Electrical characteristics
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 16. Typical application with an 8 MHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1 I+6(
%LDV
0+] 5) FRQWUROOHG
UHVRQDWRU JDLQ
5(;7 26&B287
&/
06 9
1. REXT value depends on the crystal characteristics.
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Electrical characteristics STM32F303xB STM32F303xC
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 43. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 43. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
LSEDRV[1:0]=00 - 0.5 0.9
lower driving capability
LSEDRV[1:0]=10 - - 1
IDD LSE current consumption medium low driving capability µA
LSEDRV[1:0]=01 - - 1.3
medium high driving capability
LSEDRV[1:0]=11 - - 1.6
higher driving capability
LSEDRV[1:0]=00 5 - -
lower driving capability
LSEDRV[1:0]=10 8 - -
gm Oscillator medium low driving capability µA/V
transconductance LSEDRV[1:0]=01 15 - -
medium high driving capability
LSEDRV[1:0]=11 25 - -
higher driving capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design.
3. rteSaUc(LhSeEd). is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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STM32F303xB STM32F303xC Electrical characteristics
Figure 17. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1 I/6(
N+] 'ULYH
UHVRQDWRU SURJUDPPDEOH
DPSOLILHU
26&B287
&/
069
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8 Internal clock source characteristics
The parameters given in Table 44 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24.
High-speed internal (HSI) RC oscillator
Table 44. HSI oscillator characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - - 8 - MHz
TRIM HSI user trimming step - - - 1(2) %
DuCy(HSI) Duty cycle - 45(2) - 55(2) %
TA = -40 to -2.8(3) - 3.8(3)
105°C
TA = -10 to 85°C -1.9(3) - 2.3(3)
ACCHSI Accuracy of the HSI oscillator TA = 0 to 85°C -1.9(3) - 2(3) %
TA = 0 to 70°C -1.3(3) - 2(3)
TA = 0 to 55°C -1(3) - 2(3)
TA = 25°C(4) -1 - 1
tsu(HSI) HSI oscillator startup time - 1(2) - 2(2) µs
IDDA(HSI) HSI oscillator power - - 80 100(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
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Figure 18. HSI oscillator accuracy characterization results for soldered parts
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Low-speed internal (LSI) RC oscillator
Table 45. LSI oscillator characteristics(1)
Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz
tsu(LSI)(2) LSI oscillator startup time - - 85 µs
IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
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6.3.9 PLL characteristics
The parameters given in Table 46 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24.
Table 46. PLL characteristics
Value
Symbol Parameter Unit
Min Typ Max
fPLL_IN PLL input clock(1) 1(2) - 24(2) MHz
PLL input clock duty cycle 40(2) - 60(2) %
fPLL_OUT PLL multiplier output clock 16(2) - 72 MHz
tLOCK PLL lock time - - 200(2) µs
Jitter Cycle-to-cycle jitter - - 300(2) ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
2. Guaranteed by design.
6.3.10 Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 47. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max(1) Unit
tprog 16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs
tERASE Page (2 KB) erase time TA = –40 to +105 °C 20 - 40 ms
tME Mass erase time TA = –40 to +105 °C 20 - 40 ms
IDD Supply current Write mode - - 10 mA
Erase mode - - 12 mA
1. Guaranteed by design.
Table 48. Flash memory endurance and data retention
Value
Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = –40 to +85 °C (6 suffix versions) 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
tRET Data retention 1 kcycle(2) at TA = 105 °C 10 Years
10 kcycles(2) at TA = 55 °C 20
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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6.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 49. They are based on the EMS levels and classes
defined in the application note AN1709.
Table 49. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD Voltage limits to be applied on any I/O pin to VDD = 3.3 V, LQFP100, TA = +25°C,
fHCLK = 72 MHz 3B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP100, TA = +25°C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 72 MHz 4A
pins to induce a functional disturbance conforms to IEC 61000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 50. EMI characteristics
Monitored Max vs. [fHSE/fHCLK]
Symbol Parameter Conditions frequency band Unit
8/72 MHz
VDD = 3.6 V, TA = 25 °C, 0.1 to 30 MHz 7
SEMI Peak level LQFP100 package 30 to 130 MHz 20 dBµV
compliant with IEC 130 MHz to 1GHz 27
61967-2 SAE EMI Level 4 -
6.3.12 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1 standard.
Table 51. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum Unit
value(1)
Electrostatic TA = +25 °C, conforming
VESD(HBM) discharge voltage to JESD22-A114 2 2000
(human body model)
WLCSP100 3 250 V
Electrostatic TA = +25 °C, conforming package
VESD(CDM) discharge voltage to ANSI/ESD STM5.3.1 Packages
(charge device model) except 4 500
WLCSP100
1. Guaranteed by characterization results.
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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 52. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
6.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The test results are given in Table 53.
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Table 53. I/O current injection susceptibility
Functional susceptibility
Symbol Description Negative Positive Unit
injection injection
Injected current on BOOT0 –0 NA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5, –5 -
PB2 with induced leakage current on other pins from this
group less than -50 µA
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with –5 -
induced leakage current on other pins from this group
IINJ less than -50 µA mA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB2, PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12,
PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8, - +5
PD9, PD10, PD11, PD12, PD13, PD14 with induced
leakage current on other pins from this group less than
400 µA
Injected current on any other FT and FTf pins –5 NA
Injected current on any other pins –5 +5
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
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6.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 24. All I/Os are CMOS and TTL
compliant.
Table 54. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
TC and TTa I/O - - 0.3 VDD+0.07 (1)
VIL Low level input FT and FTf I/O - - 0.475 VDD-0.2 (1)
voltage BOOT0 - - 0.3 VDD–0.3 (1)
All I/Os except BOOT0 - - 0.3 VDD (2) V
TC and TTa I/O 0.445 VDD+0.398 (1) - -
VIH High level input FT and FTf I/O 0.5 VDD+0.2 (1) - -
voltage BOOT0 0.2 VDD+0.95 (1) - -
All I/Os except BOOT0 0.7 VDD (2) - -
TC and TTa I/O - 200 (1) -
Vhys Schmitt trigger FT and FTf I/O - 100 (1) - mV
hysteresis
BOOT0 - 300 (1) -
TC, FT and FTf I/O
TTa I/O in digital mode - - ±0.1
VSS ≤VIN ≤VDD
Input leakage TTa I/O in digital mode - - 1
Ilkg current (3) VDD ≤VIN ≤VDDA µA
TTa I/O in analog mode - - ±0.2
VSS ≤VIN ≤VDDA
FT and FTf I/O(4) - - 10
VDD ≤VIN ≤5 V
RPU Weak pull-up VIN = VSS 25 40 55 kΩ
equivalent resistor(5)
RPD Weak pull-down VIN = VDD 25 40 55 kΩ
equivalent resistor(5)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 53: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 19 and Figure 20 for standard I/Os.
Figure 19. TC and TTa I/O input characteristics - CMOS port
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Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 22).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 22).
Output voltage levels
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 24. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL
compliant.
Table 55. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1) Output low level voltage for an I/O pin CMOS port(2) - 0.4
VOH(3) Output high level voltage for an I/O pin IIO = +8 mA VDD–0.4 -
2.7 V < VDD < 3.6 V
VOL (1) Output low level voltage for an I/O pin TTL port(2) - 0.4
VOH (3) Output high level voltage for an I/O pin IIO = +8 mA 2.4 -
2.7 V < VDD < 3.6 V
VOL(1)(4) Output low level voltage for an I/O pin IIO = +20 mA - 1.3 V
VOH(3)(4) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V VDD–1.3 -
VOL(1)(4) Output low level voltage for an I/O pin IIO = +6 mA - 0.4
VOH(3)(4) Output high level voltage for an I/O pin 2 V < VDD < 2.7 V VDD–0.4 -
VOLFM+(1)(4) Output low level voltage for an FTf I/O pin in IIO = +20 mA - 0.4
FM+ mode 2.7 V < VDD < 3.6 V
1. ITIOhe(II/IOO current sunk by the device must always respect the absolute maximum rating specified in Table 22 and the sum of
ports and control pins) must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. TofhIeIOIIO(I/cOurproerntst sourced by the device must always respect the absolute maximum rating specified in Table 22 and the sum
and control pins) must not exceed ΣIIO(PIN).
4. Data based on design simulation.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Table 56, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 24.
Table 56. I/O AC characteristics(1)
OSPEEDRy [1:0] Symbol Parameter Conditions Min Max Unit
value(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 2(3) MHz
tf(IO)out Output high to low level - 125(3)
x0 fall time CL = 50 pF, VDD = 2 V to 3.6 V ns
tr(IO)out Output low to high level - 125(3)
rise time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V - 10(3) MHz
tf(IO)out Output high to low level - 25(3)
01 fall time CL = 50 pF, VDD = 2 V to 3.6 V ns
tr(IO)out Output low to high level - 25(3)
rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 50(3) MHz
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 30(3) MHz
CL = 50 pF, VDD = 2 V to 2.7 V - 20(3) MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
11 tf(IO)out Output high to low level CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
fall time
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) ns
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3)
tr(IO)out Output low to high level CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3)
rise time
CL = 50 pF, VDD = 2 V to 2.7 V - 12(3)
fmax(IO)out Maximum frequency(2) - 2(4) MHz
FM+ tf(IO)out Output high to low level - 12(4)
configuration(4) fall time CL = 50 pF, VDD = 2 V to 3.6 V ns
tr(IO)out Output low to high level - 34(4)
rise time
Pulse width of external 10(3)
- tEXTIpw signals detected by the - - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 23.
3. Guaranteed by design.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F303x STM32F313xx reference manual
RM0316 for a description of FM+ I/O mode configuration.
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Figure 23. I/O AC characteristics definition
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6.3.15 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 54).
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 24.
Table 57. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1) NRST Input low level voltage - - - 00.3.0V7D(D1)+
0.04.4359V8D(1D) + V
VIH(NRST)(1) NRST Input high level voltage - - -
Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV
RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ
VF(NRST)(1) NRST Input filtered pulse - - - 100(1) ns
VNF(NRST)(1) NRST Input not filtered pulse - 500(1) - - ns
1. Guaranteed by design.
2. The pull-up is dbeesmiginnimedumwi(t~h1a0%truoerdreesr)is.tance in series with a switchable PMOS. This PMOS contribution to the series
resistance must
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Figure 24. Recommended NRST pin protection
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2. The user must ensure that the wleilvl enlootnbethteakNeRnSinTtopiancccaonungtobbyetlhoewdtheevicVeIL. (NRST) max level specified in
Table 57. Otherwise the reset
6.3.16 Timer characteristics
The parameters given in Table 58 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 58. TIMx(1)(2) characteristics
Symbol Parameter Conditions Min Max Unit
- 1 - tTIMxCLK
tres(TIM) Timer resolution time fTIMxCLK = 72 MHz 13.9 - ns
fTIMxCLK = 144 MHz 6.95 - ns
x=1.8
fEXT Timer external clock - 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 fTIMxCLK = 72 MHz 0 36 MHz
ResTIM Timer resolution TIMx (except TIM2) - 16 bit
TIM2 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period fTIMxCLK = 72 MHz 0.0139 910 µs
fTIMxCLK = 144 MHz 0.0069 455 µs
x=1.8
- - 65536 × 65536 tTIMxCLK
tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz - 59.65 s
with 32-bit counter fTIMxCLK = 144 MHz
x=1.8 - 29.825 s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17
timers.
2. Guaranteed by design.
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Table 59. IWDG min/max timeout period at 40 kHz (LSI) (1)
Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]=
0x000 0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 60. WWDG min-max timeout value @72 MHz (PCLK)(1)
Prescaler WDGTB Min timeout value Max timeout value
1 0 0.05687 3.6409
2 1 0.1137 7.2817
4 2 0.2275 14.564
8 3 0.4551 29.127
1. Guaranteed by design.
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6.3.17 Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev.03 for:
• Standard-mode (Sm) : with a bit rate up to 100 Kbits/s
• Fast-mode (Fm) : with a bit rate up to 400 Kbits/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1Mbits/s
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support
Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O port
characteristics.
All I2C I/Os embed an analog filter. refer to theTable 62: I2C analog filter characteristics.
Table 61. I2C timings specification (see I2C specification, rev.03, June 2007)(1)
Standard mode Fast mode Fast Mode Plus
Symbol Parameter Unit
Min Max Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 0 1000 KHz
tLOW Low period of the SCL clock 4.7 - 1.3 - 0.5 - µs
tHIGH High Period of the SCL clock 4 0.6 0.26 - µs
tr Rise time of both SDA and SCL - 1000 - 300 - 120 ns
signals
tf Fall time of both SDA and SCL - 300 - 300 - 120 ns
signals
tHD;DAT Data hold time 0 - 0 - 0 - µs
tVD;DAT Data valid time - 3.45(2) - 0.9(2) - 0.45(2) µs
tVD;ACK Data valid acknowledge time - 3.45(2) - 0.9(2) - 0.45(2) µs
tSU;DAT Data setup time 250 - 100 - 50 - ns
tHD:STA Hold time (repeated) START 4.0 - 0.6 - 0.26 - µs
condition
tSU:STA Set-up time for a repeated START 4.7 - 0.6 - 0.26 µs
condition
tSU:STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs
tBUF Bus free time between a 4.7 - 1.3 - 0.5 - µs
STOP and START condition
Cb Capacitive load for each bus line - 400 - 400 - 550 pF
Pulse width of spikes that are 50(3) 50(3)
tSP suppressed by the analog filter for 0 0 - - ns
Standard and Fast mode
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1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to the RM0316 reference manual).
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must
be less than the maximum of tVD;DAT or tVD;ACK by a transition time.
3. The minimum width of the spikes filtered by the analog filter is above tSP(max).
Table 62. I2C analog filter characteristics(1)
Symbol Parameter Min Max Unit
tAF Pulse width of spikes that are 50 260 ns
suppressed by the analog filter
1. Guaranteed by design.
Figure 25. I2C bus AC waveforms and measurement circuit
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06 9
1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply.
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Electrical characteristics STM32F303xB STM32F303xC
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 24.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 63. SPI characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit
Master mode, SPI1 24
2.7
Slave mode, SPI1 24
fSCK SPI clock frequency 2.7
1/tc(SCK) Master mode, SPI1/2/3 18
2
Slave mode, SPI1/2/3 18
2
DuCy(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 %
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
tw(SCKH) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tw(SCKL)
tsu(MI) Data input setup time Master mode 5.5 - -
tsu(SI) Slave mode 6.5 - -
th(MI) Data input hold time Master mode 5 - -
th(SI) Slave mode 5 - - ns
ta(SO) Data output access time Slave mode 0 - 4*Tpclk
tdis(SO) Data output disable time Slave mode 0 - 24
Slave mode - 12 27
tv(SO) Data output valid time Slave mode, SPI1 - 12 18
2.7
tv(MO) Master mode - 1.5 3
th(SO) Data output hold time Slave mode 11 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
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STM32F303xB STM32F303xC Electrical characteristics
Figure 26. SPI timing diagram - slave mode and CPHA = 0
166LQSXW
W68 166 WF 6&. WK 166
6&.,QSXW &3+$
&32/ WZ 6&.+
&3+$ WZ 6&./
&32/
W9 62 WK 62 WU 6&. WGLV 62
WI 6&.
WD 62
0,62 06%287 %,7287 /6%287
287387
WVX 6,
026, 06%,1 %,7,1 /6%,1
,1387
WK 6,
DLF
Figure 27. SPI timing diagram - slave mode and CPHA = 1(1)
166LQSXW
W68 166 WF 6&. WK 166
6&.LQSXW &3+$
&32/ WZ 6&.+
&3+$ WZ 6&./
&32/
WY 62 WK 62 WU 6&. WGLV 62
WD 62 WI 6&.
0,62 06%287 %,7287 /6%287
287387
WVX 6, WK 6,
026, 06%,1 %,7,1 /6%,1
,1387
DLE
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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Electrical characteristics STM32F303xB STM32F303xC
Figure 28. SPI timing diagram - master mode(1)
+LJK
166LQSXW
WF 6&.
6&.2XWSXW &3+$
&32/
&3+$
&32/
6&.2XWSXW &3+$
&32/
&3+$
&32/
WVX 0, WZ 6&.+ WU 6&.
WZ 6&./
0,62 WI 6&.
,13 87 06%,1 %,7,1 /6%,1
WK 0,
026, 06%287 % , 7287 /6%287
28738 7
WY 02 WK 02
DLF
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
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Table 64. I2S characteristics(1)
Symbol Parameter Conditions Min Max Unit
fCK Master data: 16 bits, 1.496 1.503
1/tc(CK) I2S clock frequency audio freq=48 kHz MHz
Slave 0 12.288
tr(CK) I2S clock rise and fall Capacitive load - 8
tf(CK) time CL = 30 pF
tw(CKH) I2S clock high time Master fPCLK= 36 MHz, 331 -
tw(CKL) I2S clock low time audio frequency = 332 -
48 kHz ns
tv(WS) WS valid time Master mode 4 -
th(WS) WS hold time Master mode 4 -
tsu(WS) WS setup time Slave mode 4 -
th(WS) WS hold time Slave mode 0 -
Duty Cycle I2S slave input clock Slave mode 30 70 %
duty cycle
tsu(SD_MR) Data input setup time Master receiver 9 -
tsu(SD_SR) Data input setup time Slave receiver 2 -
th(SD_MR) Data input hold time Master receiver 0 -
th(SD_SR) Slave receiver 0 -
tv(SD_ST) Data output valid time Slave transmitter - 29
(after enable edge) ns
th(SD_ST) Data output hold time Slave transmitter 12 -
(after enable edge)
tv(SD_MT) Data output valid time Master transmitter - 3
(after enable edge)
th(SD_MT) Data output hold time Master transmitter 2 -
(after enable edge)
1. Guaranteed by characterization results.
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