Table 1 - Electrical Characteristics (continued)
Output Ports P3 - P0
VPORT = 0·7V
Input high current
Input low current
Logic level select
Input high level
Input low level
VPORT = VCC See Note 1
See Table 5
V = V
V = V
See Note 3
5V I C logic level selected
3·3V I C logic level selected
V = V to VCC
. Output ports high impedance on power-up, with SDA and SCL at logic ‘0’.
. If the REF/COMP output is not used, the output should be left open circuit or connected to VCC and disabled by setting RE = ‘0’.
. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched
into high impedance (off) state.
4. Figures measured at 2kHz deviation, SSB (within loop bandwidth).
The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varactor tuned
local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance. It can also be operated
with comparison frequencies appropriate for frequency
offsets as required in digital terrestrial television (DTT)
The SP5730 is controlled by an I C data bus and is
compatible with both standard and fast mode formats and
with I C data generated from nominal 3·3V and 5V
sources. TheI C logic level is selected by the bi-directional
port P3/ LOGLEV. 5V logic levels are selected by
connecting P3/ LOGLEV to VCC or leaving it open circuit;
3·3V logic levels are set by connecting P3/LOGLEV to
ground. If this port is used as an input the P3 data should
be programmed to high impedance. If used as an output
only 5V logic levels can be used, in which case the logic
state imposed by the port on the input is ignored.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
Data and clock are fed in on the SDA and SCL lines
respectively as defined by I C bus format . The synthesiser
5-bit fully programmable divider which is of MN1A
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the device
into write mode if it is low, and read mode if it is high.
Tables 3 and 4 illustrate the format of the data.The device
can be programmed to respond to several addresses,
which enables the use of more than one synthesiser in
architecture, where the dual modulus prescaler is 48/9,
the A counter is 3 bits, and the M counter is 12 bits.
The output of the programmable divider is applied to the
phase comparator where it is compared in both phase
and frequency domains with the comparison frequency.
This frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 29 ratios as detailed inTable 2.
an I C bus system. Table 5 shows how the address is
selected by applying a voltage to the address input.
When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage.
When the device is programmed into read mode, the
controller accepting the data must be pulled low during
all status byte acknowledge periods to read another status
byte. If the controller fails to pull the SDA line low during
this period, the device generates an internal STOP
condition, which inhibits further reading.
The programmable divider output f /2 can be switched
to port P0 by programming the device into test mode.
The test modes are described inTable 6.