电子工程世界电子工程世界电子工程世界

产品描述

搜索
 

SP5524SKGMPAD

器件型号:SP5524SKGMPAD
器件类别:配件   
厂商名称:Zarlink Semiconductor (Microsemi)
厂商官网:http://www.zarlink.com/
下载文档

器件描述

PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16

文档预览

This product is obsolete.  
This information is available for your  
convenience only.  
For more information on  
Zarlink’s obsolete products and  
replacement product lists, please visit  
SP5524  
Bidirectional I2C Bus Controlled Synthesiser  
DS3900 - 2.1 March 1995  
TheSP5524isasingle-chipfrequencysynthesiserdesigned  
for TV tuning systems. Control data is entered in the standard  
I C BUS format. The device has six controllable open-collector  
output ports (P0-P3, P6 and P7), each capable of sinking  
CHARGE PUMP  
CRYSTAL Q1  
CRYSTAL Q2  
SDA  
1
16  
DRIVE OUTPUT  
EE  
2
V
RF INPUT  
RF INPUT  
1
0mA.Inaddition,P1isa3-bit5-levelADCinput.Theinformation  
2
on these ports can be read via the I C BUS.  
2
SP5524S  
The device has one fixed I C BUS address and three  
SCL  
V
CC  
programmable addresses, allowing two or more synthesisers  
to be used in a system.  
*
I/O PORT P0  
I/O PORT P1  
I/O PORT P2  
P6 OUTPUT PORT  
P7 OUTPUT PORT/ADD SELECT  
8
9
I/O PORT P3 ✝  
FEATURES  
MP16  
Complete 1·3GHz Single Chip System  
2
Programmable via the I C BUS  
Fig. 1 Pin connections – top view  
Low Power Consumption (215mW Typ.)  
Low Radiation  
APPLICATIONS  
Phase Lock Detector  
Satellite TV when Combined with SP4902  
·5GHz Prescaler  
Varactor Drive Amp Disable  
6 Controllable Outputs, 4 Bi-directional  
5-Level ADC  
2
Cable Tuning Systems  
VCRs  
2
Variable I C BUS Address for Picture in Picture TV  
ESD Protection *  
ORDERING INFORMATION  
SP5524S KG MPAS (Tubes)  
SP5524S KG MPAD (Tape and Reel)  
*
Normal ESD handling precautions should be observed.  
SP5524  
ELECTRICALCHARACTERISTICS  
TAMB = -10°C to +80°C, VCC = +4·5V to +5·5V.  
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature  
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.  
Value  
Characteristic  
Pin  
Units  
Conditions  
Min.  
Typ.  
Max.  
Supply current  
12  
43  
53  
mA  
VCC = 5V  
Prescaler input voltage  
13,14  
12·5  
300 mVrms 100MHz to 1GHz  
30  
300 mVrms 50MHz and 1·3GHz, see Fig. 5  
Prescaler input impedance  
Prescaler input capacitance  
13,14  
50  
2
pF  
SDA, SCL  
Input high voltage  
Input low voltage  
Input high current  
Input low current  
Leakage current  
4,5  
4,5  
4,5  
4,5  
4,5  
3
0
5·5  
1·5  
10  
-10  
10  
V
V
µA  
µA  
µA  
Input voltage = VCC  
Input voltage = 0V  
When VCC = 0V  
SDA  
Output voltage  
4
0·4  
V
Sink current = 3mA  
Charge pump current low  
Charge pump current high  
1
1
1
±50  
±170  
µA  
µA  
nA  
µA  
Byte 4, bit 2 = 0, pin 1 = 2V  
Byte 4, bit 2 = 1, pin 1 = 2V  
Byte 4, bit 4 = 1, pin 1 = 2V  
V pin 16 = 0·7V  
Charge pump output leakage current  
Charge pump drive output current  
Charge pump amplifier gain  
Recommended crystal series resistance  
Crystal oscillator drive level  
±5  
16  
500  
10  
6400  
40  
200  
mV p-p  
Parallel resonant crystal (note 2)  
Crystal oscillator negative resistance  
2
750  
Output Ports  
P0-P3, P6, P7 sink current (see note 1)  
P0-P3, P6, P7 leakage current (see note 1)  
6-11  
6-11  
10  
mA  
µA  
VOUT = 0·7V, see note 1  
VOUT = 13·2V  
10  
InputPorts  
P7 input current high  
P7 input current low  
P0, P2, P3 input voltage low  
P0, P2, P3 input voltage high  
P1 input current high  
P1 input current low  
10  
10  
6,8,9  
6,8,9  
7
+10  
-10  
0·8  
µA  
µA  
V
V
µA  
µA  
V pin 10 = 13·2V  
V pin 10 = 0V  
2·7  
+10  
-10  
See Table 3 for ADC levels  
7
NOTES  
1
. Source impedance between all output ports and ground is approximately 5. This should be taken into account when calculating output port  
saturation voltages.  
. The recommended crystal series resistance quoted refers to all conditions including start-up.  
2
2
SP5524  
ABSOLUTEMAXIMUMRATINGS  
All voltages are referred to V and pin 3 at 0V.  
EE  
Value  
Parameter  
Pin  
Units  
Conditions  
Min.  
Max.  
Supply voltage  
RF input voltage  
Port voltage  
12  
-0·3  
6
V
13,14  
6-11  
2·5  
V p-p  
-0·3  
-0·3  
14  
6
V
V
Port in off state  
Port in on state  
6
-11  
Total port output current  
RF input DC offset  
6-11  
13-14  
1
50  
mA  
V
-0·3  
-0·3  
-0·3  
-0·3  
-0·3  
VCC+0·3  
VCC+0·3  
VCC+0·3  
VCC+0·3  
Charge pump DC offset  
Drive output DC offset  
Crystal oscillator DC offset  
SDA, SCL input voltage  
V
16  
V
2
V
4,5  
VCC+0·3  
5·5  
V
V
With VCC applied  
VCC not applied  
-0·3  
Storage temperature  
Junction temperature  
-55  
+150  
+150  
°C  
°C  
MP16 thermal resistance, chip-to-ambient  
MP16 thermal resistance, chip-to-case  
111  
41  
°C/W  
°C/W  
Power consumption at 5·5V  
321  
mW  
V
CC  
RF IN  
15 BIT  
PROGRAMMABLE  
DIVIDER  
F
F
COMP  
DIV  
PHASE  
Q1  
Q2  
PRE  
AMP  
48  
PRESCALER  
DIVIDER  
512  
OSC  
4MHz  
COMP  
CRYSTAL  
4
RF IN  
F
POWER ON  
DETECTOR  
LOCK  
DETECTOR  
CHARGE  
PUMP  
1
5 BIT DIVIDER  
RATIO LATCH  
CHARGE  
PUMP  
DRIVE  
OUTPUT  
SCL  
SDA  
2
I C BUS  
T0 CP  
TRANSCEIVER  
6-BIT LATCH  
CONTROL  
OS  
PORT  
DATA  
LOGIC  
INFORMATION  
LATCH  
3
TTL  
ADDRESS  
SELECT  
3-BIT  
ADC  
T1  
LEVEL  
COMP  
V
EE  
P6 P7 P3 P2 P1 P0  
Fig. 2 Block diagram  
3
SP5524  
FUNCTIONAL DESCRIPTION  
2
The SP5524 is programmed from an I C BUS. Data and  
Clock are fed in on the SDA and SCL lines respectively as  
local oscillator control voltage until the output of the program-  
mable divider is frequency and phase locked to the comparison  
frequency.  
2
defined by the I C Bus format. The synthesiser can either  
accept new data (write mode) or send data (read mode). The  
Tables in Fig. 3 illustrate the format of the data. The device  
can be programmed to respond to several addresses, which  
The reference frequency may be generated by an external  
source capacitively coupled into pin 2 or provided by an on-  
chip 4MHz crystal controlled oscillator.  
2
enables the use of more than one synthesiser in an I C BUS  
Note that the comparison frequency is 7·8125kHz when a  
system. Table 4 shows how the address is selected by  
applying a voltage to P7. The LSB of the address byte (R/W)  
sets the device into read mode if it is high and write mode if  
it is low. When the SP5524 receives a correct address byte  
it pulls the SDA line low during the acknowledge period and  
during following acknowledge periods after further data bytes  
are programmed. When the SP5524 is programmed into the  
read mode the controlling device accepting the data must pull  
down the SDA line during the following acknowledge period  
to read another status byte.  
4MHz reference is used.  
Bit 2 of Byte 4 of the programming data (CP) controls the  
current in the charge pump circuit, a logic 1 for ±170µA and  
a logic 0 for ±50µA, allowing compensation for the variable  
tuning slope of the tuner and also to enable fast channel  
changes over the full band. Bit 4 of Byte 4 (T0) disables the  
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches  
the charge pump drive amplifier’s output off when it is set to  
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the  
phase comparator inputs are available on P6 and P7, a logic  
1
connects FCOMP to P6 and FDIV to P7.  
Byte5programstheoutputportsP0-P3, P6andP7, alogic  
WRITE MODE (FREQUENCY SYNTHESIS)  
When the device is in the write mode Bytes 2+3 select the  
synthesised frequency while Bytes 4+5 select the output port  
states and charge pump information.  
0 for a high impedance output, logic 1 for low impedance (on).  
READ MODE  
Once the correct address is received and acknowledged,  
the first bit of the next byte determines whether that byte is  
interpreted as Byte 2 or 4, a logic 0 for frequency information  
and a logic 1 for charge pump and output port information.  
Additional data bytes can be entered without the need to re-  
address the device until an I C stop condition is recognised.  
This allows a smooth frequency sweep for fine tuning or AFC  
When the device is in the read mode the status data read  
from the device on the SDA line takes the form shown in Table  
2.  
Bit 1 (POR) is the power on reset indicator and is set to a  
logic 1 if the power supply to the device has dropped below a  
nominal 3V and the programmed information lost (e.g., when  
the device is initially turned on). The POR is set to 0 when the  
readsequenceisterminatedbyastopcommand. Theoutputs  
are all set to high impedance when the device is initially  
powered up. Bit 2 (FL) indicates whether the device is phase  
locked, a logic 1 is present if the device is locked and a logic  
0 if the device is unlocked.  
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports  
P0, P2 and P3 respectively. A logic 0 indicates a low level and  
a logic 1 a high level. If the ports are to be used as inputs they  
should be programmed to a high impedance state (logic1).  
These inputs will then respond to data complying with stand-  
ard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to  
give the output of the 5-level ADC.  
2
purposes.  
If the transmission of data is stopped mid-byte (e.g., by  
another device on the bus) then the previously programmed  
byte is maintained.  
FrequencydatafromBytes2and3isstoredina15-bitshift  
register and is used to control the division ratio of the 15-bit  
programmable divider which is preceded by a divide-by-8  
prescaler and amplifier to give excellent sensitivity at the local  
oscillator input; see Fig 5. The input impedance is shown in  
Fig. 7.  
The programmed frequency can be calculated by multiply-  
ing the programmed division ratio by 8 times the comparison  
frequency FCOMP  
When frequency data is entered, the phase comparator,  
via the charge pump and varactor drive amplifier, adjusts the  
.
The 5-level ADC can be used to feed AFC information to  
the microprocessor from the IF section of the television, as  
illustrated in Fig. 4.  
4
SP5524  
MSB  
LSB  
0
28  
Address  
1
0
27  
1
0
0
0
MA1 MA0  
A
A
A
A
A
Byte1  
Byte2  
Byte3  
Byte4  
Byte5  
Programmabledivider  
Programmabledivider  
Chargepumpandtestbits  
I/Oportcontrolbits  
214 213 212 211 210  
29  
21  
1
26  
25  
24  
23  
22  
20  
1
CP T1 T0  
1
1
OS  
P7 P6  
X
X
P3 P2 P1 P0  
Table 1 Write data format (MSB transmitted first)  
Address  
1
1
0
0
0
MA1 MA0  
1
A
A
Byte1  
Byte2  
Statusbyte  
POR FL  
I2  
I1  
I0  
A2 A1 A0  
Table 2 Read data format  
A2 A1 A0  
VoltageinputtoP1  
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0·6VCC to 13·2V  
0·45VCC to 0·6VCC  
0·3VCC to 0·45VCC  
0·15VCC to 0·3VCC  
0V to 0·15VCC  
MA1 MA0 VoltageinputtoP7  
0
0
1
1
0
1
0
1
0V to 0·2VCC  
Always valid  
0·3VCC to 0·7VCC  
0·8VCC to 13·2V  
Table 3 ADC levels  
Table 4 Address selection  
A
:
Acknowledge bit  
MA1, MA0  
CP  
T1  
T0  
:
:
:
:
:
:
Variable address bits (see Table 4)  
Charge Pump current select  
Test mode selection  
Charge pump disable  
Varactor drive Output disable Switch  
Control output port states  
OS  
P7, P6  
P3, P2, P1, P0  
POR  
:
:
:
:
:
Power On Reset indicator  
Phase lock detect flag  
Digital information from ports P0, P2 and P3 respectively  
5-level ADC data from P1 (see Table 3)  
Don't care  
FL  
I2, I1, I0  
A2, A1, A0  
X
Fig. 3 Data formats  
5
SP5524  
APPLICATION  
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6.  
1
30V  
1
12V  
2
2k  
15V  
3
9n  
1
80n  
0
·1µ  
1
0k  
47k  
10n  
V
T
VARACTOR DRIVE  
2
2k  
2
N3904  
1
16  
1
5V  
18p  
1
n
4
MHz  
1
n
SDA  
SCL  
OSCILLATOR OUTPUT  
TUNER  
CONTROL  
MICRO  
2
I C BUS  
SP5524S  
P1  
2
2k  
22k  
22k  
1
2k  
8
9
P3  
P2  
12k  
12k  
2
N3906  
1
12V  
BAND INPUTS  
2
N3906  
P0  
2
N3906  
AFC OUT  
IF SIGNAL  
IF SECTION  
Fig. 4 Typical application  
3
00  
3
7·5  
OPERATING  
WINDOW  
3
0
2
5
1
2·5  
5
0 100  
500  
1000  
FREQUENCY (MHz)  
1300  
1500  
Fig. 5 Typical input sensitivity  
6
SP5524  
V
V
CC  
REF  
1
CHARGE  
PUMP  
5
50  
550  
1
3
RF INPUTS  
1
70  
1
6 DRIVE  
OUTPUT  
1
4
RF input  
Loop amplifier  
V
V
CC  
CC  
NOT  
ON P6  
PORT  
3
k
SCL/SDA  
ACK  
*
*
ON SDA ONLY  
Ports P0 - P3, P6 and P7  
SCL and SDA inputs  
2
CRYSTAL Q1  
3
CRYSTAL Q2  
Reference oscillator  
Fig. 6 Input/output interface circuits  
7
SP5524  
j1  
j0.5  
j2  
j0.2  
j5  
0
.2  
0.5  
1
2
5
0
2
j5  
2j0.2  
1
·25GHz  
2
j2  
S
Z
11: O  
= 50Ω  
2
j0.5  
NORMALISED TO 50Ω  
FREQUENCY MARKER STEP = 250MHz  
2
j1  
Fig. 7 Typical input impedance  
8
For more information about all Zarlink products  
visit our Web Site at  
www.zarlink.com  
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.  
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such  
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or  
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual  
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in  
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.  
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part  
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other  
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the  
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute  
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and  
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does  
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in  
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.  
2
2
2
Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided that the system  
2
conforms to the I C Standard Specification as defined by Philips.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright Zarlink Semiconductor Inc. All Rights Reserved.  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  
小广播

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区知春路23号集成电路设计园量子银座1305 电话:(010)82350740 邮编:100191

电子工程世界版权所有 京ICP证060456号 京ICP备10001474号 电信业务审批[2006]字第258号函 京公海网安备110108001534 Copyright © 2005-2020 EEWORLD.com.cn, Inc. All rights reserved