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SP5026DP

器件型号:SP5026DP
器件类别:配件   
厂商名称:Zarlink Semiconductor (Microsemi)
厂商官网:http://www.zarlink.com/
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器件描述

PLL FREQUENCY SYNTHESIZER, 1000 MHz, PDIP18

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This product is obsolete.  
This information is available for your  
convenience only.  
For more information on  
Zarlink’s obsolete products and  
replacement product lists, please visit  
SP5026  
1
.0GHz 3-Wire Bus Controlled Synthesizer  
Data Sheet  
DS5776  
Issue 2  
December 2002  
Features  
Complete 1.OGHz Single Chip System  
Ordering Information  
Dual Standard 62.5kHz or 31.25 kHz Step Size  
Low power Consumption (5V 40mA)  
SP5026 DP  
Function Compatible with Toshiba TD6380 and  
TD6381*  
1
8-lead plastic package)  
SP5026S MP  
Pin Compatible with SP5510  
(
16-lead miniature plastic package)  
Low Radiation  
Varactor Drive Amplifier Disable  
Charge Pump Disable  
Description  
The SP5026 is a programming variant of the SP5510,  
2
Single Port 18/19 Bit Serial Data Entry  
Four Controllable Outputs  
allowing the design of one tuner with either 1 C bus or  
3-wire bus format depending on which device is  
inserted. The SP5026, when used with a TV varicap  
tuner, forms a complete phase locked loop tuning  
system. The circuit consists of a divider-by-8 prescaler  
with its own preamplifier and at 5-bit programmable  
divider controlled by a serially-loaded data register.  
Four open-collector outputs, each independently  
programmable, are included. The device has two  
modes of operation, selected by the “mode select”  
input. In mode 1, the comparison frequency is  
ESD Protection  
See notes on pin compatibility  
Normal ESD handling procedures should be observed  
Applications  
Satellite TV when combined with SP4902 2.5GHz  
Prescaler  
Cable tuning systems  
VCRs  
7
.8125kHz and the programmable divider MSB is  
bypassed; mode comparison frequency is  
2
3
.90625kHz. The comparison frequencies are both  
obtained from a 4MHz crystal controlled on-chip  
oscillator.  
Figure 1 - Block Diagram  
1
SP5026  
Data Sheet  
The comparator has a charge pump output with an amplifier stage around which feedback may be applied. Only  
one external transistor is required for varicap line driving.  
Figure 2 - Pin Connections - Top View  
Functional Description  
The SP5026 contains all the elements necessary, with the exception of reference crystal, loop filter and external  
high voltage transistor to control a voltage controlled local oscillator, so forming a PLL frequency synthesized  
source.  
The system is controlled by a microprocessor via a standard data, clock enable three-wire bus. The data load  
normally consists of a single word, which contains the frequency and port information and is only transferred to the  
internal data shift register during an enable high period. The clock input is disabled during enable low periods.  
New data words are only accepted by the internal data buffers from the shift register on a negative transition of the  
enable, so giving improved fine tune facility for digital AFC etc.  
The data sequence and timing follows the format shown in Figure 3.  
The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of the  
divider, F , is fed to the phase comparator where it is compared in phase and frequency domain to the internal  
PD  
generated comparison frequency, F  
.
COMP  
2
Zarlink Semiconductor Inc.  
Data Sheet  
SP5026  
The FC  
is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used  
COMP  
is generally 4MHz, which gives an F  
of 3.90625kHz/7.815kHz and, when multiplied back up to the synthesized  
COMP  
LO, gives a minimum step size of 31.25kHz/62.5kHz, respectively.  
The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The  
preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input sensitivity and  
impedance are shown in Figure 5 and Figure 7 respectively.  
The SP5026 contains an improved lock detect circuit which generates a flag when the loop has attained lock. “Out  
of Lock” is indicated by high impedance state.  
The SP5026 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least  
10mA. These outputs are set by the remaining four bits within the normal data word.  
Pin Compatibility  
2
The SP5026 may by used in SP5510 applications which require 3-wire bus as opposed to 1 C bus data format. In  
SP5510 applications where the reference crystal is connected to pin 3, a small modification is required to ground  
the crystal as shown in Figure 4.  
Appropriate connections to the mode select input (pin 3) must also be made.  
In mode 1 (pin 3 “HIGH”) the SP5026 is programming and step size compatible with the Toshiba TD6380, and in  
mode 2 (pin 3 “LOW”) it is compatible with the TD6381.  
Zarlink Semiconductor Inc.  
3
SP5026  
Data Sheet  
Figure 3 - Data Format and Timing  
4
Zarlink Semiconductor Inc.  
Data Sheet  
SP5026  
Figure 4 - Typical Application (FSTEP = 31.25kHz)  
Figure 5 - Typical Input Sensitivity  
Zarlink Semiconductor Inc.  
5
SP5026  
Data Sheet  
Figure 6 - Input/Output Interface Circuits  
Figure 7 - Input/Output Interface Circuits  
6
Zarlink Semiconductor Inc.  
Data Sheet  
SP5026  
Figure 8 - Typical Input Impedance  
Electrical Characteristics  
Electrical Characteristics Table†  
Value  
Characteristics  
Supply current  
Symbol  
ICC  
Pin  
Units  
mA  
Conditions  
VCC = 5V  
Min.  
Typ.  
Max.  
14  
40  
55  
Prescaler input voltage  
15,16  
12.5  
300  
mVRMS 50MHz to 1GHz  
sinewave  
Prescaler input impedance  
Input capacitance  
15,16  
50  
2
pF  
V
High level input voltage  
High level input voltage  
Low level input voltage  
High level input current  
Low level input current  
Low level input current  
High level input current  
Low level input current  
4,5,10  
3
4
0
VCC  
VCC  
0.7  
1
3
V
3,4,5,10  
V
4,5,10  
µA  
µA  
µA  
µA  
µA  
VIN = 5.5V, VCC = 5.5V  
VIN = 0V, VCC = 5.5V  
5
4,10  
3
5
250  
150  
1
VIN = 0V, VCC = 5.5V  
VIN = 5.5V, VCC = 5.5V  
VIN = 0V, VCC = 5.5V  
3
Zarlink Semiconductor Inc.  
7
SP5026  
Data Sheet  
Electrical Characteristics Table (continued)  
Value  
Characteristics  
Symbol  
Pin  
Units  
Conditions  
Min.  
Typ.  
Max.  
Clock input hysteresis  
Clock rate  
5
5
0.4  
V
MHz  
ns  
0.5  
Data set up time  
t2  
t3  
t1  
t5  
t4  
4
300  
600  
300  
600  
300  
See Figure 3  
Data hold time  
4
ns  
See Figure 3  
See Figure 3  
See Figure 3  
See Figure 4  
V pin 1= 2.0V  
V pin 1= 2.0V  
Enable set up time  
Enable hold time  
Clock-to-enable time  
Charge pump output current  
10  
10  
10  
1
ns  
ns  
ns  
+150  
6400  
µA  
nA  
Charge pump output  
leakage current  
1
+5  
5
Drift due to leakage  
mV/s  
mA  
At collector of external  
varicap drive transistor  
Charge pump drive  
output current  
18  
1
V pin 18 = 0.7V  
Charge pump amplifier gain  
Pin 18 Current 100µA  
o
Oscillator temperature  
stability  
2
2
ppm/ C  
Oscillator stability  
with supply voltage  
ppm/V  
Recommended crystal  
series resistance  
10  
200  
“Parallel resonant” crystal  
Nominal spread = +15%  
Crystal oscillator drive level  
2
2
40  
mV p-p  
Crystal oscillator source  
impedance  
-400  
Port leakage current  
6-9  
11  
10  
4
10  
10  
µA  
µA  
µA  
µA  
VOUT = 13.2V  
VOUT = VCC  
VIN = <0V  
Lock leakage current  
Varactor Drive Amp Disable  
Charge Pump Disable  
-350  
-350  
VIN = <0V  
0
0
T
=-20 C to +80 C, V = +4.5V to +5.5V. Reference frequency = 4MHz. Pin numbers refer to SP5026 (DP package).  
amb CC  
These characteristics are guaranteed by either test or design. They apply within the specified ambient temperature and supply voltage unless  
otherwise stated.  
8
Zarlink Semiconductor Inc.  
Data Sheet  
SP5026  
Absolute Maximum Ratings  
Absolute Maximum Ratings Table†  
Value  
Max  
Pin  
Pin  
Parameter  
Units  
Conditions  
SP5024 SP5024S  
Min  
Supply voltage  
Prescaler inputs  
Output ports  
14  
15,16  
6-9  
12  
13,14  
6-9  
-0.3  
-6  
V
2.5  
Vp-p  
-0.3  
14  
6
V
V
Port in off state  
Port in on state  
-
0.3  
Total port output current  
Prescaler DC offset  
6-9  
15,16  
1,18  
2
6-9  
13,14  
1,16  
2
50  
VCC+0.3  
VCC+0.3  
VCC+0.3  
VCC+0.3  
+125  
mA  
V
-0.3  
-0.3  
-0.3  
-0.7  
-55  
Loop amplifier DC offset  
Crystal oscillator DC offset  
Data bus inputs  
V
V
4,5,10  
4,5,10  
V
0C  
With VCC applied  
Storage temperature  
Junction temperature  
+150  
0C  
DP 18 thermal resistance, chip-to-ambient  
DP 18 thermal resistance, chip-to-case  
78  
0C/W  
0C/W  
24  
MP 16 thermal resistance, chip-to-ambient  
MP 16 thermal resistance, chip-to-case  
Power consumption at 5V  
111  
41  
0C/W  
0C/W  
mW  
275  
All ports off.  
All voltages are referred to VEE = 0V.  
Zarlink Semiconductor Inc.  
9
For more information about all Zarlink products  
visit our Web Site at  
www.zarlink.com  
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.  
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such  
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or  
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual  
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in  
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.  
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part  
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other  
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the  
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute  
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and  
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does  
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in  
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.  
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2
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Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided that the system  
2
conforms to the I C Standard Specification as defined by Philips.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright Zarlink Semiconductor Inc. All Rights Reserved.  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  
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