MC9S12P128
Reference Manual
Covers also MC9S12P-Family
MC9S12P96
MC9S12P64
MC9S12P32
S12
Microcontrollers
MC9S12P128RMV1
Rev. 1.12
16 October 2009
freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual.
Revision History Revision Description
Level
Date 1.07 PRELIMINARY
April 2008 1.08
July 2008 1.09 Minor Corrections
December 2008 1.10 Added typ. IDD values
March 2009
1.11 Completed Electricals
June 2009 Minor Corrections
1.12
October 2009 Final Electricals
Corrected section 1.11.3.4 Memory
Corrected 1.7.3.16 - 1.7.3.19 SPI pin description
Removed reference to MMCCTL1 register from Table 13-5
Removed item 4b from Table A-6 and A-7
Changed Version ID in Table 1-5 from $FF to $00
Added Register Summary Appendix D
Updated FTMRC Blockguide . See Revision History Chapter 13
Updated CPMU Blockguide . See Revision History Chapter 7
Chapter 1 Device Overview MC9S12P-Family . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Port Integration Module (S12PPIMV1) . . . . . . . . . . . . . . . . . . . 49
Chapter 3 S12P Memory Map Control (S12PMMCV1). . . . . . . . . . . . . . . 107
Chapter 4 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 5 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . 131
Chapter 6 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . 155
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU)
Block Description197
Chapter 8 Freescale's Scalable Controller Area Network (S12MSCANV3).
249
Chapter 9 Analog-to-Digital Converter (ADC12B10CRev 00.05) . . . . . .303
Chapter 10 Pulse-Width Modulator (PWM8B6CV1) Block Description . . 327
Chapter 11 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 361
Chapter 12 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 397
Chapter 13 128 KByte Flash Module (S12FTMRC128K1V1). . . . . . . . . . . 423
Chapter 14 Timer Module (TIM16B8CV2) Block Description . . . . . . . . . . 471
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Appendix D Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 543
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Chapter 1Device Overview MC9S12P-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.1 MC9S12P Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.4 Main External Oscillator (XOSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.5 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.6 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.7 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.8 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.9 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.10 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.11 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.13 Analog-to-Digital Converter Module (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.14 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.15 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.16 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.5 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.7.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.8 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.9.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.9.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.12 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.13 ATD External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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1.14 S12CPMU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 2
Port Integration Module (S12PPIMV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.7 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.8 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.9 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.3.10 Ports A, B, E, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . 67
2.3.11 Ports A, B, E Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.12 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.13 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.15 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.16 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.17 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.18 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.19 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3.20 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.3.21 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.22 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.23 Port T Routing Register (PTTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.24 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.25 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.26 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.3.27 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.3.28 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.3.29 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.30 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.31 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.32 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.33 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.3.34 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.35 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.36 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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2.3.37 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.38 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.39 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.40 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.41 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.42 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.43 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.3.44 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.45 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.3.46 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.47 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.48 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.3.49 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.3.50 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3.51 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3.52 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.53 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.54 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.55 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.56 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.57 Port AD Data Register (PT0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.58 Port AD Data Register (PT1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.3.59 Port AD Data Direction Register (DDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.3.60 Port AD Data Direction Register (DDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.61 Port AD Reduced Drive Register (RDR0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.62 Port AD Reduced Drive Register (RDR1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3.63 Port AD Pull Up Enable Register (PER0AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3.64 Port AD Pull Up Enable Register (PER1AD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.3.65 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Chapter 3S12P Memory Map Control (S12PMMCV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.5 Implemented Memory in the System Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.1 Implemented Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.2 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.6.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Chapter 4
Interrupt Module (S12SINTV1)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Chapter 5
Background Debug Module (S12SBDMV1)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.4.9 SYNC -- Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 6
S12S Debug Module (S12SDBGV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
6.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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Chapter 7
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
7.2.3 TEMPSENSE -- temperature sensor output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.4 VDDR -- Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.5 VDDA, VSSA -- Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.6 VSS, VSSPLL-- Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.7 VDDX, VSSX-- Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.2.8 API_EXTCLK -- API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.4.3 Stop Mode using PLL Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Chapter 8
Freescale's Scalable Controller Area Network (S12MSCANV3)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.2.1 RXCAN -- CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
8.2.2 TXCAN -- CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
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8.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.3.3 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
8.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
8.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
8.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
8.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
8.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
8.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
8.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
8.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
8.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
8.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Chapter 9
Analog-to-Digital Converter (ADC12B10CRev 00.05)
Block Description
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
9.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
9.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
9.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
9.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Chapter 10
Pulse-Width Modulator (PWM8B6CV1) Block Description
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.2.1 PWM5 -- Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.2.2 PWM4 -- Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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10.2.3 PWM3 -- Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
10.2.4 PWM2 -- Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.2.5 PWM1 -- Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.2.6 PWM0 -- Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Chapter 11
Serial Communication Interface (S12SCIV5)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.2.1 TXD -- Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.2.2 RXD -- Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
11.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
11.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
11.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
11.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
11.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
11.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
11.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
11.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
11.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
11.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
11.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
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Chapter 12
Serial Peripheral Interface (S12SPIV5)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.2.1 MOSI -- Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.2.2 MISO -- Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
12.2.3 SS -- Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
12.2.4 SCK -- Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Chapter 13
128 KByte Flash Module (S12FTMRC128K1V1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
13.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.3 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
13.4.4 Allowed Simultaneous P-Flash and D-Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . 453
13.4.5 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
13.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
13.4.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
13.4.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
13.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
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13.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
13.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 469
13.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 470
13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
14.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
14.2.1 IOC7 -- Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.2 IOC6 -- Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.3 IOC5 -- Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.4 IOC4 -- Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.5 IOC3 -- Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.6 IOC2 -- Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 475
14.2.7 IOC1 -- Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 476
14.2.8 IOC0 -- Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 476
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
14.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
14.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
14.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
14.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
14.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
14.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
14.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
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A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
A.3 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
A.4 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
A.4.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
A.4.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
A.5 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
A.6 Electrical Characteristics for the Oscillator (OSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
A.7 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
A.8 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
A.9 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
A.10 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
A.11 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
A.11.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
A.11.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Appendix B
Ordering Information
Appendix C
Package Information
C.1 80 QFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
C.2 48 QFN Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
C.3 64 LQFP Package Mechanical Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Appendix D
Detailed Register Address Map
D.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
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Chapter 1 Device Overview MC9S12P-Family
1.1 Introduction
The MC9S12P family is an optimized, automotive, 16-bit microcontroller product line focused on low-
cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit
microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS family. The
MC9S12P family is targeted at generic automotive applications requiring CAN or LIN/J2602
communication. Typical examples of these applications include body controllers, occupant detection, door
modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.
The MC9S12P family uses many of the same features found on the MC9S12XS family, including error
correction code (ECC) on flash memory, a separate data-flash module for diagnostic or data storage, a fast
analog-to-digital converter (ATD) and a frequency modulated phase locked loop (IPLL) that improves the
EMC performance.
The MC9S12P family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low
cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of
Freescale's existing 8-bit and 16-bit MCU families. Like the MC9S12XS family, the MC9S12P family run
16-bit wide accesses without wait states for all peripherals and memories. The MC9S12P family is
available in 80-pin QFP, 64-pin LQFP, and 48-pin QFN package options and aims to maximize pin
compatibility with the MC9S12XS family. In addition to the I/O ports available in each module, further
I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.
1.2 Features
This section describes the key features of the MC9S12P family.
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Device Overview MC9S12P-Family
1.2.1 MC9S12P Family Comparison
Table 1 provides a summary of different members of the MC9S12P family and their proposed features.
This information is intended to provide an understanding of the range of functionality offered by this
microcontroller family.
Table 1. MC9S12P Family
Feature MC9S12P32 MC9S12P64 MC9S12P96 MC9S12P128
CPU CPU12-V1
Flash memory (ECC) 32 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes
Data flash (ECC) 4 Kbytes
RAM 2 Kbytes 4 Kbytes 6 Kbytes
MSCAN 1
SCI 1
SPI 1
Timer 8 ch x 16-bit
PWM 6 ch x 8-bit
ADC 10 ch x 12-bit
Frequency modulated PLL Yes
External oscillator Yes
(4 16 MHz Pierce with
loop control)
Internal 1 MHz RC Yes
oscillator
Supply voltage 3.15 V 5.5 V
Execution speed Static(1) 32 MHz
Package 80 QFP, 64 LQFP, 48 QFN
1. P or D Flash erasing or programming requires a minimum bus frequency of 1MHz
1.2.2 Chip-Level Features
On-chip modules available within the family include the following features:
S12 CPU core
Up to 128 Kbyte on-chip flash with ECC
4 Kbyte data flash with ECC
Up to 6 Kbyte on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal filter
416 MHz amplitude controlled Pierce oscillator
1 MHz internal RC oscillator
Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
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Device Overview MC9S12P-Family
Pulse width modulation (PWM) module with 6 x 8-bit channels
10-channel, 12-bit resolution successive approximation analog-to-digital converter (ATD)
One serial peripheral interface (SPI) module
One serial communication interface (SCI) module supporting LIN communications
One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
1.3 Module Features
The following sections provide more details of the modules implemented on the MC9S12P family.
1.3.1 S12 16-Bit Central Processor Unit (CPU)
S12 CPU is a high-speed 16-bit processing unit:
Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
Includes many single-byte instructions. This allows much more efficient use of ROM space.
Extensive set of indexed addressing capabilities, including:
-- Using the stack pointer as an indexing register in all indexed operations
-- Using the program counter as an indexing register in all but auto increment/decrement mode
-- Accumulator offsets using A, B, or D accumulators
-- Automatic index predecrement, preincrement, postdecrement, and postincrement (by 8 to +8)
1.3.2 On-Chip Flash with ECC
On-chip flash memory on the MC9S12P features the following:
Up to 128 Kbyte of program flash memory
-- 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
-- Erase sector size 512 bytes
-- Automated program and erase algorithm
-- User margin level setting for reads
-- Protection scheme to prevent accidental program or erase
4 Kbyte data flash space
-- 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
-- Erase sector size 256 bytes
-- Automated program and erase algorithm
-- User margin level setting for reads
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Device Overview MC9S12P-Family
1.3.3 On-Chip SRAM
Up to 6 Kbytes of general-purpose RAM
1.3.4 Main External Oscillator (XOSC)
Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal
-- Current gain control on amplitude output
-- Signal with low harmonic distortion
-- Low power
-- Good noise immunity
-- Eliminates need for external current limiting resistor
-- Transconductance sized for optimum start-up margin for typical crystals
1.3.5 Internal RC Oscillator (IRC)
Trimmable internal reference clock.
-- Frequency: 1 MHz
-- Trimmed accuracy over 40C to +125C ambient temperature range: 1.5%
1.3.6 Internal Phase-Locked Loop (IPLL)
Phase-locked-loop clock frequency multiplier
-- No external components required
-- Reference divider and multiplier allow large variety of clock rates
-- Automatic bandwidth control mode for low-jitter operation
-- Automatic frequency lock detector
-- Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
-- Reference clock sources:
External 416 MHz resonator/crystal (XOSC)
Internal 1 MHz RC oscillator (IRC)
1.3.7 System Integrity Support
Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low-voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog
-- Configurable as window COP for enhanced failure detection
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Device Overview MC9S12P-Family
-- Initialized out of reset using option bits located in flash memory
Clock monitor supervising the correct function of the oscillator
1.3.8 Timer (TIM)
8 x 16-bit channels for input capture or output compare
16-bit free-running counter with 7-bit precision prescaler
1 x 16-bit pulse accumulator
1.3.9 Pulse Width Modulation Module (PWM)
6 channel x 8-bit or 3 channel x 16-bit pulse width modulator
-- Programmable period and duty cycle per channel
-- Center-aligned or left-aligned outputs
-- Programmable clock select logic with a wide range of frequencies
1.3.10 Controller Area Network Module (MSCAN)
1 Mbit per second, CAN 2.0 A, B software compatible
-- Standard and extended data frames
-- 08 bytes data length
-- Programmable bit rate up to 1 Mbps
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization
Flexible identifier acceptance filter programmable as:
-- 2 x 32-bit
-- 4 x 16-bit
-- 8 x 8-bit
Wakeup with integrated low pass filter option
Loop back for self test
Listen-only mode to monitor CAN bus
Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages
1.3.11 Serial Communication Interface Module (SCI)
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
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Device Overview MC9S12P-Family
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN
1.3.12 Serial Peripheral Interface Module (SPI)
Configurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-first or LSB-first shifting
Serial clock phase and polarity options
1.3.13 Analog-to-Digital Converter Module (ATD)
10-channel, 12-bit analog-to-digital converter
-- 3 us single conversion time
-- 8-/10-/12-bit resolution
-- Left or right justified result data
-- Internal oscillator for conversion in stop modes
-- Wakeup from low power modes on analog comparison > or <= match
-- Continuous conversion mode
-- Multiple channel scans
Pins can also be used as digital I/O
1.3.14 On-Chip Voltage Regulator (VREG)
Linear voltage regulator with bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR) circuit
Low-voltage reset (LVR)
High temperature sensor
1.3.15 Background Debug (BDM)
Non-intrusive memory access commands
Supports in-circuit programming of on-chip nonvolatile memory
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Device Overview MC9S12P-Family
1.3.16 Debugger (DBG)
Trace buffer with depth of 64 entries
Three comparators (A, B and C)
-- Comparators A compares the full address bus and full 16-bit data bus
-- Exact address or address range comparisons
Two types of comparator matches
-- Tagged This matches just before a specific instruction begins execution
-- Force This is valid on the first instruction boundary after a match occurs
Four trace modes
Four stage state sequencer
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Device Overview MC9S12P-Family
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12P-Family devices
32K/64K/96K/128K bytes Flash ATD VDDA
2K/4K/6K bytes RAM VSSA
12-bit 10-channel VRH
Analog-Digital Converter VRL
4K bytes Data Flash AN[9:0] PTAD PAD[9:0]
VDDR Voltage Regulator TIM IOC0 PT0
VSS3 IOC1 PT1
16-bit 8 channel IOC2 PTT PT2
BKGD Timer IOC3 PT3
IOC4 PT4
EXTAL CPU12-V1 IOC5 PT5
XTAL IOC6 PT6
Debug Module IOC7 PT7
VSSPLLL PP0
RESET Single-wire Background 3 address breakpoints PP1
TEST PP2
Debug Module 1 data breakpoints PWM PWM0 PTP (Wake-Up Int) PP3
PE0 PWM1 PP4
PE1 64 Byte Trace Buffer 8-bit 6channel PWM2 PP5
PE2 Pulse Width Modulator PWM3
PE3 Amplitude Controlled Clock Monitor PWM4 PP7
PE4 Low Power Pierce COP Watchdog PWM5
PE5 Periodic Interrupt PM0
PE6 Oscillator Auton. Periodic Int. PM1
PE7 PM2
PLL with Frequency PM3
PA[7:0] Modulation option PM4
PM5
Reset Generation Interrupt Module CAN RXCAN
and Test Entry msCAN 2.0B TXCAN PS0
SPI PS1
XIRQ MISO PTM PS2
IRQ Synchronous Serial IF SS PS3
PTE ECLK MOSI PJ0
SCK PJ1
PJ2
ECLKX2 SCI RXD
PJ6
Asynchronous Serial IF TXD PJ7
PTA PTS
PB[7:0] PTB
3-5V IO Supply PTJ (Wake-up Int)
VDDX1/VSSX1
VDDX2/VSSX2
Figure 1-1. MC9S12P-Family Block Diagram
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Device Overview MC9S12P-Family
1.5 Device Memory Map
Table 1-2 shows the device register memory map.
Table 1-2. Device Register Memory Map
Address Module Size
(Bytes)
0x00000x0009 PIM (port integration module)
0x000A0x000B 10
0x000C0x000D MMC (memory map control) 2
0x000E0x000F PIM (port integration module) 2
0x00100x0017 Reserved 2
0x00180x0019 MMC (memory map control) 8
0x001A0x001B Reserved 2
0x001C0x001F Device ID register 2
0x00200x002F PIM (port integration module) 4
0x00300x0033 DBG (debug module) 16
0x00340x003F Reserved 4
0x00400x006F CPMU (clock and power management) 12
0x00700x009F TIM (timer module) 48
0x00A00x00C7 ATD (analog-to-digital converter 12 bit 10-channel) 48
0x00C80x00CF PWM (pulse-width modulator 6 channels) 40
0x00D00x00D7 SCI (serial communications interface) 8
0x00D80x00DF Reserved 8
0x00E00x00FF SPI (serial peripheral interface) 8
0x01000x0113 Reserved 32
0x01140x011F FTMRC control registers 20
Reserved 12
0x0120 INT (interrupt module) 1
0x01210x013F Reserved 31
0x01400x017F CAN 64
0x01800x023F Reserved 192
0x02400x027F PIM (port integration module) 64
0x02800x02BF Reserved 64
0x02C00x02EF Reserved 48
0x02F00x02FF CPMU (clock and power management ) 16
0x03000x03FF Reserved 256
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Device Overview MC9S12P-Family
NOTE
Reserved register space shown in Table 1-2 is not allocated to any module.
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
Figure 1-2 shows S12P CPU and BDM local address translation to the global memory map. It indicates
also the location of the internal resources in the memory map. Table 1-3. shows the mapping of D-Flash
and unpaged P-Flash memory. The whole 256K global memory space is visible through the P-Flash
window located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.
Table 1-3. MC9S12P -Family mapping for D-Flash and unpaged P-Flash
Local 64K memory map Global 256K memory map
D-Flash 0x0400 - 0x13FF 0x0_4400 - 0x0_53FF
0x1400 - 0x27FF(1) 0x3_1400 -0x3_27FF(2)
P-Flash 0x4000 - 0x7FFF 0x3_4000 - 0x3_7FFF
0xC000 - 0xFFFF 0x3_C000 - 0x3_FFFF
1. 0x2FFF for MC9S12P64 because of 4K RAM size
2. 0x3_2FFF for MC9S12P64 because of 4K RAM size
Table 1-4. Derivatives
Feature MC9S12P32 MC9S12P64 MC9S12P96 MC9S12P128
P-Flash size 32KB 64KB 96KB 128KB
PF_LOW 0x3_8000 0x3_0000
PPAGES 0x0E - 0x0F 0x0C - 0x0F 0x2_8000 0x2_0000
RAMSIZE 0x0A - 0x0F 0x08 - 0x0F
RAM_LOW 2KB 4KB
0x0_3800 0x0_3000 6KB
0x0_2800
S12P-Family Reference Manual, Rev. 1.12
26 Freescale Semiconductor
Device Overview MC9S12P-Family
Figure 1-2. MC9S12P-Family Global Memory Map
CPU and BDM Global Memory Map
Local Memory Map
0x0000 REGISTERS 0x0_0000 REGISTERS (PPAGE 0x00) (PPAGE 0x01)
0x0400 RAMSIZE
D-Flash Unimplemented Area
0x1400 RAM_LOW RAM
NVM Resources
Unpaged P-Flash 0x0_4000
0x0_4400 D-Flash
RAM RAMSIZE 0x0_5400 NVM Resources
0x4000
PF_LOW=0x0_8000
Unpaged P-Flash P-Flash (PPAGE 0x02-0x0B))
10 *16K paged
0x8000 PF_LOW=0x3_0000
P-Flash window 0 0 0 0 P3 P2 P1 P0 Unpaged P-Flash (PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F)
0xC000
PPAGE
Unpaged P-Flash
PF_LOW=0x3_4000
Unpaged P-Flash
PF_LOW=0x3_8000
0xFFFF PF_LOW=0x3_C000
Unpaged P-Flash
0x3_FFFF
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor 27
Device Overview MC9S12P-Family
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID
number and Mask Set number.
The Version ID in Table 1-5. is a word located in a flash information row. The version ID number indicates
a specific version of internal NVM controller.
Table 1-5. Assigned Part ID Numbers
Device Mask Set Number Part ID(1) Version ID
$FF
MC9S12P128 0M01N $3980 $FF
$FF
MC9S12P96 0M01N $3980 $FF
MC9S12P64 0M01N $3980
MC9S12P32 0M01N $3980
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor -- non full -- mask set revision
1.7 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.
S12P-Family Reference Manual, Rev. 1.12
28 Freescale Semiconductor
Device Overview MC9S12P-Family
1.7.1 Device Pinout
Figure 1-3. MC9S12P-Family 80 QFP pinout
80 PP4/KWP4/PWM4
79 PP5/KPW5/PWM5
78 PP7/KPW7
77 VDDX1
76 VSSX1
75 PM0/RXCAN0
74 PM1/TXCAN0
73 PM2/MISO0
72 PM3/SS0
71 PM4/MOSI0
70 PM5/SCK0
69 PJ6/KWJ6
68 PJ7/KWJ7
67 TEST
66 PS3
65 PS2
64 PS1/TXD0
63 PS0/RXD0
62 VSSA
61 VRL
PWM3/KWP3/PP3 1 60 VRH
59 VDDA
PWM2/KWP2/PP2 2 58 PAD07/AN07
57 PAD06/AN06
PWM1/KWP1/PP1 3 56 PAD05/AN05
55 PAD04/AN04
PWM0/KWP0/PP0 4 MC9S12P-Family 54 PAD03/AN03
80 QFP 53 PAD02/AN02
PWM0/IOC0/PT0 5 52 PAD01/AN01
Pins shown in BOLD are 51 PAD00/AN00
IOC1/PT1 6 not available on the 50 PAD09/AN09
64 LQFP package 49 PAD08/AN08
IOC2/PT2 7 48 PA7
47 PA6
IOC3/PT3 8 46 PA5
45 PA4
KWJ0/PJ0 9 44 PA3
43 PA2
KWJ1/PJ1 10 42 PA1
41 PA0
PWM4/IOC4/PT4 11
API_EXTCLK/PWM5/IOC5/PT5 12
IOC6/PT6 13
IOC7/PT7 14
MODC/BKGD 15
PB0 16
PB1 17
PB2 18
PB3 19
PB4 20PB5 21
PB6 22
PB7 23
PE7 24
PE6 25
PE5 26
ECLK/PE4 27
VSSX2 28
VDDX2 29
RESET 30
VDDR 31
VSS3 32
VSSPLL 33
EXTAL 34
XTAL 35
KWJ2/PJ2 36
PE3 37
PE2 38
IRQ/PE1 39
XIRQ/PE0 40
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor 29
Device Overview MC9S12P-Family
Figure 1-4. MC9S12P-Family 64 LQFP pinout
64 PP5/PWM5/KWP5
63 PP7/KWP7
62 VDDX1
61 VSSX1
60 PM0/RXCAN0
59 PM1/TXCAN0
58 PM2/MISO0
57 PM3/SS0
56 PM4/MOSI0
55 PM5/SCK0
54 TEST
53 PS3
52 PS2
51 PS1/TXD0
50 PS0/RXD0
49 VSSA/VRL
PWM3/KWP3/PP3 1 MC9S12P-Family 48 VRH
PWM2/KWP2/PP2 2 64 LQFP 47 VDDA
PWM1/KWP1/PP1 3 46 PAD07/AN07
PWM0/KWP0/PP0 4 Pins shown in BOLD are 45 PAD06/AN06
not available on the 44 PAD05/AN05
PWM0/IOC0/PT0 5 48 QFN package 43 PAD04/AN04
IOC1/PT1 6 42 PAD03/AN03
IOC2/PT2 7 41 PAD02/AN02
IOC3/PT3 8 40 PAD01/AN01
KWJ0/PJ0 9 39 PAD00/AN00
KWJ1/PJ1 10 38 PAD09/AN09
37 PAD08/AN08
PWM4/IOC4/PT4 11 36 PA3
API_EXTCLK/PWM5/IOC5/PT5 12 35 PA2
34 PA1
IOC6/PT6 13 33 PA0
IOC7/PT7 14
MODC/BKGD 15
PB0 16
PB5 17
PB6 18
PB7 19
PE7 20
ECLK/PE4 21
VSSX2 22
VDDX2 23
RESET 24
VDDR 25
VSS3 26
VSSPLL 27
EXTAL 28
XTAL 29
KWJ2/PJ2 30
IRQ/PE1 31
XIRQ/PE0 32
S12P-Family Reference Manual, Rev. 1.12
30 Freescale Semiconductor
Device Overview MC9S12P-Family
Figure 1-5. MC9S12P-Family 48 QFN pinout
48 VDDX1
47 VSSX1
46 PM0/RXCAN0
45 PM1/TXCAN0
44 PM2/MISO0
43 PM3/SS0
42 PM4/MOSI0
41 PM5/SCK0
40 TEST
39 PS1/TXD0
38 PS0/RXD0
37 VSSA/VRL
PWM3/KWP3/PP3 1 36 VDDA/VRH
PWM2/KWP2/PP2 PAD07/AN07
PWM1/KWP1/PP1 2 35 PAD06/AN06
PAD05/AN05
PWM0/IOC0/PT0 3 34 PAD04/AN04
IOC1/PT1 4 MC9S12P-Family 33 PAD03/AN03
IOC2/PT2 48 QFN PAD02/AN02
IOC3/PT3 5 32 PAD01/AN01
PAD00/AN00
PWM4/IOC4/PT4 6 31 PAD09/AN09
API_EXTCLK/PWM5/IOC5/PT5 PAD08/AN08
7 30 PE0/XIRQ
IOC6/PT6
IOC7/PT7 8 29
MODC/BKGD
9 28
10 27
11 26
12 25
PE7 13
ECLK/PE4 14
VSSX2 15
VDDX2 16
RESET 17
VDDR 18
VSS3 19
VSSPLL 20
EXTAL 21
XTAL 22
KWJ2/PJ2 23
IRQ/PE1 24
1.7.2 Pin Assignment Overview
Table 1-6 provides a summary of which Ports are available for each package option. Routing of pin
functions is summarized in Table 1-7.
Table 1-6. Port Availability by Package Option
Port 80 QFP 64 LQFP 48 QFN
Port AD/ADC Channels 10/10 10/10 10/10
4 0
Port A pins 8 4 0
Port B pins 8 4 4
Port E pins inc. IRQ/XIRQ input only 8 3 1
5 6 6
Port J 6 6 3
Port M 7 4 2
Port P 4
Port S
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor 31
Device Overview MC9S12P-Family
Table 1-6. Port Availability by Package Option
Port 80 QFP 64 LQFP 48 QFN
Port T 8 8 8
Sum of Ports 64 49 34
I/O Power Pairs VDDX/VSSX 2/2 2/2 2/2
Table 1-7. Peripheral - Port Routing Options(1)
PWM0 PWM4 PWM5
PT0 O
PT4 O
PT5 O
1. "O" denotes a possible rerouting under software
control
Table 1-8 provides a pin out summary listing the availability and functionality of individual pins for each
package option.
S12P-Family Reference Manual, Rev. 1.12
32 Freescale Semiconductor
Freescale Semiconductor Table 1-8. Pin-Out Summary(1)
Package Pin Function Internal Pull
Resistor
Power
Supply Description
QFP LQFP QFN Pin 2nd 3rd CTRL Reset
80 64 48 PP3 Func. Func. State
PP2
1 1 1 PP1 KWP3 PWM3 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PP0 PWM channel
PT0 VDDX
2 2 2 PT1 KWP2 PWM2 PERP/PPSP Disabled Port P I/O, interrupt,
PT2 VDDX PWM channel
PT3
S12P-Family Reference Manual, Rev. 1.12 3 3 3 PJ0 KWP1 PWM1 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PJ1 PWM channel
PT4 VDDX
4 4 - PT5 KWP0 PWM0 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
VDDX PWM/ channel
PT6 VDDX
5 5 4 PT7 IOC0 PWM0 VDDX PERT/PPST Disabled Port T I/O, TIM channel
BKGD IOC1 -- VDDX
6 6 5 IOC2 -- VDDX PERT/PPST Disabled Port T I/O, TIM channel
IOC3 --
7 7 6 KWJ0 -- VDDX PERT/PPST Disabled Port T I/O, TIM channel
KWJ1 --
8 8 7 IOC4 PERT/PPST Disabled Port T I/O, TIM channel
PWM4
9 9 - PERJ/PPSJ Up Port J I/O, interrupt
10 10 - PERJ/PPSJ Up Port J I/O, interrupt
11 11 8 PERT/PPST Disabled Port T I/O, PWM/TIM
channel
12 12 9 IOC5 PWM5 PERT/PPST Disabled Port T I/O, PWM/TIM Device Overview MC9S12P-Family
IOC6 or channel, API output
API_EX
TCLK
13 13 10 VDDX PERT/PPST Disabled Port T I/O, channel of
VDDX PERT/PPST TIM
VDDX
14 14 11 IOC7 Always on Disabled Port T I/O, channel of
TIM
33 15 15 12 MODC -- Up Background debug
Freescale Semiconductor Table 1-8. Pin-Out Summary(1)
Package Pin Function Internal Pull
Resistor
Power
Description
Supply
QFP LQFP QFN 2nd 3rd Reset
80 64 48 Pin Func. Func. CTRL State
16 16 - PB0 -- -- VDDX PUCR Disabled Port B I/O
17 - -
18 - - PB1 -- -- VDDX PUCR Disabled Port B I/O
19 - -
20 - - PB2 -- -- VDDX PUCR Disabled Port B I/O
21 17 -
22 18 - PB3 -- -- VDDX PUCR Disabled Port B I/O
23 19 -
S12P-Family Reference Manual, Rev. 1.12 24 20 13 PB4 -- -- VDDX PUCR Disabled Port B I/O
25 - -
PB5 -- -- VDDX PUCR Disabled Port B I/O
PB6 -- -- VDDX PUCR Disabled Port B I/O
PB7 -- -- VDDX PUCR Disabled Port B I/O
PE7 ECLKX2 -- VDDX PUCR Up Port E I/O
PE6 -- -- VDDX While RESET pin Port E I/O
is low: down
26 - - PE5 -- -- VDDX While RESET pin Port E I/O
is low: down
27 21 14 PE4 ECLK -- VDDX PUCR Up Port E I/O, bus clock
output
28 22 15 VSSX2 -- -- -- -- -- --
29 23 16 VDDX2 -- -- -- -- -- -- Device Overview MC9S12P-Family
30 24 17 RESET -- -- VDDX PULLUP External reset
31 25 18 VDDR -- -- -- -- -- --
32 26 19 VSS3 -- -- -- -- -- --
33 27 20 VSSPLL -- -- -- -- -- --
34 28 21 EXTAL -- -- VDDP NA NA Oscillator pin
LL
34
Freescale Semiconductor Table 1-8. Pin-Out Summary(1)
Package Pin Function Internal Pull
Resistor
Power
Supply Description
QFP LQFP QFN Pin 2nd 3rd CTRL Reset
80 64 48 XTAL Func. Func. State
35 29 22 -- -- VDDP NA NA Oscillator pin
LL
36 30 23 PJ2 KWJ2 -- PERJ/PPSJ Up Port J I/O, interrupt
-- VDDX PUCR
37 - - PE3 -- -- VDDX PUCR Up Port E I/O
-- VDDX PUCR
S12P-Family Reference Manual, Rev. 1.12 38 - - PE2 -- VDDX Up Port E I/O
-- PUCR
39 31 24 PE1 IRQ VDDX Up Port E Input, maskable
-- PUCR
-- VDDX PUCR interrupt
-- VDDX PUCR
40 32 25 PE0 XIRQ -- VDDX PUCR Up Port E Input, non-
-- VDDX PUCR
-- VDDX PUCR maskable interrupt
-- VDDX PUCR
41 33 - PA0 -- -- VDDX PUCR Disabled Port A I/O
PA1 -- -- VDDX PER1AD
42 34 - PA2 -- VDDA Disabled Port A I/O
PA3 -- -- PER1AD
43 35 - PA4 -- VDDA Disabled Port A I/O
PA5 -- -- PER1AD
44 36 - PA6 -- VDDA Disabled Port A I/O
PA7 -- -- PER1AD
45 - - PAD08 AN08 VDDA Disabled Port A I/O
46 - - Disabled Port A I/O
47 - - Disabled Port A I/O
48 - - Disabled Port A I/O Device Overview MC9S12P-Family
49 37 26 Disabled Port AD I/O,
analog input of ATD
50 38 27 PAD09 AN09 Disabled Port AD I/O,
analog input of ATD
51 39 28 PAD00 AN00 Disabled Port AD I/O,
analog input of ATD
52 40 29 PAD01 AN01 Disabled Port AD I/O,
analog input of ATD
35
36 Table 1-8. Pin-Out Summary(1) Device Overview MC9S12P-Family
Package Pin Function Internal Pull
Resistor
Power
Supply Description
QFP LQFP QFN Pin 2nd 3rd CTRL Reset
80 64 48 PAD02 Func. Func. State
53 41 30 AN02 -- VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
-- VDDA
54 42 31 PAD03 AN03 PER1AD Disabled Port AD I/O,
-- VDDA analog input of ATD
55 43 32 PAD04 AN04 -- VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
S12P-Family Reference Manual, Rev. 1.12 -- VDDA
56 44 33 PAD05 AN05 PER1AD Disabled Port AD I/O,
-- VDDA analog input of ATD
57 45 34 PAD06 AN06 -- -- PER1AD Disabled Port AD I/O,
-- -- analog input of ATD
-- --
58 46 35 PAD07 AN07 -- -- PER1AD Disabled Port AD I/O,
-- VDDX analog input of ATD
-- VDDX
59 47 36 VDDA -- -- VDDX -- -- --
VRH(2) -- -- VDDX
60 48 36 VRL(3) -- -- N.A. -- -- --
VSSA -- -- VDDX
61 49 37 RXD -- VDDX -- -- --
PS0 TXD -- VDDX
62 49 37 PS1 -- -- --
PS2 --
63 50 38 PS3 KWJ7 PERS/PPSS Up Port S I/O, RXD of SCI
TEST KWJ6
64 51 39 PJ7 SCK PERS/PPSS Up Port S I/O, TXD of SCI
PJ6
65 52 - PM5 PERS/PPSS Up Port S I/O
Freescale Semiconductor 66 53 - PERS/PPSS Up Port S I/O
67 54 40 RESET pin DOWN Test input
68 - - PERJ/PPSJ Up Port J I/O, interrupt
69 - - PERJ/PPSJ Up Port J I/O, interrupt
70 55 41 PERM/PPSM Disabled Port M I/O, MISO of SPI
Freescale Semiconductor Table 1-8. Pin-Out Summary(1)
Package Pin Function Internal Pull
Resistor
Power
Description
Supply
QFP LQFP QFN 2nd 3rd Reset
80 64 48 Pin Func. Func. CTRL State
71 56 42 PM4 MOSI -- VDDX PERM/PPSM Disabled Port M I/O, MOSI of SPI
72 57 43 PM3 SS -- VDDX PERM/PPSM Disabled Port M I/O, SCK of SPI
73 58 44 PM2 MISO -- VDDX PERM/PPSM Disabled Port M I/O, SS of SPI0
74 59 45 PM1 TXCAN VDDX PERM/PPSM Disabled Port M I/O, TX of CAN
S12P-Family Reference Manual, Rev. 1.12 75 60 46 PM0 RXCAN VDDX PERM/PPSM Disabled Port M I/O, RX of CAN
76 61 47 VSSX1 -- -- -- -- -- --
77 62 48 VDDX1 -- -- -- -- -- --
78 63 - PP7 KWP7 VDDX PERP/PPSP Disabled Port P I/O, interrupt
79 64 - PP5 KWP5 PWM5 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
80 - - PP4 KWP4 PWM4 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
1. Table shows a superset of pin functions. Not all functions are available on all derivatives
2. VRH and VDDA share single pin on 48 pin package option
3. VRL and VSSA share single pin on 64 and 48 pin package option
NOTE Device Overview MC9S12P-Family
For devices assembled in 48-pin and 64-pin packages all non-bonded out pins should be configured as
outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-8 for affected
pins.
37
Device Overview MC9S12P-Family
1.7.3 Detailed Signal Descriptions
1.7.3.1 EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the internal reference clock. XTAL is the oscillator output.
1.7.3.2 RESET -- External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an
internal pull-up device.
1.7.3.3 TEST -- Test Pin
This input only pin is reserved for factory test. This pin has an internal pull-down device.
NOTE
The TEST pin must be tied to VSSX in all applications.
1.7.3.4 BKGD / MODC -- Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.7.3.5 PAD[9:0] / AN[9:0] -- Port AD Input Pins of ATD
PAD[9:0] are general-purpose input or output pins and analog inputs AN[9:0] of the analog-to-digital
converter ATD.
1.7.3.6 PA[7:0] -- Port A I/O Pins
PA[7:0] are general-purpose input or output pins.
1.7.3.7 PB[7:0] -- Port B I/O Pins
PB[7:0] are general-purpose input or output pins.
1.7.3.8 PE7 -- Port E I/O Pin 7 / ECLKX2
PE7 is a general-purpose input or output pin. An internal pull-up is enabled during reset. It can be
configured to output ECLKX2.
1.7.3.9 PE[6:5] -- Port E I/O Pin 6-5
PE[6:5] are a general-purpose input or output pins.
S12P-Family Reference Manual, Rev. 1.12
38 Freescale Semiconductor
Device Overview MC9S12P-Family
1.7.3.10 PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference. The ECLK output has a programmable prescaler.
1.7.3.11 PE[3:2] -- Port E I/O Pin 3
PE[3:2] are a general-purpose input or output pins.
1.7.3.12 PE1 / IRQ -- Port E Input Pin 1
PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.
1.7.3.13 PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ
interrupt is level sensitive and active low. As XIRQ is level sensitive, while this pin is low the MCU will
not enter STOP mode.
1.7.3.14 PJ[7:6, 2:0] / KWJ[7:6, 2:0] -- Port J I/O Pins 7-6, 2-0
PJ[7:6, 2:0] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs.
1.7.3.15 PM[7:6] -- Port M I/O Pins 7-6
PM[7:6] are a general-purpose input or output pins.
1.7.3.16 PM5 / SCK -- Port M I/O Pin 5
PM5 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial
peripheral interface (SPI).
1.7.3.17 PM4 / MOSI -- Port M I/O Pin 4
PM4 is a general-purpose input or output pin. It can be configured as the master output (during master
mode) or slave input pin (during slave mode) MOSI for the serial peripheral interface (SPI).
1.7.3.18 PM3 / SS -- Port M I/O Pin 3
PM3 is a general-purpose input or output pin.It can be configured as the slave select pin SS of the serial
peripheral interface (SPI).
1.7.3.19 PM2 / MISO-- Port M I/O Pin 3
PM2 is a general-purpose input or output pin. It can be configured as the master input (during master
mode) or slave output pin (during slave mode) MISO for the serial peripheral interface (SPI)
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor 39
Device Overview MC9S12P-Family
1.7.3.20 PM1 / TXCAN -- Port M I/O Pin 1
PM1 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controller (CAN).
1.7.3.21 PM0 / RXCAN -- Port M I/O Pin 0
PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controller (CAN).
1.7.3.22 PP[5:0] / KWP[5:0] / PWM[5:0] -- Port P I/O Pins 5-0
PP[5:0] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs. They
can be configured as pulse width modulator (PWM) channel 5-0 output
1.7.3.23 PP7 / KWP7 -- Port P I/O Pin 7
PP7 is a general-purpose input or output pin. It can be configured as a keypad wakeup input.
1.7.3.24 PS3 -- Port S I/O Pin 3
PS3 is a general-purpose input or output pin.
1.7.3.25 PS2 -- Port S I/O Pin 2
PS2 is a general-purpose input or output pin.
1.7.3.26 PS1 / TXD -- Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface (SCI).
1.7.3.27 PS0 / RXD -- Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface (SCI).
1.7.3.28 PT[7:6] / IOC[7:6] -- Port T I/O Pins 7-6
PT[7:6] are general-purpose input or output pins. They can be configured as timer (TIM) channel 7-6.
1.7.3.29 PT5 / IOC5 / PWM5 / API_EXTCLK -- Port T I/O Pin 5
PT5 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 5, pulse width
modulator (PWM) output 5 or as the output of the API_EXTCLK.
S12P-Family Reference Manual, Rev. 1.12
40 Freescale Semiconductor
Device Overview MC9S12P-Family
1.7.3.30 PT4 / IOC4 / PWM4 -- Port T I/O Pin 4
PT4 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 4 or pulse width
modulator (PWM) output 4.
1.7.3.31 PT[3:1] / IOC[3:1] -- Port T I/O Pin [3:1]
PT[3:1] are a general-purpose input or output pins. They can be configured as timer (TIM) channels 3-1.
1.7.3.32 PT0 / IOC0 / PWM0 -- Port T I/O Pin 0
PT0 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 0 or pulse width
modulator (PWM) output 0.
1.7.4 Power Supply Pins
MC9S12P-Family power and ground pins are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE
All VSS pins must be connected together in the application.
1.7.4.1 VDDX[2:1], VSSX[2:1] -- Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All VDDX pins are connected together internally. All VSSX pins are connected together
internally.
1.7.4.2 VDDR -- Power Pin for Internal Voltage Regulator
Power supply input to the internal voltage regulator.
1.7.4.3 VSS3 -- Core Ground Pin
The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current
path is through the VSS3 pin. No static external loading of these pins is permitted.
1.7.4.4 VDDA, VSSA -- Power Supply Pins for ATD and Voltage Regulator
These are the power supply and ground input pins for the analog-to-digital converter and the voltage
regulator.
1.7.4.5 VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog-to-digital converter.
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Freescale Semiconductor 41
Device Overview MC9S12P-Family
1.7.4.6 VSSPLL -- Ground Pin for PLL
This pin provides ground for the oscillator and the phased-locked loop. The voltage supply of nominally
1.8V is derived from the internal voltage regulator.
1.7.4.7 Power and Ground Connection Summary
Table 1-9. Power and Ground Connection Summary
Mnemonic Nominal Description
Voltage
VDDR 5.0 V External power supply to internal voltage
regulator
VDDX[2:1] 5.0 V
VSSX[2:1] 0V External power and ground, supply to pin
5.0 V drivers
VDDA 0V
VSSA Operating voltage and ground for the
0V analog-to-digital converters and the
VRL 5.0 V reference for the internal voltage regulator,
VRH allows the supply voltage to the A/D to be
VSS3 0V bypassed independently.
VSSPLL 0V Reference voltages for the analog-to-digital
converter.
Internal power and ground generated by
internal regulator for the internal core.
Provides operating voltage and ground for
the phased-locked loop. This allows the
supply voltage to the PLL to be bypassed
independently. Internal power and ground
generated by internal regulator.
1.8 System Clock Description
For the system clock description please refer to chapter Chapter 7, "S12 Clock, Reset and Power
Management Unit (S12CPMU) Block Description.
1.9 Modes of Operation
The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.9.2 Low Power Operation.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
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42 Freescale Semiconductor
Device Overview MC9S12P-Family
1.9.1 Chip Configuration Summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-
10). The MODC bit in the MODE register shows the current operating mode and provides limited mode
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET.
Table 1-10. Chip Modes
Chip Modes MODC
Normal single chip 1
Special single chip 0
1.9.1.1 Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
1.9.1.2 Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor 43
Device Overview MC9S12P-Family
1.9.2 Low Power Operation
The MC9S12P has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description
refer to S12CPMU section.
1.10 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 13.5 Security
1.11 Resets and Interrupts
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1 Resets
Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the Section
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Table 1-11. Reset Sources and Vector Locations
Vector Address Reset Source CCR Local Enable
Mask
$FFFE
$FFFE Power-On Reset (POR) None None
$FFFE Low Voltage Reset (LVR)
$FFFE None None
$FFFC External pin RESET
$FFFA Illegal Address Reset None None
Clock monitor reset
COP watchdog reset None None
None OSCE Bit in CPMUOSC register
None CR[2:0] in CPMUCOP register
1.11.2 Interrupt Vectors
Table 1-12 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Section Chapter 4 Interrupt Module (S12SINTV1)) provides an interrupt vector base register (IVBR)
to relocate the vectors.
Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
Vector Address(1) Interrupt Source CCR Local Enable Wake up Wakeup
Mask from STOP from WAIT
Vector base + $F8 Unimplemented instruction trap None
Vector base+ $F6 SWI None None - -
Vector base+ $F4 XIRQ None None
Vector base+ $F2 IRQ X Bit IRQCR (IRQEN) - -
I bit
Yes Yes
Yes Yes
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44 Freescale Semiconductor
Device Overview MC9S12P-Family
Table 1-12. Interrupt Vector Locations (Sheet 2 of 3)
Vector Address(1) Interrupt Source CCR Local Enable Wake up Wakeup
Mask from STOP from WAIT
Vector base+ $F0
RTI timeout interrupt I bit CPMUINT (RTIE) 7.6 Interrupts
Vector base+ $EE
Vector base + $EC TIM timer channel 0 I bit TIE (C0I) No Yes
Vector base+ $EA
Vector base+ $E8 TIM timer channel 1 I bit TIE (C1I) No Yes
Vector base+ $E6
Vector base+ $E4 TIM timer channel 2 I bit TIE (C2I) No Yes
Vector base + $E2
Vector base+ $E0 TIM timer channel 3 I bit TIE (C3I) No Yes
Vector base+ $DE
Vector base+ $DC TIM timer channel 4 I bit TIE (C4I) No Yes
Vector base + $DA
Vector base + $D8 TIM timer channel 5 I bit TIE (C5I) No Yes
Vector base+ $D6
TIM timer channel 6 I bit TIE (C6I) No Yes
Vector base + $D4
Vector base + $D2 TIM timer channel 7 I bit TIE (C7I) No Yes
Vector base + $D0
Vector base + $CE TIM timer overflow I bit TSRC2 (TOF) No Yes
Vector base + $CC TIM Pulse accumulator A overflow I bit PACTL (PAOVI) No Yes
to
TIM Pulse accumulator input edge I bit PACTL (PAI) No Yes
Vector base + $CA
Vector base + $C8 SPI I bit SPICR1 (SPIE, SPTIE) No Yes
Vector base + $C6 SCI I bit SCICR2 Yes Yes
Vector base + $C4
(TIE, TCIE, RIE, ILIE)
to
Vector base + $BC Reserved
Vector base + $BA
Vector base + $B8 ATD I bit ATDCTL2 (ASCIE) Yes Yes
Vector base + $B6
Vector base + $B4 Reserved
Vector base + $B2
Vector base + $B0 Port J I bit PIEJ (PIEJ7-PIEJ6, PIEJ2- Yes Yes
PIEJ0)
Reserved
Oscillator status interrupt I bit CPMUINT (OSCIE) No No
PLL lock interrupt
I bit CPMUINT (LOCKIE) No No
FLASH error
FLASH command Reserved
CAN wake-up I bit FERCNFG (SFDIE, DFDIE) No No
CAN errors
CAN receive I bit FCNFG (CCIE) No Yes
CAN transmit
I bit CANRIER (WUPIE)
I bit CANRIER (CSCIE, OVRIE)
8.4.7 Interrupts
I bit CANRIER (RXFIE)
I bit CANTIER (TXEIE[2:0])
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45 Freescale Semiconductor
Device Overview MC9S12P-Family
Table 1-12. Interrupt Vector Locations (Sheet 3 of 3)
Vector Address(1) Interrupt Source CCR Local Enable Wake up Wakeup
Mask from STOP from WAIT
Vector base + $AE Reserved
to
Vector base + $90
Vector base + $8E Port P interrupt I bit PIEP (PIEP7,PIEP5-PIEP0) Yes Yes
Vector base+ $8C PWM emergency shutdown I bit PWMSDN (PWMIE) No Yes
Vector base + $8A Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Yes
Vector base + $88 Autonomous periodical interrupt I bit CPMUAPICTRL (APIE) Yes Yes
(API)
Vector base + $86 High temperature interrupt I bit CPMUHTCL (HTIE) No Yes
Vector base + $84 ATD compare interrupt I bit ATDCTL2 (ACMPIE) Yes Yes
Vector base + $82 Reserved
Vector base + $80 Spurious interrupt -- None - -
1. 16 bits vector address based
1.11.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section 13.6 Initialization.
1.11.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4 Memory
The RAM arrays are not initialized out of reset.
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46 Freescale Semiconductor
Device Overview MC9S12P-Family
1.12 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See Table 1-13 and Table 1-14 for coding. The FOPT register is
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
Table 1-13. Initial COP Rate Configuration
NV[2:0] in CR[2:0] in
FOPT Register COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-14. Initial WCOP Configuration
NV[3] in WCOP in
FOPT Register COPCTL Register
1 0
0 1
1.13 ATD External Trigger Input Connection
The ATD module includes external trigger inputs ETRIG0 and ETRIG1. The external trigger allows the
user to synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the
external trigger inputs.
Table 1-15. ATD External Trigger Sources
External Trigger Connectivity
Input
PWM channel 1
ETRIG0 PWM channel 3
ETRIG1
Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.
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Freescale Semiconductor 47
Device Overview MC9S12P-Family
1.14 S12CPMU Configuration
The bandgap reference voltage VBG and the output voltage of the temperature sensor VHT can be
connected to the ATD channel SPECIAL17 (see Table 9-15.) using the VSEL (Voltage Access Select Bit)
in CPMUHTCTL register (see Table 7-13.)
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48 Freescale Semiconductor
Chapter 2
Port Integration Module (S12PPIMV1)
Revision History
Rev. No. Date Sections Substantial Change(s)
Affected
(Item No.) (Submitted By)
V01.00 19 Mar 2008 Initial version
V01.01 05 May 2008 Corrected mistakes in Port J register and field names
V01.02 08 Jan 2009 Corrected PERxAD register descriptions.
Minor corrections.
2.1 Introduction
2.1.1 Overview
The S12P Family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This section covers:
Port A and B used as general purpose I/O
Port E associated with the IRQ, XIRQ interrupt inputs
Port T associated with 1 timer module
Port S associated with 1 SCI module
Port M associated with 1 MSCAN and 1 SPI module
Port P connected to the PWM - inputs can be used as an external interrupt source
Port J used as general purpose I/O - inputs can be used as an external interrupt source
Port AD associated with one 10-channel ATD module
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
NOTE
This section assumes the availability of all features (80-pin package option).
Some functions are not available on lower pin count package options. Refer
to the pin-out summary section.
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Freescale Semiconductor 49
Port Integration Module (S12PPIMV1)
2.1.2 Features
The Port Integration Module includes these distinctive registers:
Data registers and data direction registers for Ports A, B, E, T, S, M, P, J and AD when used as
general purpose I/O
Control registers to enable/disable pull devices and select pull-ups/pull-downs on Ports T, S, M, P
and J on per-pin basis
Control registers to enable/disable pull-up devices on Port AD on per-pin basis
Single control register to enable/disable pull-ups on Ports A, B, and E, on per-port basis and on
BKGD pin
Control registers to enable/disable reduced output drive on Ports T, S, M, P, J and AD on per-pin
basis
Single control register to enable/disable reduced output drive on Ports A, B, and E on per-port basis
Control registers to enable/disable open-drain (wired-or) mode on Ports S and M
Interrupt flag register for pin interrupts on Ports P and J
Control register to configure IRQ pin operation
Routing register to support module port relocation
Free-running clock outputs
A standard port pin has the following minimum features:
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
Optional features supported on dedicated pins:
Open drain for wired-or connections
Interrupt inputs with glitch filtering
2.2 External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
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50 Freescale Semiconductor
Port Integration Module (S12PPIMV1)
Table 2-1. Pin Functions and Priorities
Port Pin Name Pin Function I/O Description Pin Function
& Priority(1) after Reset
- BKGD I MODC input during RESET
MODC (2) I/O S12X_BDM communication pin BKGD
A PA[7:0] BKGD I/O General purpose GPIO
GPIO I/O General purpose GPIO
B PB[7:0] GPIO O Free-running clock at core clock rate (ECLK x 2) GPIO
I/O General purpose
E PE[7] ECLKX2 I/O General purpose GPIO
GPIO O Free-running clock at bus clock rate or programmable down-
PE[6:5] GPIO GPIO
PE[4] ECLK scaled bus clock
I/O General purpose
PE[3:2] GPIO I/O General purpose
PE[1] GPIO
PE[0] IRQ I Maskable level- or falling edge-sensitive interrupt
T PT[7:6] GPI I General purpose
PT5 XIRQ I Non-maskable level-sensitive interrupt
GPI I General purpose
PT4 IOC[7:6] I/O Timer Channels 7 - 6
GPIO I/O General purpose
PT[3:1] IOC5 I/O Timer Channel 5
PT0 (PWM5) O Pulse Width Modulator channel 5
VREG_API O VREG Autonomous Periodical Interrupt Clock
S PS[3:2] GPIO I/O General purpose
PS1 IOC4 I/O Timer Channel 4
PS0 (PWM4) O Pulse Width Modulator channel 4
GPIO I/O General purpose
IOC[3:1] I/O Timer Channels 3 - 1
GPIO I/O General purpose
IOC0 I/O Timer Channel 0
(PWM0) O Pulse Width Modulator channel 0
GPIO I/O General purpose
GPIO I/O General purpose
TXD O Serial Communication Interface transmit pin
GPIO I/O General purpose
RXD I Serial Communication Interface receive pin
GPIO I/O General purpose
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Freescale Semiconductor 51
Port Integration Module (S12PPIMV1)
Port Pin Name Pin Function I/O Description Pin Function
& Priority(1) after Reset
M PM5 SCK I/O Serial Peripheral Interface serial clock pin GPIO
GPIO I/O General purpose GPIO
GPIO
PM4 MOSI I/O Serial Peripheral Interface master out/slave in pin GPIO
GPIO I/O General purpose
PM3 SS I/O Serial Peripheral Interface slave select output in master mode,
input in slave mode or master mode.
GPIO I/O General purpose
PM2 MISO I/O Serial Peripheral Interface master in/slave out pin
GPIO I/O General purpose
PM1 TXCAN O MSCAN transmit pin
GPIO I/O General purpose
PM0 RXCAN I MSCAN receive
GPIO I/O General purpose
P PP7 GPIO/KWP7 I/O General purpose; with interrupt
PP5 PWM5 I/O Pulse Width Modulator channel 5; emergency shut-down
GPIO/KWP5 I/O General purpose; with interrupt
PP[4:0] PWM[4:0] O Pulse Width Modulator channel 4 - 0
GPIO/KWP[4:0] I/O General purpose; with interrupt
J PJ[7:6] GPIO/KWJ[7:6] I/O General purpose; with interrupt
PJ[2:0] GPIO/KWJ[2:0] I/O General purpose; with interrupt
AD PAD[9:0] GPIO I/O General purpose
AN[9:0] I ATD analog
1. Signals in brackets denote alternative module routing pins.
2. Function active when RESET asserted.
2.3 Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
2.3.1 Memory Map
Table 2-2 shows the register map of the Port Integration Module.
Table 2-2. Block Memory Map
Port Offset or Register Access Reset Value Section/Page
Address
A 0x0000 PORTA--Port A Data Register R/W 0x00 2.3.3/2-63
B 2.3.4/2-63
R/W 0x00 2.3.5/2-64
0x0001 PORTB--Port B Data Register 2.3.6/2-64
R/W 0x00
0x0002 DDRA--Port A Data Direction Register
R/W 0x00
0x0003 DDRB--Port B Data Direction Register
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52 Freescale Semiconductor
Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Port Offset or Register Access Reset Value Section/Page
Address
0x0004 PIM Reserved R 0x00 2.3.7/2-65
:
0x0007
E 0x0008 PORTE--Port E Data Register R/W(1) 0x00 2.3.8/2-65
R/W1 0x00 2.3.9/2-66
0x0009 DDRE--Port E Data Direction Register
Non-PIM address range(2) - - -
0x000A
:
0x000B
A 0x000C PUCR--Pull-up Up Control Register R/W1 0x50 2.3.10/2-67
B R/W1 0x00 2.3.11/2-68
E 0x000D RDRIV--Reduced Drive Register
- - -
0x000E Non-PIM address range2
:
0x001B
E 0x001C ECLKCTL--ECLK Control Register R/W1 0xC0 / 0x80(3) 2.3.12/2-69
R 0x00 2.3.13/2-69
0x001D PIM Reserved 0x40 2.3.14/2-70
R/W1 0x00 2.3.15/2-70
0x001E IRQCR--IRQ Control Register R -
- -
0x001F PIM Reserved
Non-PIM address range2
0x0020
:
0x023F
T 0x0240 PTT--Port T Data Register R/W 0x00 2.3.16/2-71
R 2.3.17/2-72
0x0241 PTIT--Port T Input Register (4)
0x0242 DDRT--Port T Data Direction Register R/W 0x00 2.3.18/2-73
0x0243 RDRT--Port T Reduced Drive Register R/W 0x00 2.3.19/2-74
0x0244 PERT--Port T Pull Device Enable Register R/W 0x00 2.3.20/2-74
0x0245 PPST--Port T Polarity Select Register R/W 0x00 2.3.21/2-75
0x0246 PIM Reserved R 0x00 2.3.22/2-75
0x0247 Port T Routing Register R/W 0x00 2.3.23/2-76
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Freescale Semiconductor 53
Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Port Offset or Register Access Reset Value Section/Page
Address
S 0x0248 PTS--Port S Data Register R/W 0x00 2.3.24/2-77
0x0249 PTIS--Port S Input Register
0x024A DDRS--Port S Data Direction Register R 4 2.3.25/2-77
0x024B RDRS--Port S Reduced Drive Register
0x024C PERS--Port S Pull Device Enable Register R/W 0x00 2.3.26/2-78
0x024D PTPS--Port S Polarity Select Register
0x024E WOMS--Port S Wired-Or Mode Register R/W 0x00 2.3.27/2-79
0x024F PIM Reserved
R/W 0xFF 2.3.28/2-79
M 0x0250 PTM--Port M Data Register
0x0251 PTIM--Port M Input Register R/W 0x00 2.3.29/2-80
0x0252 DDRM--Port M Data Direction Register
0x0253 RDRM--Port M Reduced Drive Register R/W 0x00 2.3.30/2-80
0x0254 PERM--Port M Pull Device Enable Register
0x0255 PPSM--Port M Polarity Select Register R 0x00 2.3.39/2-86
0x0256 WOMM--Port M Wired-Or Mode Register
0x0257 PIM Reserved R/W 0x00 2.3.32/2-81
P 0x0258 PTP--Port P Data Register R 4 2.3.33/2-82
0x0259 PTIP--Port P Input Register
0x025A DDRP--Port P Data Direction Register R/W 0x00 2.3.34/2-83
0x025B RDRP--Port P Reduced Drive Register
0x025C PERP--Port P Pull Device Enable Register R/W 0x00 2.3.35/2-84
0x025D PTPP--Port P Polarity Select Register
0x025E PIEP--Port P Interrupt Enable Register R/W 0x00 2.3.36/2-85
0x025F PIFP--Port P Interrupt Flag Register
0x0260 PIM Reserved R/W 0x00 2.3.37/2-85
:
0x0267 R/W 0x00 2.3.38/2-86
R 0x00 2.3.39/2-86
R/W 0x00 2.3.40/2-87
R 4 2.3.41/2-88
R/W 0x00 2.3.42/2-88
R/W 0x00 2.3.43/2-89
R/W 0x00 2.3.44/2-90
R/W 0x00 2.3.45/2-90
R/W 0x00 2.3.46/2-91
R/W 0x00 2.3.47/2-91
R 0x00 2.3.48/2-92
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Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Port Offset or Register Access Reset Value Section/Page
Address
J 0x0268 PTJ--Port J Data Register R/W 0x00 2.3.49/2-92
2.3.50/2-93
0x0269 PTIJ--Port J Input Register R 4 2.3.51/2-93
2.3.52/2-94
0x026A DDRJ--Port J Data Direction Register R/W 0x00 2.3.53/2-94
0x00 2.3.54/2-95
0x026B RDRJ--Port J Reduced Drive Register R/W 0xFF 2.3.55/2-95
0x00 2.3.56/2-96
0x026C PERJ--Port J Pull Device Enable Register R/W 0x00 2.3.57/2-96
0x00 2.3.58/2-97
0x026D PPSJ--Port J Polarity Select Register R/W 0x00 2.3.59/2-97
0x00 2.3.60/2-98
0x026E PIEJ--Port J Interrupt Enable Register R/W 0x00 2.3.61/2-98
0x00 2.3.62/2-99
0x026F PIFJ--Port J Interrupt Flag Register R/W 0x00 2.3.62/2-99
0x00 2.3.64/2-100
AD 0x0270 PT0AD--Port AD Data Register R 0x00 2.3.65/2-100
0x00
0x0271 PT1AD--Port AD Data Register R/W 0x00
0x0272 DDR0AD--Port AD Data Direction Register R
0x0273 DDR1AD--Port AD Data Direction Register R/W
0x0274 RDR0AD--Port AD Reduced Drive Register R
0x0275 RDR1AD--Port AD Reduced Drive Register R/W
0x0276 PER0AD--Port AD Pull Up Enable Register R
0x0277 PER1AD--Port AD Pull Up Enable Register R/W
0x0278 PIM Reserved R
:
0x027F
1. Write access not applicable for one or more register bits. Refer to register description.
2. Refer to device memory map to determine related module.
3. Mode dependent.
4. Read always returns logic level on pins.
Register Bit 7 6 5 4 3 2 1 Bit 0
Name PA3 PA2 PA1 PA0
PB3 PB2 PB1 PB0
0x0000 R PA7 PA6 PA5 PA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB3 DDRB2 DDRB1 DDRB0
PORTA W
0x0001 R PB7 PB6 PB5 PB4
PORTB W
0x0002 R DDRA6 DDRA5 DDRA4
DDRA W DDRA7
0x0003 R DDRB6 DDRB5 DDRB4
DDRB W DDRB7
= Unimplemented or Reserved
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Freescale Semiconductor 55
Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name 0 0
0 0
0x0004 R 0 0 0 0 0 0 0 0
0 0
Reserved W PE1
0 PE0
0x0005 R 0 0 0 0 0 0 0
PUPBE
Reserved W RDPB PUPAE
RDPA
0x0006 R 0 0 0 0 0 0 EDIV1
0 EDIV0
Reserved W 0 0
0 0
0x0007 R 0 0 0 0 0 0 0
Reserved W
0x0008 R PE7 PE6 PE5 PE4 PE3 PE2
DDRE6
PORTE W
BKPUE
0x0009 R DDRE5 DDRE4 DDRE3 DDRE2
DDRE W DDRE7
0x000A R Non-PIM Address Range
0x000B W
Non-PIM
Address
Range
0x000C R 0 0 PUPEE 0 0
PUCR W
0x000D R 0 0 0 RDPE 0 0
RDRIV W NCLKX2
0
0x000E R Non-PIM Address Range
0x001B W
Non-PIM
Address
Range
0x001C R DIV16 EDIV4 EDIV3 EDIV2
ECLKCTL W NECLK 0 0 0 0
0x001D R 0
Reserved W
0x001E R 0 0 0 0
IRQCR W IRQE IRQEN
0x001F R 0 0 0 0 0 0
Reserved W
= Unimplemented or Reserved
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Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name
Non-PIM Address Range PTT2
0x0020 R PTIT2
0x023F W DDRT2
Non-PIM RDRT2
Address PERT2
Range PPST2
0x0240 R PTT7 PTT6 PTT5 PTT4 PTT3 0 PTT1 PTT0
PTT W PTIT6 PTIT5 PTIT4 PTIT3 0 PTIT1 PTIT0
PTS2
0x0241 R PTIT7 PTIS2
PTIT W DDRS2
RDRS2
0x0242 R DDRT6 DDRT5 DDRT4 DDRT3 PERS2 DDRT1 DDRT0
DDRT W DDRT7 PPSS2
0x0243 R RDRT6 RDRT5 RDRT4 RDRT3 RDRT1 RDRT0
RDRT W RDRT7
0x0244 R PERT6 PERT5 PERT4 PERT3 PERT1 PERT0
PERT W PERT7
0x0245 R PPST6 PPST5 PPST4 PPST3 PPST1 PPST0
PPST W PPST7 0 0 0 0 0 0
0x0246 R 0
Reserved W
0x0247 R 0 0 PTTRR5 PTTRR4 0 0
PTTRR0
PTTRR W
0x0248 R 0 0 0 0 PTS3 PTS1 PTS0
PTIS1 PTIS0
PTS W
0x0249 R 0 0 0 0 PTIS3
PTIS W
0x024A R 0 0 0 0 DDRS3 DDRS1 DDRS0
RDRS3
DDRS W PERS3
PPSS3
0x024B R 0 0 0 0 RDRS1 RDRS0
RDRS W
0x024C R 0 0 0 0 PERS1 PERS0
PERS W
0x024D R 0 0 0 0 PPSS1 PPSS0
PPSS W
= Unimplemented or Reserved
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Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name WOMS3 WOMS2 WOMS1 WOMS0
0x024E R 0 0 0 0 0 0 0 0
WOMS W PTM3 PTM2 PTM1 PTM0
PTIM3 PTIM2 PTIM1 PTIM0
0x024F R 0 0 0 0
DDRM3 DDRM2 DDRM1 DDRM0
Reserved W RDRM3 RDRM2 RDRM1 RDRM0
PERM3 PERM2 PERM1 PERM0
0x0250 R 0 0 PTM5 PTM4 PPSM3 PPSM2 PPSM1 PPSM0
WOMM3 WOMM2 WOMM1 WOMM0
PTM W
0 0 0 0
0x0251 R 0 0 PTIM5 PTIM4
PTP3 PTP2 PTP1 PTP0
PTIM W PTIP3 PTIP2 PTIP1 PTIP0
0x0252 R 0 0 DDRM5 DDRM4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP3 RDRP2 RDRP1 RDRP0
DDRM W PERP3 PERP2 PERP1 PERP0
PPSP3 PPSP2 PPSP1 PPSP0
0x0253 R 0 0 RDRM5 RDRM4
RDRM W
0x0254 R 0 0 PERM5 PERM4
PERM W
0x0255 R 0 0 PPSM5 PPSM4
PPSM W
0x0256 R 0 0
WOMM5 WOMM4
WOMM W
0x0257 R 0 0 0 0
Reserved W
0x0258 R 0
PTP W PTP7 PTP5 PTP4
0x0259 R PTIP7 0 PTIP5 PTIP4
PTIP W
0x025A R 0
DDRP W DDRP7 DDRP5 DDRP4
0x025B R 0
RDRP W RDRP7 RDRP5 RDRP4
0x025C R 0
PERP W PERP7 PERP5 PERP4
0x025D R 0 PPSP5 PPSP4
PPSP W PPSP7
= Unimplemented or Reserved
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Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name PIEP3
PIFP3
0x025E R 0
PIEP W PIEP7 PIEP5 PIEP4 0 PIEP2 PIEP1 PIEP0
0
0x025F R 0 0
PIFP W PIFP7 PIFP5 PIFP4 0 PIFP2 PIFP1 PIFP0
0 0 0 0
0x0260 R 0 0 0 0 0
0
Reserved W 0
0
0x0261 R 0 0 0 0 0 0 0 0
0
Reserved W 0
0
0x0262 R 0 0 0 0 0 0 0
Reserved W
0x0263 R 0 0 0 0 0 0 0
Reserved W
0x0264 R 0 0 0 0 0 0 0
Reserved W
0x0265 R 0 0 0 0 0 0 0
Reserved W
0x0266 R 0 0 0 0 0 0 0
Reserved W
0x0267 R 0 0 0 0 0 0 0
Reserved W
0x0268 R 0 0
PTJ W PTJ7 PTJ6 PTJ2 PTJ1 PTJ0
PTIJ2 PTIJ1 PTIJ0
0x0269 R PTIJ7 PTIJ6 0 0
PTIJ W
0x026A R 0 0
DDRJ W DDRJ7 DDRJ6 DDRJ2 DDRJ1 DDRJ0
0x026B R 0 0
RDRJ W RDRJ7 RDRJ6 RDRJ2 RDRJ1 RDRJ0
0x026C R 0 0
PERJ W PERJ7 PERJ6 PERJ2 PERJ1 PERJ0
= Unimplemented or Reserved
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Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name
0x026D R 0 0 0
PPSJ W PPSJ7 PPSJ6 PPSJ2 PPSJ1 PPSJ0
0x026E R 0 0 0
PIEJ W PIEJ7 PIEJ6 PIEJ2 PIEJ1 PIEJ0
0x026F R 0 0 0
PIFJ W PIFJ7 PIFJ6 PIFJ2 PIFJ1 PIFJ0
0x0270 R 0 0 0 0 0 0 PT0AD1 PT0AD0
PT0AD W
0x0271 R PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
PT1AD W PT1AD7
0x0272 R 0 0 0 0 0 0 DDR0AD1 DDR0AD0
DDR0AD W
0x0273 R
DDR1AD W DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0
0x0274 R 0 0 0 0 0 0 RDR0AD1 RDR0AD0
RDR0AD W
0x0275 R
RDR1AD W RDR1AD7 RDR1AD6 RDR1AD5 RDR1AD4 RDR1AD3 RDR1AD2 RDR1AD1 RDR1AD0
0x0276 R 0 0 0 0 0 0 PER0AD1 PER0AD0
PER0AD W
0x0277 R
PER1AD W PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
0x0278 R 0 0 0 0 0 0 0 0
Reserved W
0x0279 R 0 0 0 0 0 0 0 0
Reserved W
0x027A R 0 0 0 0 0 0 0 0
Reserved W
0x027B R 0 0 0 0 0 0 0 0
Reserved W
= Unimplemented or Reserved
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Port Integration Module (S12PPIMV1)
Register Bit 7 6 5 4 3 2 1 Bit 0
Name
0x027C R 0 0 0 0 0 0 0 0
Reserved W
0x027D R 0 0 0 0 0 0 0 0
Reserved W
0x027E R 0 0 0 0 0 0 0 0
Reserved W
0x027F R 0 0 0 0 0 0 0 0
Reserved W
= Unimplemented or Reserved
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
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Port Integration Module (S12PPIMV1)
Table 2-3. Pin Configuration Summary
DDR IO RDR PE PS(1) IE(2) Function Pull Device Interrupt
Disabled Disabled
0 x x 0 x 0 Input Pull Up Disabled
Pull Down Disabled
0 x x 1 0 0 Input Disabled Falling edge
Disabled Rising edge
0 x x 1 1 0 Input Pull Up Falling edge
Pull Down Rising edge
0 x x 0 0 1 Input Disabled Disabled
Disabled Disabled
0 x x 0 1 1 Input Disabled Disabled
Disabled Disabled
0 x x 1 0 1 Input Disabled Falling edge
Disabled Rising edge
0 x x 1 1 1 Input Disabled Falling edge
Disabled Rising edge
1 0 0 x x 0 Output, full drive to 0
1 1 0 x x 0 Output, full drive to 1
1 0 1 x x 0 Output, reduced drive to 0
1 1 1 x x 0 Output, reduced drive to 1
1 0 0 x 0 1 Output, full drive to 0
1 1 0 x 1 1 Output, full drive to 1
1 0 1 x 0 1 Output, reduced drive to 0
1 1 1 x 1 1 Output, reduced drive to 1
1. Always "0" on Port A, B, E, and AD.
2. Applicable only on Port P and J.
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
NOTE
Figure of port data registers also display the alternative functions if
applicable on the related pin as defined in Table 2-1. Names in brackets
denote the availability of the function when using a specific routing option.
NOTE
Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
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Port Integration Module (S12PPIMV1)
2.3.3 Port A Data Register (PORTA)
Address 0x0000 Access: User read/write(1)
7 6 5 4 3 2 1 0
R
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-1. Port A Data Register (PORTA)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field Table 2-4. PORTA Register Field Descriptions
7-0 Description
PA
Port A general purpose input/output data--Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
2.3.4 Port B Data Register (PORTB)
Address 0x0001 Access: User read/write(1)
7 6 5 4 3 2 1 0
R
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-2. Port B Data Register (PORTB)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field Table 2-5. PORTB Register Field Descriptions
7-0 Description
PB
Port B general purpose input/output data--Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
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Port Integration Module (S12PPIMV1)
2.3.5 Port A Data Direction Register (DDRA)
Address 0x0002 Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-3. Port A Data Direction Register (DDRA)
1. Read: Anytime
Write: Anytime
Table 2-6. DDRA Register Field Descriptions
Field Description
7-0 Port A Data Direction--
DDRA This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.6 Port B Data Direction Register (DDRB)
Address 0x0003 Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-4. Port B Data Direction Register (DDRB)
1. Read: Anytime
Write: Anytime
Table 2-7. DDRB Register Field Descriptions
Field Description
7-0 Port B Data Direction--
DDRB This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Port Integration Module (S12PPIMV1)
2.3.7 PIM Reserved Register
Address 0x0004 to 0x0007 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-5. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.8 Port E Data Register (PORTE)
Address 0x0008 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PE6 PE5 PE4 PE3 PE2 PE1 PE0
PE7
W
Altern. ECLKX2 -- -- ECLK -- -- IRQ XIRQ
Function
Reset 0 0 0 0 0 0 --(2) --2
= Unimplemented or Reserved
Figure 2-6. Port E Data Register (PORTE)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
Table 2-8. PORTE Register Field Descriptions
Field Description
7 Port E general purpose input/output data--Data Register, ECLKX2 output
PE When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
6-5, 3-2 The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
PE
Port E general purpose input/output data--Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
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Port Integration Module (S12PPIMV1)
Table 2-8. PORTE Register Field Descriptions (continued)
Field Description
4 Port E general purpose input/output data--Data Register, ECLK output
PE When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The ECLK output function takes precedence over the general purpose I/O function if enabled.
1 Port E general purpose input data and interrupt--Data Register, IRQ input.
PE This pin can be used as general purpose and IRQ input.
0 Port E general purpose input data and interrupt--Data Register, XIRQ input.
PE This pin can be used as general purpose and XIRQ input.
2.3.9 Port E Data Direction Register (DDRE)
Address 0x0009 Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0
W 0
Reset 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-7. Port E Data Direction Register (DDRE)
1. Read: Anytime
Write: Anytime
Table 2-9. DDRE Register Field Descriptions
Field Description
7-2 Port E Data Direction--
DDRE This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
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2.3.10 Port Integration Module (S12PPIMV1)
Ports A, B, E, BKGD pin Pull-up Control Register (PUCR)
Address 0x000C Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 PUPAE
PUPBE 0
BKPUE PUPEE
W
Reset 0 1 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-8. Ports ABEK, BKGD pin Pull-up Control Register (PUCR)
1. Read:Anytime in single-chip modes.
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
Table 2-10. PUCR Register Field Descriptions
Field Description
6 BKGD pin pull-up Enable--Enable pull-up device on pin
BKPUE This bit configures whether a pull-up device is activated, if the pin is used as input. If a pin is used as output this bit
has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
4 Port E Pull-up Enable--Enable pull-up devices on all port input pins except pins 5 and 6
PUPEE This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
Pins 5 and 6 have pull-down devices enabled only during reset. This bit has no effect on these pins.
1 Pull-up device enabled
0 Pull-up device disabled
1 Port B Pull-up Enable--Enable pull-up devices on all port input pins
PUPBE This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
0 1 Pull-up device enabled
PUPAE 0 Pull-up device disabled
Port A Pull-up Enable--Enable pull-up devices on all port input pins
This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
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Port Integration Module (S12PPIMV1)
2.3.11 Ports A, B, E Reduced Drive Register (RDRIV)
Address 0x000D Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0
RDPE RDPB RDPA
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-9. Ports ABEK Reduced Drive Register (RDRIV)
1. Read: Anytime
Write: Anytime
Table 2-11. RDRIV Register Field Descriptions
Field Description
4 Port E reduced drive--Select reduced drive for output port
RDPE This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 1 Reduced drive selected (approx. 1/5 of the full drive strength)
RDPE 0 Full drive strength enabled
Port B reduced drive--Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
0 1 Reduced drive selected (approx. 1/5 of the full drive strength)
RDPA 0 Full drive strength enabled
Port A reduced drive--Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
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Port Integration Module (S12PPIMV1)
2.3.12 ECLK Control Register (ECLKCTL)
Address 0x001C Access: User read/write(1)
7 6 5 4 3 2 1 0
R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
Mode 1 0 0 0 0 0 0
Reset: Depen-
1 0 0 0 0 0 0
Special dent
single-chip 0 1 0 0 0 0 0 0
Normal 1
single-chip
= Unimplemented or Reserved
Figure 2-10. ECLK Control Register (ECLKCTL)
1. Read: Anytime
Write: Anytime
Table 2-12. ECLKCTL Register Field Descriptions
Field Description
7 No ECLK--Disable ECLK output
NECLK This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate of equivalent to
the internal bus clock.
1 ECLK disabled
0 ECLK enabled
6 No ECLKX2--Disable ECLKX2 output
NCLKX2 This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
5 1 ECLKX2 disabled
DIV16 0 ECLKX2 enabled
Free-running ECLK pre-divider--Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
4-0 1 Divider enabled: ECLK rate = EDIV rate divided by 16
EDIV 0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider--Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
2.3.13 PIM Reserved Register
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Port Integration Module (S12PPIMV1)
Address 0x001D Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-11. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.14 IRQ Control Register (IRQCR)
Address 0x001E Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
IRQE IRQEN
W
Reset 0 1 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-12. IRQ Control Register (IRQCR)
1. Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Table 2-13. IRQCR Register Field Descriptions
Field Description
7 IRQ select edge sensitive only--
IRQE Special mode: Read or write anytime.
Normal mode: Read anytime, write once.
6 1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
IRQEN and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ pin configured for low level recognition
IRQ enable--
Read or write anytime.
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
2.3.15 PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Writing to this register when in special modes can alter the pin functionality.
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Port Integration Module (S12PPIMV1)
Address 0x001F Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-13. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.16 Port T Data Register (PTT)
Address 0x0240 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
PTT7
W
Altern. IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
Function -- -- (PWM5) (PWM4) -- -- -- (PWM0)
--
-- -- VREG_API -- -- -- 0 --
0
Reset 0 0 0 0 0 0
Figure 2-14. Port T Data Register (PTT)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
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Port Integration Module (S12PPIMV1)
Table 2-14. PTT Register Field Descriptions
Field Description
7-6, 3-1 Port T general purpose input/output data--Data Register, TIM output
PTT When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The TIM output function takes precedence over the general purpose I/O function if the related channel is enabled.
5 Port T general purpose input/output data--Data Register, TIM output, routed PWM output, VREG_API output
PTT When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The TIM output function takes precedence over the routed PWM, VREG_API function and the general purpose
I/O function if the related channel is enabled.
The routed PWM function takes precedence over VREG_API and the general purpose I/O function if the related
channel is enabled.
The VREG_API takes precedence over the general purpose I/O function if enabled.
4,0 Port T general purpose input/output data--Data Register, TIM output, routed PWM output
PTT When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the
related channel is enabled.
The routed PWM function takes precedence over the general purpose I/O function if the related channel is
enabled.
2.3.17 Port T Input Register (PTIT)
Address 0x0241 Access: User read(1)
7 6 5 4 3 2 1 0
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset u u u u u u u u
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-15. Port T Input Register (PTIT)
1. Read: Anytime
Write:Never, writes to this register have no effect.
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Port Integration Module (S12PPIMV1)
Field Table 2-15. PTIT Register Field Descriptions
7-0 Description
PTIT
Port T input data--
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.18 Port T Data Direction Register (DDRT)
Address 0x0242 Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-16. Port T Data Direction Register (DDRT)
1. Read: Anytime
Write: Anytime
Table 2-16. DDRT Register Field Descriptions
Field Description
7-6, 3-1 Port T data direction--
DDRT This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
5 1 Associated pin is configured as output
DDRT 0 Associated pin is configured as input
Port T data direction--
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to
be an output if enabled. In these cases the data direction bit will not change.
4,0 1 Associated pin is configured as output
DDRT 0 Associated pin is configured as input
Port T data direction--
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Port Integration Module (S12PPIMV1)
2.3.19 Port T Reduced Drive Register (RDRT)
Address 0x0243 Access: User read/write(1)
7 6 5 4 3 2 1 0
R RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-17. Port T Reduced Drive Register (RDRT)
1. Read: Anytime
Write: Anytime
Table 2-17. RDRT Register Field Descriptions
Field Description
7-0 Port T reduced drive--Select reduced drive for output pin
RDRT This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
2.3.20 Port T Pull Device Enable Register (PERT)
Address 0x0244 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-18. Port T Pull Device Enable Register (PERT)
1. Read: Anytime
Write: Anytime
Table 2-18. PERT Register Field Descriptions
Field Description
7-0 Port T pull device enable--Enable pull device on input pin
PERT This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
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Port Integration Module (S12PPIMV1)
2.3.21 Port T Polarity Select Register (PPST)
Address 0x0245 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W 0
Reset 0 0 0 0 0 0 0
Figure 2-19. Port T Polarity Select Register (PPST)
1. Read: Anytime
Write: Anytime
Table 2-19. PPST Register Field Descriptions
Field Description
7-0 Port T pull device select--Configure pull device polarity on input pin
PPST This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device is selected
0 A pull-up device is selected
2.3.22 PIM Reserved Register
Address 0x0246 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-20. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
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Port Integration Module (S12PPIMV1)
2.3.23 Port T Routing Register (PTTRR)
Address 0x0247 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PTTRR0
PTTRR5 PTTRR4
W
Routing -- -- PWM5 PWM4 -- -- -- PWM0
Option
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-21. Port T Routing Register (PTTRR)
1. Read: Anytime
Write: Anytime
This register configures the re-routing of PWM channels on alternative pins on Port T.
Table 2-20. Port T Routing Register Field Descriptions
Field Description
5 Port T data direction--
PTTRR This register controls the routing of PWM channel 5.
4 1 PWM5 routed to PT5
PTTRR 0 PWM5 routed to PP5
Port T data direction--
This register controls the routing of PWM channel 4.
0 1 PWM4 routed to PT4
PTTRR 0 PWM4 routed to PP4
Port T data direction--
This register controls the routing of PWM channel 0.
1 PWM0 routed to PT0
0 PWM0 routed to PP0
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Port Integration Module (S12PPIMV1)
2.3.24 Port S Data Register (PTS)
Address 0x0248 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
PTS3 PTS2 PTS1 PTS0
W
Altern. -- -- -- -- -- -- TXD RXD
Function 0 0
Reset 0 0 0 0 0 0
Figure 2-22. Port S Data Register (PTS)
1. Read: Anytime The data source is depending on the data direction value.
Write: Anytime
Field Table 2-21. PTS Register Field Descriptions
3-2
PTS Description
1 Port S general purpose input/output data--Data Register
PTS When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
0 If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
PTS pin input state is read.
Port S general purpose input/output data--Data Register, SCI TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The SCI function takes precedence over the general purpose I/O function if enabled.
Port S general purpose input/output data--Data Register, SCI RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The SCI function takes precedence over the general purpose I/O function if enabled.
2.3.25 Port S Input Register (PTIS)
Address 0x0249 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0
W
Reset u u u u u u u u
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-23. Port S Input Register (PTIS)
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Port Integration Module (S12PPIMV1)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Field Table 2-22. PTIS Register Field Descriptions
3-0 Description
PTIS
Port S input data--
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.26 Port S Data Direction Register (DDRS)
Address 0x024A Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
DDRS3 DDRS2 DDRS1 DDRS0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-24. Port S Data Direction Register (DDRS)
1. Read: Anytime
Write: Anytime
Table 2-23. DDRS Register Field Descriptions
Field Description
3-2 Port S data direction--
DDRS This bit determines whether the associated pin is an input or output.
1 1 Associated pin is configured as output
DDRS 0 Associated pin is configured as input
Port S data direction--
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
0 1 Associated pin is configured as output
DDRS 0 Associated pin is configured as input
Port S data direction--
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Port Integration Module (S12PPIMV1)
2.3.27 Port S Reduced Drive Register (RDRS)
Address 0x024B Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
RDRS3 RDRS2 RDRS1 RDRS0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-25. Port S Reduced Drive Register (RDRS)
1. Read: Anytime
Write: Anytime
Table 2-24. RDRS Register Field Descriptions
Field Description
3-0 Port S reduced drive--Select reduced drive for output pin
RDRS This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
2.3.28 Port S Pull Device Enable Register (PERS)
Address 0x024C Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
PERS3 PERS2 PERS1 PERS0
W
Reset 0 0 0 0 1 1 1 1
Figure 2-26. Port S Pull Device Enable Register (PERS)
1. Read: Anytime
Write: Anytime
Table 2-25. PERS Register Field Descriptions
Field Description
3-0 Port S pull device enable--Enable pull device on input pin or wired-or output pin
PERS This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
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Port Integration Module (S12PPIMV1)
2.3.29 Port S Polarity Select Register (PPSS)
Address 0x024D Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
PPSS3 PPSS2 PPSS1 PPSS0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-27. Port S Polarity Select Register (PPSS)
1. Read: Anytime
Write: Anytime
Table 2-26. PPSS Register Field Descriptions
Field Description
3-0 Port S pull device select--Configure pull device polarity on input pin
PPSS This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device is selected
0 A pull-up device is selected
2.3.30 Port S Wired-Or Mode Register (WOMS)
Address 0x024E Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0
WOMS3 WOMS2 WOMS1 WOMS0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-28. Port S Wired-Or Mode Register (WOMS)
1. Read: Anytime
Write: Anytime
Table 2-27. WOMS Register Field Descriptions
Field Description
3-0 Port S wired-or mode--Enable open-drain functionality on output pin
WOMS This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic "0" is driven active
low while a logic "1" remains undriven. This allows a multipoint connection of several serial modules. The bit has no
influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
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Port Integration Module (S12PPIMV1)
2.3.31 PIM Reserved Register
Address 0x024F Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-29. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.32 Port M Data Register (PTM)
Address 0x0250 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
W
Altern. -- -- SCK MOSI SS MISO TXCAN RXCAN
Function 0 0
Reset 0 0 0 0 0 0
Figure 2-30. Port M Data Register (PTM)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field Table 2-28. PTM Register Field Descriptions
5
Description
PTM
Port M general purpose input/output data--Data Register, SPI SCK input/output
4 When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
PTM purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The SPI function takes precedence over the general purpose I/O function if enabled.
Port M general purpose input/output data--Data Register, SPI MOSI input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The SPI function takes precedence over the general purpose I/O function if enabled.
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Port Integration Module (S12PPIMV1)
Table 2-28. PTM Register Field Descriptions (continued)
Field Description
3 Port M general purpose input/output data--Data Register, SPI SS input/output
PTM When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
2 The SPI function takes precedence over the general purpose I/O function if enabled.
PTM
Port M general purpose input/output data--Data Register, SPI MISO input/output
1 When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
PTM purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The SPI function takes precedence over the general purpose I/O function if enabled.
Port M general purpose input/output data--Data Register, CAN TXCAN output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
0 The CAN function takes precedence over the general purpose I/O function if enabled.
PTM
Port M general purpose input/output data--Data Register, CAN RXCAN input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The CAN function takes precedence over the general purpose I/O function if enabled.
2.3.33 Port M Input Register (PTIM)
Address 0x0251 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
W
Reset u u u u u u u u
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-31. Port M Input Register (PTIM)
1. Read: Anytime
Write:Never, writes to this register have no effect.
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Port Integration Module (S12PPIMV1)
Table 2-29. PTIM Register Field Descriptions
Field Description
5-0 Port M input data--
PTIM A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.34 Port M Data Direction Register (DDRM)
Address 0x0252 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-32. Port M Data Direction Register (DDRM)
1. Read: Anytime
Write: Anytime
Table 2-30. DDRM Register Field Descriptions
Field Description
5 Port M data direction--
DDRM This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
4 1 Associated pin is configured as output
DDRM 0 Associated pin is configured as input
Port M data direction--
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
3 1 Associated pin is configured as output
DDRM 0 Associated pin is configured as input
Port M data direction--
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Port Integration Module (S12PPIMV1)
Table 2-30. DDRM Register Field Descriptions (continued)
Field Description
2 Port M data direction--
DDRM This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 1 Associated pin is configured as output
DDRM 0 Associated pin is configured as input
Port M data direction--
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an output. In this case the data direction bit will not change.
0 1 Associated pin is configured as output
DDRM 0 Associated pin is configured as input
Port M data direction--
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an input. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.35 Port M Reduced Drive Register (RDRM)
Address 0x0253 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-33. Port M Reduced Drive Register (RDRM)
1. Read: Anytime
Write: Anytime
Table 2-31. RDRM Register Field Descriptions
Field Description
5-0 Port M reduced drive--Select reduced drive for output pin
RDRM This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
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Port Integration Module (S12PPIMV1)
2.3.36 Port M Pull Device Enable Register (PERM)
Address 0x0254 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-34. Port M Pull Device Enable Register (PERM)
1. Read: Anytime
Write: Anytime
Table 2-32. PERM Register Field Descriptions
Field Description
5-0 Port M pull device enable--Enable pull device on input pin or wired-or output pin
PERM This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
2.3.37 Port M Polarity Select Register (PPSM)
Address 0x0255 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-35. Port M Polarity Select Register (PPSM)
1. Read: Anytime
Write: Anytime
Table 2-33. PPSM Register Field Descriptions
Field Description
5-0 Port M pull device select--Configure pull device polarity on input pin
PPSM This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
If CAN is active the selection of a pull-down device on the RXCAN input will have no effect.
1 A pull-down device is selected
0 A pull-up device is selected
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Port Integration Module (S12PPIMV1)
2.3.38 Port M Wired-Or Mode Register (WOMM)
Address 0x0256 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0
WOMM5 WOMM4 WOMM3 WOMM2
WOMM1 WOMM0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-36. Port M Wired-Or Mode Register (WOMM)
1. Read: Anytime
Write: Anytime
Table 2-34. WOMM Register Field Descriptions
Field Description
5-0 Port M wired-or mode--Enable open-drain functionality on output pin
WOMM This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic "0" is driven active
low while a logic "1" remains undriven. This allows a multipoint connection of several serial modules. The bit has no
influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
2.3.39 PIM Reserved Register
Address 0x0257 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-37. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
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Port Integration Module (S12PPIMV1)
2.3.40 Port P Data Register (PTP)
Address 0x0258 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0
PTP7 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
Altern. -- -- PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
Function 0 0
Reset 0 0 0 0 0 0
Figure 2-38. Port P Data Register (PTP)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field Table 2-35. PTP Register Field Descriptions
7
Description
PTP
Port P general purpose input/output data--Data Register, pin interrupt input/output
5 The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
PTP driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
4-0 pin input state is read.
PTP
Pin interrupts can be generated if enabled in input or output mode.
Port P general purpose input/output data--Data Register, PWM input/output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The PWM function takes precedence over the general purpose I/O function if the related channel or the
emergency shut-down feature is enabled.
Pin interrupts can be generated if enabled in input or output mode.
Port P general purpose input/output data--Data Register, PWM output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
The PWM function takes precedence over the general purpose I/O function if the related channel is enabled.
Pin interrupts can be generated if enabled in input or output mode.
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Port Integration Module (S12PPIMV1)
2.3.41 Port P Input Register (PTIP)
Address 0x0259 Access: User read(1)
7 6 5 4 3 2 1 0
R PTIP7 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
Reset u u u u u u u u
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-39. Port P Input Register (PTIP)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Field Table 2-36. PTIP Register Field Descriptions
7,5-0 Description
PTIP
Port P input data--
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.42 Port P Data Direction Register (DDRP)
Address 0x025A Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRP7 0
W 0
Reset DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
0 0 0 0 0 0 0
Figure 2-40. Port P Data Direction Register (DDRP)
1. Read: Anytime
Write: Anytime
Table 2-37. DDRP Register Field Descriptions
Field Description
7 Port P data direction--
DDRP This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Table 2-37. DDRP Register Field Descriptions (continued)
Field Description
5 Port P data direction--
DDRP This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the emergency shut-down feature is enabled
this pin is an input. In this case the data direction bit will not change.
4-0 1 Associated pin is configured as output
DDRP 0 Associated pin is configured as input
Port P data direction--
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.43 Port P Reduced Drive Register (RDRP)
Address 0x025B Access: User read/write(1)
7 6 5 4 3 2 1 0
R RDRP7 0
W 0
Reset RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
0 0 0 0 0 0 0
Figure 2-41. Port P Reduced Drive Register (RDRP)
1. Read: Anytime
Write: Anytime
Table 2-38. RDRP Register Field Descriptions
Field Description
7,5-0 Port P reduced drive--Select reduced drive for output pin
RDRP This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
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Port Integration Module (S12PPIMV1)
2.3.44 Port P Pull Device Enable Register (PERP)
Address 0x025C Access: User read/write(1)
7 6 5 4 3 2 1 0
R PPSP7 0
W 0
Reset PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
0 0 0 0 0 0 0
Figure 2-42. Port P Pull Device Enable Register (PERP)
1. Read: Anytime
Write: Anytime
Table 2-39. PERP Register Field Descriptions
Field Description
7,5-0 Port P pull device enable--Enable pull device on input pin
PERP This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
2.3.45 Port P Polarity Select Register (PPSP)
Address 0x025D Access: User read/write(1)
7 6 5 4 3 2 1 0
R PPSP7 0
W 0
Reset PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
0 0 0 0 0 0 0
Figure 2-43. Port P Polarity Select Register (PPSP)
1. Read: Anytime
Write: Anytime
Table 2-40. PPSP Register Field Descriptions
Field Description
7,5-0 Port P pull device select--Configure pull device and pin interrupt edge polarity on input pin
PPSP This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device is selected; rising edge selected
0 A pull-up device is selected; falling edge selected
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Port Integration Module (S12PPIMV1)
2.3.46 Port P Interrupt Enable Register (PIEP)
Read: Anytime. Access: User read/write(1)
Address 0x025E
7 6 5 4 3 2 1 0
R PIEP7 0
W 0
Reset PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
0 0 0 0 0 0 0
Figure 2-44. Port P Interrupt Enable Register (PIEP)
1. Read: Anytime
Write: Anytime
Field Table 2-41. PIEP Register Field Descriptions
7,5-0 Description
PIEP
Port P interrupt enable--
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.3.47 Port P Interrupt Flag Register (PIFP)
Address 0x025F Access: User read/write(1)
7 6 5 4 3 2 1 0
R PIFP7 0
W 0
Reset PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
0 0 0 0 0 0 0
Figure 2-45. Port P Interrupt Flag Register (PIFP)
1. Read: Anytime
Write: Anytime
Field Table 2-42. PIFP Register Field Descriptions
7,5-0 Description
PIFP
Port P interrupt flag--
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic "1" to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
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Freescale Semiconductor 91
Port Integration Module (S12PPIMV1)
2.3.48 PIM Reserved Registers
Address 0x0260-0x267 Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-46. PIM Reserved Registers
1. Read: Always reads 0x00
Write: Unimplemented
2.3.49 Port J Data Register (PTJ)
Address 0x0268 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0
PTJ7 PTJ6 PTJ2 PTJ1 PTJ0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-47. Port J Data Register (PTJ)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Table 2-43. PTJ Register Field Descriptions
Field Description
7-6, 2-0 Port J general purpose input/output data--Data Register, pin interrupt input/output
PTJ The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Pin interrupts can be generated if enabled in input or output mode.
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92 Freescale Semiconductor
Port Integration Module (S12PPIMV1)
2.3.50 Port J Input Register (PTIJ)
Address 0x0269 Access: User read(1)
7 6 5 4 3 2 1 0
R PTIJ7 PTIJ6 0 0 0 PTIJ2 PTIJ1 PTIJ0
W
Reset u u u u u u u u
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-48. Port J Input Register (PTIJ)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Table 2-44. PTIJ Register Field Descriptions
Field Description
7-6, 2-0 Port J input data--
PTIJ A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.51 Port J Data Direction Register (DDRJ)
Address 0x026A Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDRJ7 0 0 0
W 0
Reset DDRJ6 DDRJ2 DDRJ1 DDRJ0
0 0 0 0 0 0 0
Figure 2-49. Port J Data Direction Register (DDRJ)
1. Read: Anytime
Write: Anytime
Table 2-45. DDRJ Register Field Descriptions
Field Description
7-6, 2-0 Port J data direction--
DDRJ This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
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Freescale Semiconductor 93
Port Integration Module (S12PPIMV1)
2.3.52 Port J Reduced Drive Register (RDRJ)
Address 0x026B Access: User read/write(1)
7 6 5 4 3 2 1 0
R RDRJ7 0 0 0
W 0
Reset RDRJ6 RDRJ2 RDRJ1 RDRJ0
0 0 0 0 0 0 0
Figure 2-50. Port J Reduced Drive Register (RDRJ)
1. Read: Anytime
Write: Anytime
Table 2-46. RDRJ Register Field Descriptions
Field Description
7-6, 2-0 Port J reduced drive--Select reduced drive for output pin
RDRJ This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
2.3.53 Port J Pull Device Enable Register (PERJ)
Address 0x026C Access: User read/write(1)
7 6 5 4 3 2 1 0
R PERJ7 0 0 0
W 1
Reset PERJ6 PERJ2 PERJ1 PERJ0
1 0 0 0 1 1 1
Figure 2-51. Port J Pull Device Enable Register (PERJ)
1. Read: Anytime
Write: Anytime
Table 2-47. PERJ Register Field Descriptions
Field Description
7-6, 2-0 Port J pull device enable--Enable pull device on input pin
PERJ This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
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94 Freescale Semiconductor
Port Integration Module (S12PPIMV1)
2.3.54 Port J Polarity Select Register (PPSJ)
Address 0x026D Access: User read/write(1)
7 6 5 4 3 2 1 0
R PPSJ7 0 0 0
W 0
Reset PPSJ6 PPSJ2 PPSJ1 PPSJ0
0 0 0 0 0 0 0
Figure 2-52. Port J Polarity Select Register (PPSJ)
1. Read: Anytime
Write: Anytime
Table 2-48. PPSJ Register Field Descriptions
Field Description
7-6, 2-0 Port J pull device select--Configure pull device and pin interrupt edge polarity on input pin
PPSJ This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device is selected; rising edge selected
0 A pull-up device is selected; falling edge selected
2.3.55 Port J Interrupt Enable Register (PIEJ)
Read: Anytime. Access: User read/write(1)
Address 0x026E
7 6 5 4 3 2 1 0
R PIEJ7 0 0 0
W 0
Reset PIEJ6 PIEJ2 PIEJ1 PIEJ0
0 0 0 0 0 0 0
Figure 2-53. Port J Interrupt Enable Register (PIEJ)
1. Read: Anytime
Write: Anytime
Table 2-49. PIEJ Register Field Descriptions
Field Description
7-6, 2-0 Port J interrupt enable--
PIEJ This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
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Freescale Semiconductor 95
Port Integration Module (S12PPIMV1)
2.3.56 Port J Interrupt Flag Register (PIFJ)
Address 0x026F Access: User read/write(1)
7 6 5 4 3 2 1 0
R PIFJ7 0 0 0
W 0
Reset PIFJ6 PIFJ2 PIFJ1 PIFJ0
0 0 0 0 0 0 0
Figure 2-54. Port J Interrupt Flag Register (PIFJ)
1. Read: Anytime
Write: Anytime
Table 2-50. PIFJ Register Field Descriptions
Field Description
7-6, 2-0 Port J interrupt flag--
PIFJ The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic "1" to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.3.57 Port AD Data Register (PT0AD)
Address 0x0270 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
PT0AD1 PT0AD0
W
Altern. -- -- -- -- -- -- AN9 AN8
Function
Reset 0 0 0 0 0 0 0 0
Figure 2-55. Port AD Data Register (PT0AD)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Table 2-51. PT0AD Register Field Descriptions
Field Description
1-0 Port AD general purpose input/output data--Data Register, ATD AN analog input
PT0AD When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
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Port Integration Module (S12PPIMV1)
2.3.58 Port AD Data Register (PT1AD)
Address 0x0271 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
PT1AD7
W
Altern. AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Function
Reset 0 0 0 0 0 0 0 0
Figure 2-56. Port AD Data Register (PT1AD)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Table 2-52. PT1AD Register Field Descriptions
Field Description
7-0 Port AD general purpose input/output data--Data Register, ATD AN analog input
PT1AD When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
2.3.59 Port AD Data Direction Register (DDR0AD)
Address 0x0272 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DDR0AD1 DDR0AD0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-57. Port AD Data Direction Register (DDR0AD)
1. Read: Anytime
Write: Anytime
Table 2-53. DDR0AD Register Field Descriptions
Field Description
1-0 Port AD data direction--
DDR0AD This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level "1".
1 Associated pin is configured as output
0 Associated pin is configured as input
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Freescale Semiconductor 97
Port Integration Module (S12PPIMV1)
2.3.60 Port AD Data Direction Register (DDR1AD)
Address 0x0273 Access: User read/write(1)
7 6 5 4 3 2 1 0
R DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0
DDR1AD7
W
Reset 0 0 0 0 0 0 0 0
Figure 2-58. Port AD Data Direction Register (DDR1AD)
1. Read: Anytime
Write: Anytime
Table 2-54. DDR1AD Register Field Descriptions
Field Description
7-0 Port AD data direction--
DDR1AD This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level "1".
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.61 Port AD Reduced Drive Register (RDR0AD)
Address 0x0274 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
RDR0AD1 RDR0AD0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-59. Port AD Reduced Drive Register (RDR0AD)
1. Read: Anytime
Write: Anytime
Table 2-55. RDR0AD Register Field Descriptions
Field Description
1-0 Port AD reduced drive--Select reduced drive for output pin
RDR0AD This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
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Port Integration Module (S12PPIMV1)
2.3.62 Port AD Reduced Drive Register (RDR1AD)
Address 0x0275 Access: User read/write(1)
7 6 5 4 3 2 1 0
R RDR1AD6 RDR1AD5 RDR1AD4 RDR1AD3 RDR1AD2 RDR1AD1 RDR1AD0
RDR1AD7
W
Reset 0 0 0 0 0 0 0 0
Figure 2-60. Port AD Reduced Drive Register (RDR1AD)
1. Read: Anytime
Write: Anytime
Table 2-56. RDR1AD Register Field Descriptions
Field Description
7-0 Port AD reduced drive--Select reduced drive for output pin
RDR1AD This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
2.3.63 Port AD Pull Up Enable Register (PER0AD)
Address 0x0276 Access: User read/write(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
PER0AD1 PER0AD0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-61. Port AD Pull Up Enable Register (PER0AD)
1. Read: Anytime
Write: Anytime
Table 2-57. PER0AD Register Field Descriptions
Field Description
1-0 Port AD pull-up enable--Enable pull-up device on input pin
PER0AD This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect.
1 Pull device enabled
0 Pull device disabled
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Freescale Semiconductor 99
Port Integration Module (S12PPIMV1)
2.3.64 Port AD Pull Up Enable Register (PER1AD)
Address 0x0277 Access: User read/write(1)
7 6 5 4 3 2 1 0
R PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0
PER1AD7
W
Reset 0 0 0 0 0 0 0 0
Figure 2-62. Port AD Pull Up Enable Register (PER1AD)
1. Read: Anytime
Write: Anytime
Table 2-58. PER1AD Register Field Descriptions
Field Description
7-0 Port AD pull-up enable--Enable pull-up device on input pin
PER1AD This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect.
1 Pull device enabled
0 Pull device disabled
2.3.65 PIM Reserved Registers
Address 0x0278-0x27F Access: User read(1)
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-63. PIM Reserved Registers
1. Read: Always reads 0x00
Write: Unimplemented
2.4 Functional Description
2.4.1 General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output or input of a peripheral module.
2.4.2 Registers
A set of configuration registers is common to all ports with exception of the ATD port (Table 2-59). All
registers can be written at any time, however a specific configuration might not become active.
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Port Integration Module (S12PPIMV1)
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
Table 2-59. Register availability per port(1)
Port Data Input Data Reduced Pull Polarity Wired- Interrupt Interrupt Routing
Direction Drive Enable Select Or Mode Enable Flag
-
A yes - yes yes yes - - - - -
-
B yes - yes - - - - yes
-
E yes - yes - - - - yes
-
T yes yes yes yes yes yes - - - -
-
S yes yes yes yes yes yes yes - -
M yes yes yes yes yes yes yes - -
P yes yes yes yes yes yes - yes yes
J yes yes yes yes yes yes - yes yes
AD yes - yes yes yes - - - -
1. Each cell represents one register with individual configuration bits
2.4.2.1 Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to "0".
If the data direction register bits are set to logic level "1", the contents of the data register is returned. This
is independent of any other configuration (Figure 2-64).
2.4.2.2 Input register (PTIx)
This register is read-only and always returns the buffered state of the pin (Figure 2-64).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as an general purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-101).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
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Freescale Semiconductor 101
Port Integration Module (S12PPIMV1)
PTI
0
1
PT 0 PIN
1
DDR 0
1
data out
Module output enable
module enable
Figure 2-64. Illustration of I/O pin functionality
2.4.2.4 Reduced drive register (RDRx)
If the pin is used as an output this register allows the configuration of the drive strength independent of the
use with a peripheral module.
2.4.2.5 Pull device enable register (PERx)
This register turns on a pull-up or pull-down device on the related pins determined by the associated
polarity select register (2.4.2.6/2-102).
The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral
module only allow certain configurations of pull devices to become active. Refer to the respective bit
descriptions.
2.4.2.6 Polarity select register (PPSx)
This register selects either a pull-up or pull-down device if enabled.
It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as
a wired-or output.
2.4.2.7 Wired-or mode register (WOMx)
If the pin is used as an output this register turns off the active high drive. This allows wired-or type
connections of outputs.
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Port Integration Module (S12PPIMV1)
2.4.2.8 Interrupt enable register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable
the interrupt.
2.4.2.9 Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.10 Module routing register (PTTRR)
This register allows software re-configuration of the pinouts of the different package options for specific
peripherals:
PTTRR supports the re-routing of the PWM channels to alternative ports
2.4.3 Pins and Ports
NOTE
Please refer to the device pinout section to determine the pin availability in
the different package options.
2.4.3.1 BKGD pin
The BKGD pin is associated with the BDM module.
During reset, the BKGD pin is used as MODC input.
2.4.3.2 Port A, B
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for general purpose I/O.
2.4.3.3 Port E
Port E is associated with the free-running clock outputs ECLK, ECLKX2 and interrupt inputs IRQ and
XIRQ.
Port E pins PE[6:5,3:2] can be used for either general purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general purpose I/O or as the free-running clock ECLKX2 output
running at the core clock rate.
Port E pin PE[4] an be used for either general purpose I/O or as the free-running clock ECLK output
running at the bus clock rate or at the programmed divided clock rate.
Port E pin PE[1] can be used for either general purpose input or as the level- or falling edge-sensitive IRQ
interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.14/2-70) and clearing the
I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple
input with a pull-up.
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Port Integration Module (S12PPIMV1)
Port E pin PE[0] can be used for either general purpose input or as the level-sensitive XIRQ interrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so
this pin is initially configured as a high-impedance input with a pull-up.
2.4.3.4 Port T
This port is associated with TIM and PWM.
Port T pins PT[5:4,0] can be used for either general purpose I/O, or with the routed PWM or with the
channels of the standard Timer subsystem.
Port T pins PT[7:6,3:1] can be used for either general purpose I/O, or with the channels of the standard
Timer subsystem.
2.4.3.5 Port S
This port is associated with SCI.
Port S pins PS[1:0] can be used either for general purpose I/O, or with the SCI subsystem.
Port S pins PS[3:2] can be used for general purpose I/O.
2.4.3.6 Port M
This port is associated with CAN and SPI.
Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN subsystem.
Port M pins PM[5:2] can be used for general purpose I/O, or with the SPI subsystem.
2.4.3.7 Port P
This port is associated with the PWM.
Port P pins PP[7,5:0] can be used for either general purpose I/O with pin interrupt capability, or with the
PWM subsystem.
2.4.3.8 Port J
Port J pins PJ[7:6,2:0] can be used for general purpose I/O with pin-interrupt capability.
2.4.3.9 Port AD
This port is associated with the ATD.
Port AD pins PAD[9:0] can be used for either general purpose I/O, or with the ATD subsystem.
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Port Integration Module (S12PPIMV1)
2.4.4 Pin interrupts
Ports P and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-66) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-65 and
Table 2-60).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set uncertain
tpign
tpval
Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0)
Table 2-60. Pulse Detection Criteria
Mode
Pulse STOP STOP(1)
Unit
Ignored tpulse 3 bus clocks tpulse tpign
Uncertain 3 < tpulse < 4 bus clocks tpign < tpulse < tpval
Valid tpulse 4 bus clocks tpulse tpval
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
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Port Integration Module (S12PPIMV1)
tpulse
Figure 2-66. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5 Initialization Information
2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
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Chapter 3 S12P Memory Map Control (S12PMMCV1)
Table 3-1. Revision History Table
Table 3-2.
Rev. No. Date Sections Substantial Change(s)
Affected
(Item No.) (Submitted By)
01.03 18.APR.2008 Section 3.3.2.3, Corrected the address offset of the PPAGE register (on page 3-112)
"Program Page
01.04 27.Jun.2008 Index Register
01.04 11.Jul.2008
(PPAGE)"
Section 3.5.1,
"Implemented Removed "Table 1-9. MC9S12P Derivatives"
Memory Map"
Removed references to the MMCCTL1 register
3.1 Introduction
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 3-1 shows a block diagram of the S12PMMC module.
3.1.1 Glossary Table 3-3. Glossary Of Terms
Term Definition
Local Addresses Address within the CPU12's Local Address Map (Figure 3-10)
Global Addresse Address within the Global Address Map (Figure 3-10)
Aligned Bus Access Bus access to an even address.
Misaligned Bus Access Bus access to an odd address.
NS Normal Single-Chip Mode
SS Special Single-Chip Mode
Unimplemented Address Ranges Address ranges which are not mapped to any on-chip ressource.
P-Flash Program Flash
D-Plash Data Flash
NVM Non-volatile Memory; P-Flash or D-Flash
IFR NVM Information Row. Refer to FTMRC Block Guide
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S12P Memory Map Control (S12PMMCV1)
3.1.2 Overview
The S12PMMC connects the CPU12's and the S12SBDM's bus interfaces to the MCU's on-chip
ressources (memories and peripherals). It arbitrates the bus accesses and detemines all of the MCU's
memory maps. Furthermore, the S12PMMC is responsible for constraining memory accesses on secured
devices and for selecting the MCU's functional mode.
3.1.3 Features
The main features of this block are:
Paging capability to support a global 256 KByte memory address space
Bus arbitration between the masters CPU12, S12SBDM to different resources.
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU12, S12SBDM
Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address
which does not belong to any of the on-chip modules) in single-chip modes
3.1.4 Modes of Operation
The S12PMMC selects the MCU's functional mode. It also determines the devices behavior in secured and
unsecured state.
3.1.4.1 Functional Modes
Two funtional modes are implementes on devices of the S12P product family:
Normal Single Chip (NS)
The mode used for running applications.
Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals
may also provide special debug features in this mode.
3.1.4.2 Security
S12P devives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module
determines the access permissions to the on-chip memories in secured and unsecured state.
3.1.5 Block Diagram
Figure 3-1 shows a block diagram of the S12PMMC.
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S12P Memory Map Control (S12PMMCV1)
BDM CPU
MMC
Address Decoder & Priority DBG
Target Bus Controller
D-Flash P-Flash RAM Peripherals
Figure 3-1. S12PMMC Block Diagram
3.2 External Signal Description
The S12PMMC uses two external pins to determine the devices operating mode: RESET and MODC
(Figure 3-4) See Device User Guide (DUG) for the mapping of these signals to device pins.
Table 3-4. External System Pins Associated With S12PMMC
Pin Name Pin Functions Description
RESET The RESET pin is used the select the MCU's operating mode.
RESET
(See DUG) MODC The MODC pin is captured at the rising edge of the RESET pin. The captured
value determines the MCU's operating mode.
MODC
(See DUG)
3.3 Memory Map and Registers
3.3.1 Module Memory Map
A summary of the registers associated with the S12PMMC block is shown in Figure 3-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
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Address Register Bit 7 6 5 4 3 2 1 Bit 0
0x000B Name 0 0 0
0x0011 MODE R MODC 0 0 0 0
0x0015 DP10 DP9 DP8
DIRECT W PIX2 PIX1 PIX0
PPAGE R DP14 DP13 DP12 DP11
DP15
W
R 0 0 0 0 PIX3
W
= Unimplemented or Reserved
Figure 3-2. MMC Register Summary
3.3.2 Register Descriptions
This section consists of the S12PMMC control register descriptions in address order.
3.3.2.1 Mode Register (MODE)
Address: 0x000B
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
MODC
W
Reset MODC1 0 0 0 0 0 0 0
1. External signal (see Table 3-4).
= Unimplemented or Reserved
Figure 3-3. Mode Register (MODE)
Read: Anytime.
Write: Only if a transition is allowed (see Figure 3-4).
The MODC bit of the MODE register is used to select the MCU's operating mode.
Table 3-5. MODE Field Descriptions
Field Description
7 Mode Select Bit -- This bit controls the current operating mode during RESET high (inactive). The external
MODC mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered
into the respective register bit after the RESET signal goes inactive (see Figure 3-4).
Write restrictions exist to disallow transitions between certain modes. Figure 3-4 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to
the register bit except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
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RESET
1 0
Normal Special
Single-Chip
Single-Chip 1
(SS)
(NS)
0
1
Figure 3-4. Mode Transition Diagram when MCU is Unsecured
3.3.2.2 Direct Page Register (DIRECT)
Address: 0x0011
7 6 5 4 3 2 1 0
R DP14 DP13 DP12 DP11 DP10 DP9 DP8
DP15
W
Reset 0 0 0 0 0 0 0 0
Figure 3-5. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special SS, writr-one in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Table 3-6. DIRECT Field Descriptions
Field Description
70 Direct Page Index Bits 158 -- These bits are used by the CPU when performing accesses using the direct
DP[15:8] addressing mode. These register bits form bits [15:8] of the local address (see Figure 3-6).
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Global Address [17:0]
Bit17 Bit16 Bit15 Bit8 Bit7 Bit0
DP [15:8]
CPU Address [15:0]
Figure 3-6. DIRECT Address Mapping
Example 3-1. This example demonstrates usage of the Direct Addressing Mode
MOVB #0x80,DIRECT ;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
LDY <00 ;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are "direct page aware" and can
;automatically select direct mode.
3.3.2.3 Program Page Index Register (PPAGE)
Address: 0x0015
7 6 5 4 3 2 1 0
R 0 0 0 0 PIX1 PIX0
1 0
PIX3 PIX2
W
Reset 0 0 0 0 1 1
Figure 3-7. Program Page Index Register (PPAGE)
Read: Anytime
Write: Anytime
These four index bits are used to map 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-8). This supports accessing
up to 256 KB of Flash (in the Global map) within the 64KB Local map. The PPAGE index register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions.
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Bit17 Global Address [17:0] S12P Memory Map Control (S12PMMCV1)
Bit14 Bit13 Bit0
PPAGE Register [3:0] Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-8. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Table 3-7. PPAGE Field Descriptions
Field Description
30 Program Page Index Bits 30 -- These page index bits are used to select which of the 256 P-Flash or ROM
PIX[3:0] array pages is to be accessed in the Program Page Window.
The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0x0C. Parts of this page are covered by
Registers, D-Flash and RAM space. See SoC Guide for details.
The fixed 16KB page from 0x40000x7FFF is the page number 0x0D.
The reset value of 0x0E ensures that there is linear Flash space available between addresses 0x0000 and
0xFFFF out of reset.
The fixed 16KB page from 0xC000-0xFFFF is the page number 0x0F.
3.4 Functional Description
The S12PMMC block performs several basic functions of the S12P sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1 MCU Operating Modes
Normal single chip mode
This is the operation mode for running application codeThere is no external bus in this mode.
Special single chip mode
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This mode is generally used for debugging operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin.
3.4.2 Memory Map Scheme
3.4.2.1 CPU and BDM Memory Map Scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the memory map during user's code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x3_FF00 -
0x3_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0x0F.
3.4.2.1.1 Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in S12PMMC allows accessing up to 256KB of P-Flash in the global
memory map by using the four index bits (PPAGE[3:0]) to page 16x16 KB blocks into the program page
window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see Section 3.6.1, "CALL and RTC Instructions).
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC0000xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU
memory map.
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Expansion of the BDM Local Address Map
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global
address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
The four BDMPPR Program Page index bits allow access to the full 256KB address map that can be
accessed with 18 address bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and,
in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM
hardware commands. See the BDM Block Guide for further details. (see Figure 3-9).
BDM HARDWARE COMMAND
Global Address [17:0]
Bit17 Bit14 Bit13 Bit0
BDMPPR Register [3:0] BDM Local Address [13:0]
BDM FIRMWARE COMMAND
Global Address [17:0]
Bit17 Bit14 Bit13 Bit0
BDMPPR Register [3:0] CPU Local Address [13:0]
Figure 3-9. BDMPPR Address Mapping
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CPU and BDM Global Memory Map
Local Memory Map
0x0000 REGISTERS 0x0_0000 REGISTERS (PPAGE 0x00) (PPAGE 0x01)
0x0400 D-Flash RAMSIZE
Unimplemented Area
0x1400 RAM_LOW RAM
NVM Resources
Unpaged P-Flash 0x0_4000
0x0_4400 D-Flash
RAM RAMSIZE 0x0_5400 NVM Resources
0x4000
0x0_8000
Unpaged P-Flash P-Flash (PPAGE 0x02-0x0B))
10 *16K paged
0x8000 0 0 0 0 P3P2P1P0 0x3_0000 (PPAGE 0x0C) (PPAGE 0x0D) (PPAGE 0x0E) (PPAGE 0x0F)
PPAGE
Unpaged P-Flash Unpaged P-Flash
or 0x3_4000
P-Flash window Unpaged P-Flash
0x3_8000
0xC000
Unpaged P-Flash
Unpaged P-Flash
0xFFFF 0x3_C000
Unpaged P-Flash
0x3_FFFF
Figure 3-10. Local to Global Address Mapping
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3.5 Implemented Memory in the System Memory Architecture
Each memory can be implemented in its maximum allowed size. But some devices have been defined for
smaller sizes, which means less implemented pages. All non implemented pages are called unimplemented
areas.
Registers has a fixed size of 1KB, accessible via xbus0.
SRAM has a maximum size of 11KB, accessible via xbus0.
D-Flash has a fixed size of 4KB accessible via xbus0.
P-Flash has a maximum size of 224KB, accessible via xbus0.
3.5.1 Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, D-Flash, and P-Flash) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the SoC Guide for further details. Figure 3-11
and Table 3-8 show the memory spaces occupied by the on-chip resources. Please note that the memory
spaces have fixed top addresses.
Table 3-8. Global Implemented Memory Space
Internal Resource Bottom Address Top Address
0x0_03FF
Registers 0x0_0000 0x0_3FFF
System RAM RAM_LOW = 0x0_53FF
D-Flash 0x0_4000 minus RAMSIZE(1) 0x3_FFFF
0x0_4400
P-Flash PF_LOW =
0x4_0000 minus FLASHSIZE(2)
1. RAMSIZE is the hexadecimal value of RAM SIZE in bytes
2. FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
In single-chip modes accesses by the CPU12 (except for firmware commands) to any of the
unimplemented areas (see Figure 3-11) will result in an illegal access reset (system reset). BDM accesses
to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM
module (Refer to BDM Block Guide).
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S12P Memory Map Control (S12PMMCV1)
CPU and BDM Global Memory Map
Local Memory Map
0x0000 REGISTERS 0x0_0000 REGISTERS (PPAGE 0x00) (PPAGE 0x01)
0x0400 D-Flash RAMSIZE
Unimplemented Area
0x1400 RAM_LOW
Unpaged P-Flash 0x0_4000 RAM
0x0_4400 NVM Resources
RAM RAMSIZE 0x0_5400
D-Flash
0x4000 NVM Resources
0x0_8000
Unpaged P-Flash
0x8000 Unimplemented area
PF_LOW
P-Flash window 0 0 0 0 P3P2P1P0
PPAGE P-Flash
0xC000
Unpaged P-Flash PFSIZE
0xFFFF 0x3_FFFF
Figure 3-11. Implemented Global Address Mapping
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3.5.2 Chip Bus Control
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12,
S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data
bus swapping operations. All internal resources are connected to specific target buses (see Figure 3-12).
DBG CPU BDM
S12X0 S12X1
MMC "Crossbar Switch"
XBUS0
P-Flash D-Flash BDM SRAM IPBI
resources Peripherals
Figure 3-12. S12P platform
3.5.2.1 Master Bus Prioritization regarding Access Conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case
the CPU will be stalled after finishing the current operation and the BDM will gain access to the
bus.
3.5.3 Interrupts
The MMC does not generate any interrupts
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3.6 Initialization/Application Information
3.6.1 CALL and RTC Instructions
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16 Kbyte program page window in the
64 Kbyte local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new instruction-
supplied PPAGE value into the PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
pushes this 16-bit value onto the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
address
This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction
execution. A CALL instruction can be performed from any address to any other address in the local CPU
memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing
mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand
in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory
locations where the new page value and the address of the called subroutine are stored. Using indirect
addressing for both the new page value and the address within the page allows usage of values calculated
at run time rather than immediate values that must be known at the time of assembly.
The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks
the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction
after the CALL instruction.
During the execution of an RTC instruction the CPU performs the following steps:
1. Pulls the previously stored PPAGE value from the stack
2. Pulls the 16-bit return address from the stack and loads it into the PC
3. Writes the PPAGE value into the PPAGE register
4. Refills the queue and resumes execution at the return address
This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory
space.
The CALL and RTC instructions behave like JSR and RTS instruction, they however require more
execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and
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CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to
access subroutines that are already present in the local CPU memory map (i.e. in the same page in the
program memory page window for example). However calling a function located in a different page
requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because
the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the
RTC instruction must be called using the CALL instruction even when the correct page is already present
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
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Chapter 4
Interrupt Module (S12SINTV1)
Version Revision Effective Author Description of Changes
Number Date Date
removed references to XIRQ/IRQ and added D2D error and D2D
01.01 13 Jun interrupt instead
2006 updates for S12P family devices:
01.02 - re-added XIRQ and IRQ references since this functionality is used
13 Sep on devices without D2D
2007 - added low voltage reset as possible source to the pin reset vector
added clarification of "Wake-up from STOP or WAIT by XIRQ with
01.03 21 Nov X bit set" feature
2007
4.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.1.1 Glossary
Table 4-2 contains terms and abbreviations used in the document.
Table 4-2. Terminology
Term Meaning
CCR Condition Code Register (in the CPU)
ISR Interrupt Service Routine
MCU Micro-Controller Unit
4.1.2 Features
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base1 + 0x0080).
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258 I bit maskable interrupt vector requests (at addresses vector base + 0x00820x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU
request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.
4.1.3 Modes of Operation
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from wait mode if an interrupt occurs. Please refer to Section 4.5.3, "Wake Up
from Stop or Wait Mode" for details.
Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of
waking-up the CPU from stop mode if an interrupt occurs. Please refer to Section 4.5.3, "Wake Up
from Stop or Wait Mode" for details.
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 4.3.1.1, "Interrupt Vector Base Register (IVBR)" for details.
4.1.4 Block Diagram
Figure 4-1 shows a block diagram of the INT module.
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
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Peripheral Interrupt Module (S12SINTV1)
Interrupt Requests
Wake Up
CPU
Vector
Address
Non I bit Maskable Channels Priority
Decoder
To CPU
I bit Maskable Channels IVBR
Interrupt
Requests
Figure 4-1. INT Block Diagram
4.2 External Signal Description
The INT module has no external signals.
4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the INT module.
4.3.1 Register Descriptions
This section describes in address order all the INT registers and their individual bits.
4.3.1.1 Interrupt Vector Base Register (IVBR)
Address: 0x0120
7 6 5 4 3 2 1 0
R
IVB_ADDR[7:0]
W
Reset 1 1 1 1 1 1 1 1
Figure 4-2. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
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Table 4-3. IVBR Field Descriptions
Field Description
70 Interrupt Vector Base Address Bits -- These bits represent the upper byte of all vector addresses. Out of
IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF800xFFFE) to ensure compatibility to
HCS12.
Note: A system reset will initialize the interrupt vector base register with "0xFF" before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as "0xFF". This is done to enable
handling of all non-maskable interrupts in the BDM firmware.
4.4 Functional Description
The INT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
4.4.1 S12S Exception Requests
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the
priority of pending interrupt requests.
4.4.2 Interrupt Prioritization
The INT module contains a priority decoder to determine the priority for all interrupt requests pending for
the CPU. If more than one interrupt request is pending, the interrupt request with the higher vector address
wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The I bit in the condition code register (CCR) of the CPU must be cleared.
3. There is no SWI, TRAP, or X bit maskable request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than
the I bit maskable interrupt requests. If the X bit in the CCR is cleared, it is
possible to interrupt an I bit maskable interrupt by an X bit maskable
interrupt. It is possible to nest non maskable interrupt requests, e.g., by
nesting SWI or TRAP calls.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher
priority interrupt request could override the original interrupt request that caused the CPU to request the
vector. In this case, the CPU will receive the highest priority vector and the system will process this
interrupt request first, before the original interrupt request is processed.
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If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied
to the CPU will default to that of the spurious interrupt vector.
NOTE
Care must be taken to ensure that all interrupt requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0080)).
4.4.3 Reset Exception Requests
The INT module supports three system reset exception request types (please refer to the Clock and Reset
generator module for details):
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
2. Clock monitor reset request
3. COP watchdog reset request
4.4.4 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in Table 4-4.
Table 4-4. Exception Vector Map and Priority
Vector Address(1) Source
0xFFFE Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
0xFFFC Clock monitor reset
0xFFFA COP watchdog reset
(Vector base + 0x00F8) Unimplemented opcode trap
(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x00F4) X bit maskable interrupt request (XIRQ or D2D error interrupt)(2)
(Vector base + 0x00F2) IRQ or D2D interrupt request(3)
(Vector base + 0x00F00x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the
vector address, in descending order)
(Vector base + 0x0080) Spurious interrupt
1. 16 bits vector address based
2. D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
3. D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
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4.5 Initialization/Application Information
4.5.1 Initialization
After system reset, software should:
1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF800xFFF9).
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.
4.5.2 Interrupt Nesting
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the
CPU.
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, other I bit maskable interrupt requests can interrupt the
current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
1. Service interrupt, e.g., clear interrupt flags, copy data, etc.
2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt
requests)
3. Process data
4. Return from interrupt by executing the instruction RTI
4.5.3 Wake Up from Stop or Wait Mode
4.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine
whether an I bit maskable interrupts is qualified to wake-up the CPU or not, the same conditions as in
normal run mode are applied during stop or wait mode:
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU.
Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can
wake-up the MCU from stop mode.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set.
If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the
associated ISR is not called. The CPU then resumes program execution with the instruction following the
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Interrupt Module (S12SINTV1)
WAI or STOP instruction. This features works the same rules like any interrupt request, i.e. care must be
taken that the X interrupt request used for wake-up remains active at least until the system begins execution
of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur.
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Interrupt Module (S12SINTV1)
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Chapter 5
Background Debug Module (S12SBDMV1)
Revision History
Revision Number Date Summary of Changes
s12s_bdm.01.00.00 08.Feb.2006 First version of S12SBDMV1
s12s_bdm.01.00.02 09.FEB.2006 Updated register address information & Block Version
s12s_bdm.01.00.12 10.May.2006 Removed CLKSW bit and description
s12s_bdm.01.01.01 20.Sept.2007 Added conditional text for S12P family
5.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with
HCS12S core is 0xC2)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
5.1.1 Features
The BDM includes these distinctive features:
Single-wire communication with host development system
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Background Debug Module (S12SBDMV1)
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during wait mode
When secured, hardware commands are allowed to access the register space in special single chip
mode, if the Flash erase tests fail.
Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with
HCS12S core is 0xC2)
BDM hardware commands are operational until system stop mode is entered
5.1.2 Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending the function during background debug mode.
5.1.2.1 Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
Normal modes
General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
5.1.2.2 Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents access to Flash other than allowing erasure. For more
information please see Section 5.4.1, "Security".
5.1.2.3 Low-Power Modes
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
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Background Debug Module (S12SBDMV1)
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 5-1.
Host Serial Data 16-Bit Shift Register
System BKGD Interface Control
Register Block
TRACE Instruction Code Bus Interface Address
BDMACT and and
Data
Execution Control Logic Control
Clocks
ENBDM Standard BDM Firmware
SDV LOOKUP TABLE
UNSEC Secured BDM Firmware
BDMSTS LOOKUP TABLE
Register
Figure 5-1. BDM Block Diagram
5.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is based on the the settings for the VCO clock
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
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Background Debug Module (S12SBDMV1)
5.3 Memory Map and Register Definition
5.3.1 Module Memory Map
Table 5-1 shows the BDM memory map when BDM is active.
Global Address Table 5-1. BDM Memory Map Size
(Bytes)
0x3_FF000x3_FF0B Module
0x3_FF0C0x3_FF0E 12
BDM registers 3
0x3_FF0F BDM firmware ROM 1
0x3_FF100x3_FFFF Family ID (part of BDM firmware ROM) 240
BDM firmware ROM
5.3.2 Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global Register Bit 7 6 5 4 3 2 1 Bit 0
Address Name
0x3_FF00 Reserved R X X X X X X 0 0
W
0x3_FF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0
W
0x3_FF02 Reserved R X X X X X X X X
W
0x3_FF03 Reserved R X X X X X X X X
W
0x3_FF04 Reserved R X X X X X X X X
W
0x3_FF05 Reserved R X X X X X X X X
W
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary
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Background Debug Module (S12SBDMV1)
Global Register Bit 7 6 5 4 3 2 1 Bit 0
Address Name CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
0x3_FF06 BDMCCR R 0 0 0 0 0 0 0
W 0 0 0
0 0 0 BPP3 BPP2 BPP1 BPP0
0x3_FF07 Reserved R 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
W 0 0 0 0
0x3_FF08 BDMPPR R
BPAE
W
0x3_FF09 Reserved R 0
W
0x3_FF0A Reserved R 0
W
0x3_FF0B Reserved R 0
W
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary (continued)
5.3.2.1 BDM Status Register (BDMSTS)
Register Global Address 0x3_FF01
7 6 5 4 3 2 1 0
R BDMACT 0 SDV TRACE 0 UNSEC 0
ENBDM
W
Reset 1 0 0 0 0 0(2) 0
Special Single-Chip Mode 0(1)
All Other Modes 0 0 0 0 0 0 0 0
= Unimplemented, Reserved = Implemented (do not alter)
0 = Always read zero
1. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully
transmitted and executed.
2. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
Figure 5-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
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Background Debug Module (S12SBDMV1)
-- ENBDM should only be set via a BDM hardware command if the BDM firmware commands
are needed. (This does not apply in special single chip mode).
-- BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
the standard BDM firmware lookup table upon exit from BDM active mode.
-- All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Table 5-2. BDMSTS Field Descriptions
Field Description
7 Enable BDM -- This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
ENBDM active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
6 0 BDM disabled
BDMACT 1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode. In special single chip mode with
4
SDV the device secured, this bit will not be set by the firmware until after the Flash erase verify tests are
complete.
3
TRACE BDM Active Status -- This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
1 standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
UNSEC the map.
0 BDM not active
1 BDM active
Shift Data Valid -- This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a firmware or hardware read command or after data has been received as part of a firmware or hardware
write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used
by the standard BDM firmware to control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
TRACE1 BDM Firmware Command is Being Executed -- This bit gets set when a BDM TRACE1 firmware
command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands:
GO or GO_UNTIL.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
Unsecure -- If the device is secured this bit is only writable in special single chip mode from the BDM secure
firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled
and put into the memory map overlapping the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the on-chip Flash is erased. This being the case, the UNSEC
bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure
BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip
Flash EEPROM. Note that if the user does not change the state of the bits to "unsecured" mode, the
system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect
when the security byte in the Flash EEPROM is configured for unsecure mode.
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Background Debug Module (S12SBDMV1)
Register Global Address 0x3_FF06
R 7 6 5 4 3 2 1 0
W
Reset CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Special Single-Chip Mode
All Other Modes 1 1 0 0 1 0 0 0
0 0
0 0 0 0 0 0
Figure 5-4. BDM CCR Holding Register (BDMCCR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register in this CPU mode. Out of reset in all other modes the BDMCCR
register is read zero.
When entering background debug mode, the BDM CCR holding register is used to save the condition code
register of the user's program. It is also used for temporary storage in the standard BDM firmware mode.
The BDM CCR holding register can be written to modify the CCR value.
5.3.2.2 BDM Program Page Index Register (BDMPPR)
Register Global Address 0x3_FF08
7 6 5 4 3 2 1 0
BPP1 BPP0
R BPAE 0 0 0 BPP3 BPP2
0 0
W
Reset 0 0 0 0 0 0
= Unimplemented, Reserved
Figure 5-5. BDM Program Page Register (BDMPPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Table 5-3. BDMPPR Field Descriptions
Field Description
7
BDM Program Page Access Enable Bit -- BPAE enables program page access for BDM hardware and
BPAE firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD
and WRITE_BD) can not be used for global accesses even if the BGAE bit is set.
30 0 BDM Program Paging disabled
BPP[3:0] 1 BDM Program Paging enabled
BDM Program Page Index Bits 30 -- These bits define the selected program page. For more detailed
information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.
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Background Debug Module (S12SBDMV1)
5.3.3 Family ID Assignment
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x3_FF0F). The read-only
value is a unique family ID which is 0xC2 for devices with HCS12S core.
5.4 Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see Section 5.4.3, "BDM Hardware Commands". Target system memory
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see Section 5.4.4, "Standard BDM Firmware Commands". The CPU resources referred to are the
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see Section 5.4.3, "BDM Hardware Commands") and in secure mode (see Section 5.4.1,
"Security"). Firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
5.4.1 Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware
lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.
The secure BDM firmware verifies that the on-chip Flash EEPROM are erased. This being the case, the
UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM firmware
and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the Flash does
not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware
enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the
firmware commands. This allows the BDM hardware to be used to erase the Flash.
BDM operation is not possible in any other mode than special single chip mode when the device is secured.
The device can only be unsecured via BDM serial interface in special single chip mode. For more
information regarding security, please see the S12S_9SEC Block Guide.
5.4.2 Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated
only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)
register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire
interface, using a hardware command such as WRITE_BD_BYTE.
After being enabled, BDM is activated by one of the following1:
Hardware BACKGROUND command
1. BDM is enabled and active immediately out of special single-chip reset.
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Background Debug Module (S12SBDMV1)
CPU BGND instruction
Breakpoint force or tag mechanism1
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
NOTE
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x3_FF00 to 0x3_FFFF. BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
When BDM is activated while CPU executes code overlapping with BDM firmware space the saved
program counter (PC) will be auto incremented by one from the BDM firmware, no matter what caused
the entry into BDM active mode (BGND instruction, BACKGROUND command or breakpoints). In such
a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO
command.
5.4.3 BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU such
as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in Table 5-4.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
1. This method is provided by the S12S_DBG module.
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Background Debug Module (S12SBDMV1)
enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
Table 5-4. Hardware Commands
Command Opcode Data Description
(hex)
BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be
issued when the part enters active background mode.
ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE E4 16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Odd address data on low byte; even address data on high byte.
READ_BD_WORD EC 16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Must be aligned access.
READ_BYTE E0 16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Odd address data on low byte; even address data on high byte.
READ_WORD E8 16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Must be aligned access.
WRITE_BD_BYTE C4 16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD CC 16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Must be aligned access.
WRITE_BYTE C0 16-bit address Write to memory with standard BDM firmware lookup table out of map.
16-bit data in Odd address data on low byte; even address data on high byte.
WRITE_WORD C8 16-bit address Write to memory with standard BDM firmware lookup table out of map.
16-bit data in Must be aligned access.
NOTE:
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
5.4.4 Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active
BDM to execute standard BDM firmware commands, see Section 5.4.2, "Enabling and Activating BDM".
Normal instruction execution is suspended while the CPU executes the firmware located in the standard
BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.
As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become
visible in the on-chip memory map at 0x3_FF000x3_FFFF, and the CPU begins executing the standard
BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are
received.
The firmware commands are shown in Table 5-5.
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Table 5-5. Firmware Commands
Command(1) Opcode Data Description
(hex)
READ_NEXT(2) 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.
READ_PC 63 16-bit data out Read program counter.
READ_D 64 16-bit data out Read D accumulator.
READ_X 65 16-bit data out Read X index register.
READ_Y 66 16-bit data out Read Y index register.
READ_SP 67 16-bit data out Read stack pointer.
WRITE_NEXT 42 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location
pointed to by X.
WRITE_PC 43 16-bit data in Write program counter.
WRITE_D 44 16-bit data in Write D accumulator.
WRITE_X 45 16-bit data in Write X index register.
WRITE_Y 46 16-bit data in Write Y index register.
WRITE_SP 47 16-bit data in Write stack pointer.
GO 08 none Go to user program. If enabled, ACK will occur when leaving active
GO_UNTIL(3)
background mode.
0C none Go to user program. If enabled, ACK will occur upon returning to active
background mode.
TRACE1 10 none Execute one user instruction then return to active BDM. If enabled,
ACK will occur upon returning to active background mode.
TAGGO -> GO 18 none (Previous enable tagging and go to user program.)
This command will be deprecated and should not be used anymore.
Opcode will be executed as a GO command.
1. If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
2. When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources
are accessed rather than user code. Writing BDM firmware is not possible.
3. System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).
The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the "UNTIL"
condition (BDM active again) is reached (see Section 5.4.7, "Serial Interface Hardware Handshake Protocol" last Note).
5.4.5 BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a
16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte
or word implication in the command name.
8-bit reads return 16-bits of data, of which, only one byte will contain valid
data. If reading an even address, the valid data will appear in the MSB. If
reading an odd address, the valid data will appear in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM will ignore the least significant bit
of the address and will assume an even address from the remaining bits.
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For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the
command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for
the requested data to be made available in the BDM shift register, ready to be shifted out.
For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be
written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing, it is
recommended that the ACK (acknowledge function) is used to indicate
when an operation is complete. When using ACK, the delay times are
automated.
Figure 5-6 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 16 target clock cycles.1
1. Target clock cycles are cycles measured using the target MCU's serial clock rate. See Section 5.4.6, "BDM Serial Interface"
and Section 5.3.2.1, "BDM Status Register (BDMSTS)" for information on how serial clock rate is selected.
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Background Debug Module (S12SBDMV1)
8 Bits 16 Bits 150-BC 16 Bits
AT ~16 TC/Bit AT ~16 TC/Bit Delay AT ~16 TC/Bit
Hardware Command Address Data Next
Read Command
Hardware 150-BC
Write Delay
Firmware Command Address Data Next
Read Command
Firmware 48-BC
Write DELAY
GO, Command Data Next
TRACE Command
36-BC
DELAY
Command Data Next
Command
76-BC
Delay
Command Next BC = Bus Clock Cycles
Command TC = Target Clock Cycles
Figure 5-6. BDM Command Structure
5.4.6 BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed based on the VCO clock (please refer to the CPMU Block Guide for
more details), which gets divided by 8. This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 5-7 and that of target-to-host in Figure 5-8 and
Figure 5-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the
host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
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earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 5-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived Target Senses Bit Earliest
Start of Bit Time 10 Cycles Start of
Next Bit
Synchronization
Uncertainty
Figure 5-7. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 5-8 shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
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BDM Clock High-Impedance High-Impedance
(Target MCU) R-C Rise High-Impedance
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
Perceived
Start of Bit Time
BKGD Pin
10 Cycles Earliest
10 Cycles Start of
Next Bit
Host Samples
BKGD Pin
Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-9 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
BDM Clock
(Target MCU)
Host High-Impedance
Drive to Speedup Pulse
BKGD Pin
Target System
Drive and
Speedup Pulse
Perceived
Start of Bit Time
BKGD Pin
10 Cycles Earliest
10 Cycles Start of
Next Bit
Host Samples
BKGD Pin
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
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5.4.7 Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM
clock source can be modified when changing the settings for the VCO frequency (CPMUSYNR), it is very
helpful to provide a handshake protocol in which the host could determine when an issued command is
executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8. The alternative
is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate
the clock could be running. This sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a
brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued
by the host, has been successfully executed (see Figure 5-10). This pulse is referred to as the ACK pulse.
After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read
command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock
cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick
of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the
command execution depends upon the CPU bus, which in some cases could be very slow due to long
accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely
on any accurate time measurement or short response time to any event in the serial communication.
BDM Clock
(Target MCU)
16 Cycles
Target High-Impedance High-Impedance
Transmits
ACK Pulse 32 Cycles
BKGD Pin
Speedup Pulse
Minimum Delay
From the BDM Command
16th Tick of the Earliest
Last Command Bit Start of
Next Bit
Figure 5-10. Target Acknowledge Pulse (ACK)
NOTE
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters wait or stop prior to executing a
hardware command, the ACK pulse will not be issued meaning that the
BDM command was not executed. After entering wait or stop mode, the
BDM command is no longer pending.
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Figure 5-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was
odd or even.
Target Host
BKGD Pin READ_BYTE Byte Address (2) Bytes are New BDM
Host Target Retrieved Command
Host Target
BDM Issues the
ACK Pulse (out of scale)
BDM Decodes BDM Executes the
the Command READ_BYTE Command
Figure 5-11. Handshake Protocol at Command Level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK
handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware
handshake protocol in Figure 5-10 specifies the timing when the BKGD pin is being driven, so the host
should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one
side is driving low and the other side is issuing a speedup pulse (high). Other
"highs" are pulled rather than driven. However, at low rates the time of the
speedup pulse can become lengthy and so the potential conflict time
becomes longer as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not
acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command
(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be
issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any
possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol
provides a mechanism in which a command, and its corresponding ACK, can be aborted.
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NOTE
The ACK pulse does not provide a time out. This means for the GO_UNTIL
command that it can not be distinguished if a stop or wait has been executed
(command discarded and ACK not issued) or if the "UNTIL" condition
(BDM active) is just not reached yet. Hence in any case where the ACK
pulse of a command is not issued the possible pending command should be
aborted before issuing a new command. See the handshake abort procedure
described in Section 5.4.8, "Hardware Handshake Abort Procedure".
5.4.8 Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued
the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving
it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a
speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,
see Section 5.4.9, "SYNC -- Request Timed Reference Pulse", and assumes that the pending command
and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been
completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it
can not be guaranteed that the pending command is aborted when issuing a SYNC before the
corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins
until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware
READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command
starts during this latency time the READ or WRITE command will not be aborted, but the corresponding
ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL command can not be aborted. Only
the corresponding ACK pulse can be aborted by the SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in
the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.
The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short
abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending
command will be aborted along with the ACK pulse. The potential problem with this abort procedure is
when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not
perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new
command after the abort pulse was issued, while the target expects the host to retrieve the accessed
memory byte. In this case, host and target will run out of synchronism. However, if the command to be
aborted is not a read command the short abort pulse could be used. After a command is aborted the target
assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference
for the reader to better understand the BDM internal behavior. It is not
recommended that this procedure be used in a real application.
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Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See Section 5.4.9, "SYNC -- Request
Timed Reference Pulse".
Figure 5-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
command. Note that, after the command is aborted a new command could be issued by the host computer.
READ_BYTE CMD is Aborted SYNC Response
by the SYNC Request From the Target
(Out of Scale) (Out of Scale)
BKGD Pin READ_BYTE Memory Address READ_STATUS New BDM Command
Host Target Host Target Host Target
BDM Decode New BDM Command
and Starts to Execute
the READ_BYTE Command
Figure 5-12. ACK Abort Procedure at the Command Level
NOTE
Figure 5-12 does not represent the signals in a true timing scale
Figure 5-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
At Least 128 Cycles
BDM Clock ACK Pulse High-Impedance Speedup Pulse
(Target MCU) Electrical Conflict
Host and
Target MCU Target Drive
Drives to to BKGD Pin
BKGD Pin Host SYNC Request Pulse
Host
Drives SYNC
To BKGD Pin
BKGD Pin
16 Cycles
Figure 5-13. ACK Pulse and SYNC Request Conflict
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NOTE
This information is being provided so that the MCU integrator will be aware
that such a conflict could occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
ACK_ENABLE -- enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
ACK_DISABLE -- disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 5.4.3, "BDM Hardware Commands" and Section 5.4.4, "Standard BDM Firmware Commands"
for more information on the BDM commands.
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be
used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is
issued in response to this command, the host knows that the target supports the hardware handshake
protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In
this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid
command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to
background mode. The ACK pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse
related to this command could be aborted using the SYNC command.
The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this
case, is issued when the CPU enters into background mode. This command is an alternative to the GO
command and should be used when the host wants to trace if a breakpoint match occurs and causes the
CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which
could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related
to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode
after one instruction of the application program is executed. The ACK pulse related to this command could
be aborted using the SYNC command.
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5.4.9 SYNC -- Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the
correct communication speed to use for BDM communications until after it has analyzed the response to
the SYNC command. To issue a SYNC command, the host should perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication
frequency (The lowest serial communication frequency is determined by the settings for the VCO
clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically
one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed
for subsequent BDM communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is
discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the
SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new
BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the
same as in a regular SYNC command. Note that one of the possible causes for a command to not be
acknowledged by the target is a host-target synchronization problem. In this case, the command may not
have been understood by the target and so an ACK response pulse will not be issued.
5.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM
firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to
return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or
tracing through the user code one instruction at a time.
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If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but
no user instruction is executed. Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but
all peripherals are free running. Hence possible timing relations between CPU code execution and
occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will
result in a return address pointing to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when
the stop or wait instruction is traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving
the low power mode. This is the case because BDM active mode can not be entered after CPU
executed the stop instruction. However all BDM hardware commands except the BACKGROUND
command are operational after tracing a stop or wait instruction and still being in stop or wait
mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is
operational.
As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value
points to the entry of the corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command
will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM
active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.
All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or
wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
stop mode has been reached. Hence after a system stop mode the handshake feature must be
enabled again by sending the ACK_ENABLE command.
5.4.11 Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the
SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any
time-out limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieval after the time-out has
occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data
to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware
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handshake protocol is enabled, the time out between a read command and the data retrieval is disabled.
Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data
from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out
feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host
needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued.
After that period, the read command is discarded and the data is no longer available for retrieval. Any
negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC
request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the
serial communication is active. This means that if a time frame higher than 512 serial clock cycles is
observed between two consecutive negative edges and the command being issued or data being retrieved
is not complete, a soft-reset will occur causing the partially received command or data retrieved to be
disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the
target as the start of a new BDM command, or the start of a SYNC request pulse.
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Chapter 6
S12S Debug Module (S12SDBGV2)
Table 6-1. Revision History
Revision Number Revision Sections Summary of Changes
Date Affected
02.07 Added application information
02.08 13.DEC.2007 6.5 Spelling corrections. Revision history format changed.
02.09 Added note for end aligned, PurePC, rollover case.
09.MAY.2008 General
29.MAY.2008 6.4.5.4
6.1 Introduction
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12SDBG module is optimized for S12SCPU debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
6.1.1 Glossary Of Terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16 bit data entity
Data Line: 20 bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches
the execution stage a tag hit occurs.
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6.1.2 Overview
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3 Features
Three comparators (A, B and C)
-- Comparators A compares the full address bus and full 16-bit data bus
-- Comparator A features a data bus mask register
-- Comparators B and C compare the full address bus only
-- Each comparator features selection of read or write access cycles
-- Comparator B allows selection of byte or word access cycles
-- Comparator matches can initiate state sequencer transitions
Three comparator modes
-- Simple address/data comparator match mode
-- Inside address range mode, Addmin Address Addmax
-- Outside address range match mode, Address < Addmin or Address > Addmax
Two types of matches
-- Tagged -- This matches just before a specific instruction begins execution
-- Force -- This is valid on the first instruction boundary after a match occurs
Two types of breakpoints
-- CPU breakpoint entering BDM on breakpoint (BDM)
-- CPU breakpoint executing SWI on breakpoint (SWI)
Trigger mode independent of comparators
-- TRIG Immediate software trigger
Four trace modes
-- Normal: change of flow (COF) PC information is stored (see 6.4.5.2.1) for change of flow
definition.
-- Loop1: same as Normal but inhibits consecutive duplicate source address entries
-- Detail: address and data for all cycles except free cycles and opcode fetches are stored
-- Compressed Pure PC: all program counter addresses are stored
4-stage state sequencer for trace buffer control
-- Tracing session trigger linked to Final State of state sequencer
-- Begin and End alignment of tracing to trigger
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6.1.4 Modes of Operation
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Table 6-2. Mode Dependent Restriction Summary
BDM BDM MCU Comparator Breakpoints Tagging Tracing
Enable Active Secure Matches Enabled Possible Possible Possible
x x 1 Yes Yes Yes No
0 0 0 Yes Yes
0 1 0 Only SWI Yes
1 0 0 Yes Yes
1 1 0 No Active BDM not possible when not enabled No
Yes Yes
No No
6.1.5 Block Diagram TAGS
TAGHITS BREAKPOINT REQUESTS
TO CPU
SECURE
CPU BUS &
电子工程世界