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QS5100

器件型号:QS5100
厂商名称:Altonics
厂商官网:http://www.altonics.com
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器件描述

digital FX lsi

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QS5100
Digital FX LSI
1. General Description
The QS5100 is a high quality Effect processor LSI that can
produce the effects of reverb, chorus, echo, vibrato, tremolo,
wahwah, and flanger with a 5 band-equalizer.
All functions can be controlled by an external 8bit MCU, making
it possible for the QS5100 to be applied to a wide variety of
applications.
Making the QS5100 the best solution for external guitar
effectors, car audio, PA and hardware effect modules.
2. Features
• High resolution of up to 32k ~ 48kHz sampling rate
• Supports 8 bit MCU or Serial EEPROM interface for
stand alone mode.
• 5 band EQ on digital output
• Supports 256k words EDO DRAM for delay.
• Low power operation 2.7V ~ 3.6V
• Support for 16/18/20/22/24 bits Codec I/F
• Supports reverb, chorus, echo, wah wah, flanger,
tremolo, vibrato
• Compact thin package 64 LQFP (10 X 10mm)
• f = 8.192 ~ 12.288 MHz
• Low power consumption under 10uA
in power down mode
• IDD
OP
< 50 mA
• Can be assign CODEC I/F (Left or Right Justified)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
QS5100
Datecode KOREA
44
43
42
41
40
39
38
37
36
35
34
33
64P LQFP
10 X 10mm 0.5 pitch
QS5100
3. Pin Description
PIN NO
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
PAD NAME
CPU_DATA[0]
CPU_DATA[1]
CPU_DATA[2]
CPU_DATA[3]
CPU_DATA[4]
CPU_DATA[5]
VDD
VSS
CPU_DATA[6]
CPU_DATA[7]
CPU_REB
PAD TYPE
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PVDF
PV0F
PC3B03U
PC3B03U
PC3B03U
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
P
I/O
I/O
I/O
Digital FX LSI
DESCRIPTION
CPU Data I/O for Normal Mode.
Serial EEPROM Data I/O for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Serial EEPROM Clock for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Set[0] for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Set[1] for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Set[2] for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Set[3] for Stand Alone Mode.
Power
Ground
CPU Data I/O for Normal Mode.
Set[4] for Stand Alone Mode.
CPU Data I/O for Normal Mode.
Set[5] for Stand Alone Mode.
Data Read Enable for Normal Mode.
Used for external data read operation,
functions on active low.
First Serial Peripheral Interface CS for Stand
Alone Mode.
P12
CPU_WEB
PC3B03U
I/O
Data Write Enable for Normal Mode.
Used for external data write operation,
functions on active low.
First Serial Peripheral Interface Clock for Stand
Alone Mode.
P13
CPU_AB0
PC3B03U
I/O
Address Data Select for Normal Mode.
Used to distinguish between Address and Data.
Low for Address, High for Data.
First Serial Peripheral Interface Data for Stand
Alone Mode
P14
CSB
PC3D21
I
QS5100 Chip Select.
Data Read/Write operation possible when ‘0’.
Cannot when ‘1’.
P15
IRQB
PC3B03U
I/O
CPU Interrrupt for Normal Mode.
Second Serial Peripheral Interface CS for Stand
Alone Mode.
P16
P17
P18
SPI2_CLK
SPI2_OUT
MODE0
PC3B03U
PC3B03U
PC3D21
I/O
I/O
I
Second Serial Peripheral Interface Clock for
Stand Alone Mode.
Second Serial Peripheral Interface Data for
Stand Alone Mode.
System Clock Mode
2X clock is used in System Clock when ‘0’, 1X
clock when ‘1’
System Select Mode
Normal Mode when ‘0’, Stand Alone Mode when
‘1’
Clock 2X Test Mode
Normal mode when ‘0’, Clock 2X test mode
when ‘1’
P19
MODE1
PC3D21
I
P20
MODE2
PC3D21
I
QS5100
Digital FX LSI
PIN NO
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
PAD NAME
MRSTB
XOUT
XIN
VDD
VSS
SIN
MCLK
WCLK
BCLK
SOUT
DRAM_ADDR[4]
DRAM_ADDR[5]
DRAM_ADDR[6]
DRAM_ADDR[7]
DRAM_ADDR[8]
DRAM_OEB
DRAM_UCASB
DRAM_LCASB
VDD
VSS
DRAM_ADDR[3]
DRAM_ADDR[2]
DRAM_ADDR[1]
DRAM_ADDR[0]
DRAM_RASB
DRAM_WEB
DRAM_DATA[3]
DRAM_DATA[2]
DRAM_DATA[1]
DRAM_DATA[0]
DRAM_DATA[4]
DRAM_DATA[5]
DRAM_DATA[6]
DRAM_DATA[7]
DRAM_DATA[8]
PAD TYPE
PC3D21U
PC3X11
PC3X11
PVDF
PV0F
PC3D21
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PVDF
PV0F
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3O03
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
I/O
I
O
I
P
P
I
O
O
O
O
O
O
O
O
O
O
O
O
P
P
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
Master Reset
Operates on active low.
Crystal Output
Crystal Input ( f = 8.192 ~ 12.288 Mhz )
Power
Ground
Serial Data Input
Serial Data System Clock
Serial Data Sample Rate Clock
Serial Data Bit Clock
Serial Data Output
DRAM Address
DRAM Address
DRAM Address
DRAM Address
DRAM Address
DRAM Output Enable
DRAM Upper Column Address Strobe
DRAM Lower Column Address Strobe
Power
Ground
DRAM Address
DRAM Address
DRAM Address
DRAM Address
DRAM Row Address strobe
DRAM Write Enable
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
QS5100
Digital FX LSI
PIN NO
P56
P57
P58
P59
P60
P61
P62
P63
P64
PAD NAME
VDD
VSS
DRAM_DATA[9]
DRAM_DATA[10]
DRAM_DATA[11]
DRAM_DATA[15]
DRAM_DATA[14]
DRAM_DATA[13]
DRAM_DATA[12]
PAD TYPE
PVDF
PV0F
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
PC3B03U
I/O
P
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Ground
DESCRIPTION
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
DRAM Data Inputs/Outputs
QS5100
Digital FX LSI
4. Block Diagram
DRAM I/F
CPU_DATA[0~7]
MCUInterface
CPU_RDB
CPU_WRB
CSB
CPU_AB0
IRQB
SOUT
FX DSP
SIN
MCLK
BCLK
WCLK
EIL
WIL
Lin
Wah
Rin
WIR
WO
TO
FO
CO
ROL
Tremolo
Flanger
Chorus
Reverb
Echo
TIL
TIR
FIL
FIR
CIL
CIR
RIL
RIR
ROR
EIR
EOL
/EOR
BOR
WSOR
TSOR
FSOR
CSOR
RSOR
BOL
WSOL
TSOL
FSOL
CSOL
RSOL
EQOL
Data out
EQOR
EQ
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