PIC18CXX2
High-Performance Microcontrollers with 10-Bit A/D
High Performance RISC CPU: Pin Diagrams
DIP, Windowed CERDIP
C-compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX MCLR/VPP 1 40 RB7
instruction set RA0/AN0 2 39 RB6
* Linear program memory addressing to 2M bytes RA1/AN1 3 38 RB5
* Linear data memory addressing to 4K bytes
RA2/AN2/VREF- 4 37 RB4
On-Chip Program Memory On-Chip
RA3/AN3/VREF+ 5 36 RB3/CCP2*
RA4/T0CKI 6 35 RB2/INT2
RA5/AN4/SS/LVDIN 7 PIC18C4X2 34 RB1/INT1
Device EPROM # Single Word RAM RE0/RD/AN5 8 33 RB0/INT0
(bytes) Instructions (bytes)
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
PIC18C242 16K 8192 512 VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
PIC18C252 32K 16384 1536 OSC1/CLKI 13 28 RD5/PSP5
PIC18C442 16K 8192 512 OSC2/CLKO/RA6 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
PIC18C452 32K 16384 1536 RC1/T1OSI/CCP2* 16 25 RC6/TX/CK
* Up to 10 MIPs operation: RC2/CCP1 17 24 RC5/SDO
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active RC3/SCK/SCL 18 23 RC4/SDI/SDA
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts RD0/PSP0 19 22 RD3/PSP3
* 8 x 8 Single Cycle Hardware Multiplier RD1/PSP1 20 21 RD2/PSP2
Peripheral Features:
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 40-pin PIC16C7X devices
High current sink/source 25 mA/25 mA Analog Features:
Three external interrupt pins 10-bit Analog-to-Digital Converter module (A/D)
with:
Timer0 module: 8-bit/16-bit timer/counter with - Fast sampling rate
8-bit programmable prescaler - Conversion available during sleep
- DNL = 1 LSb, INL = 1 LSb
Timer1 module: 16-bit timer/counter
Programmable Low-Voltage Detection (LVD)
Timer2 module: 8-bit timer/counter with 8-bit module
period register (time-base for PWM) - Supports interrupt on low voltage detection
* Timer3 module: 16-bit timer/counter Programmable Brown-out Reset (BOR)
Secondary oscillator clock option - Timer1/Timer3
Special Microcontroller Features:
Two Capture/Compare/PWM (CCP) modules. CCP
pins that can be configured as: Power-on Reset (POR), Power-up Timer (PWRT)
- Capture input: capture is 16-bit, and Oscillator Start-up Timer (OST)
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY) Watchdog Timer (WDT) with its own on-chip RC
- PWM output: PWM resolution is 1- to 10-bit. oscillator for reliable operation
Max. PWM freq. @:8-bit resolution = 156 kHz
10-bit resolution = 39 kHz Programmable code-protection
Power saving SLEEP mode
Master Synchronous Serial Port (MSSP) module. Selectable oscillator options including:
Two modes of operation:
- 3-wire SPITM (supports all 4 SPI modes) - 4X Phase Lock Loop (of primary oscillator)
- I2CTM master and slave mode - Secondary Oscillator (32 kHz) clock input
Addressable USART module: In-Circuit Serial Programming (ICSPTM) via two pins
- Supports interrupt on Address bit CMOS Technology:
Parallel Slave Port (PSP) module Low-power, high-speed EPROM technology
Fully static design
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low-power consumption
7/99 Microchip Technology Inc. Preliminary DS39026B-page 1
PIC18CXX2 RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 MCLR/VPP
Pin Diagrams
PLCC
NC RB7 RB6 RB5 RB4 NC
6 5 4 3 2 1 44 43 42 41 40
RA4/T0CKI 7 39 RB3/CCP2*
RA5/AN4/SS/LVDIN RB2/INT2
8 38 RB1/INT1
RE0/RD/AN5 RB0/INT0
RE1/WR/AN6 9 37 VDD
RE2/CS/AN7 VSS
10 36 RD7/PSP7
VDD RD6/PSP6
11 PIC18C4X2 35 RD5/PSP5
VSS 12 34 RD4/PSP4
OSC1/CLKI RC7/RX/DT
OSC2/CLKO/RA6 13 33
RC0/T1OSO/T1CKI
14 32
NC
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2* NC
TQFP 44 43 42 41 40 39 38 37 36 35 34
RC7/RX/DT 1 33 NC
RD4/PSP4 RC0/T1OSO/T1CKI
RD5/PSP5 2 32 OSC2/CLKO/RA6
RD6/PSP6 OSC1/CLKI
RD7/PSP7 3 31 VSS
VDD
VSS 4 30 RE2/AN7/CS
VDD RE1/AN6/WR
RB0/INT0 5 PIC18C4X2 29 RE0/AN5/RD
RB1/INT1 6 28 RA5/AN4/SS/LVDIN
RB2/INT2 RA4/T0CKI
RB3/CCP2* 7 27
8 26
9 25
10 24
11 12 13 14 15 16 17 18 19 20 21 22 23
NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 44-pin PIC16C7X devices
DS39026B-page 2 Preliminary 7/99 Microchip Technology Inc.
Pin Diagrams (Cont.'d) PIC18CXX2
DIP, JW RB7
RB6
MCLR/VPP 1 40 RB5
RB4
RA0/AN0 2 39 RB3/CCP2*
RB2/INT2
RA1/AN1 3 38 RB1/INT1
RB0/INT0
RA2/AN2/VREF- 4 37 VDD
VSS
RA3/AN3/VREF+ 5 36 RD7/PSP7
RD6/PSP6
RA4/T0CKI 6 35 RD5/PSP5
RD4/PSP4
RA5/AN4/SS/LVDIN 7 PIC18C4X2 34 RC7/RX/DT
RC6/TX/CK
RE0/RD/AN5 8 33 RC5/SDO
RC4/SDI/SDA
RE1/WR/AN6 9 32 RD3/PSP3
RD2/PSP2
RE2/CS/AN7 10 31
VDD 11 30
VSS 12 29
OSC1/CLKI 13 28
OSC2/CLKO/RA6 14 27
RC0/T1OSO/T1CKI 15 26
RC1/T1OSI/CCP2* 16 25
RC2/CCP1 17 24
RC3/SCK/SCL 18 23
RD0/PSP0 19 22
RD1/PSP1 20 21
NOTE: Pin compatible with 40-pin PIC16C7X devices
DIP, SOIC, JW
MCLR/VPP 1 28 RB7
RA0/AN0 2 27 RB6
RA1/AN1 3 26 RB5
RA2/AN2/VREF- 4 25 RB4
RA3/AN3/VREF+ 5 PIC18C2X2 24 RB3/CCP2*
RA4/T0CKI 6 23 RB2/INT2
RA5/AN4/SS/LVDIN 7 22 RB1/INT1
VSS 8 21 RB0/INT0
OSC1/CLKI 9 20 VDD
OSC2/CLKO/RA6 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2* 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 28-pin PIC16C7X devices
7/99 Microchip Technology Inc. Preliminary DS39026B-page 3
PIC18CXX2
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations ............................................................................................................................................................ 15
3.0 Reset .......................................................................................................................................................................................... 23
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Table Reads/Table Writes .......................................................................................................................................................... 53
6.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 61
7.0 Interrupts .................................................................................................................................................................................... 65
8.0 I/O Ports ..................................................................................................................................................................................... 77
9.0 Timer0 Module ........................................................................................................................................................................... 93
10.0 Timer1 Module ........................................................................................................................................................................... 97
11.0 Timer2 Module ......................................................................................................................................................................... 102
12.0 Timer3 Module ......................................................................................................................................................................... 105
13.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 109
14.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 117
15.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 151
16.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 167
17.0 Low Voltage Detect .................................................................................................................................................................. 175
18.0 Special Features of the CPU .................................................................................................................................................... 181
19.0 Instruction Set Summary .......................................................................................................................................................... 191
20.0 Development Support............................................................................................................................................................... 235
21.0 Electrical Characteristics .......................................................................................................................................................... 241
22.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 273
23.0 Packaging Information.............................................................................................................................................................. 275
Appendix A: Revision History ......................................................................................................................................................... 283
Appendix B: Device Differences..................................................................................................................................................... 283
Appendix C: Conversion Considerations........................................................................................................................................ 284
Appendix D: Migration from Baseline to Enhanced Devices .......................................................................................................... 284
Appendix E: Migration from Midrange to Enhanced Devices ......................................................................................................... 285
Appendix F: Migration from High-end to Enhanced Devices ......................................................................................................... 285
Index ................................................................................................................................................................................................. 287
On-Line Support................................................................................................................................................................................. 293
Reader Response .............................................................................................................................................................................. 294
PIC18CXX2 Product Identification System ........................................................................................................................................ 295
To Our Valued Customers
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DS39026B-page 4 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
1.0 DEVICE OVERVIEW The following two figures are device block diagrams
sorted by pin count; 28-pin for Figure 1-1 and 40-pin for
This document contains device-specific information for Figure 1-2. The 28-pin and 40-pin pinouts are listed in
the following four devices: Table 1-2 and Table 1-3 respectively.
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28 and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port (PSP)
implemented and the number of Analog-to-Digital (A/D)
converter input channels is reduced to 5. An overview
of features is shown in Table 1-1.
TABLE 1-1: DEVICE FEATURES
Features PIC18C242 PIC18C252 PIC18C442 PIC18C452
Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz
Program Memory (Bytes) 16K 32K
Program Memory (Instructions) 8192 16384 16K 32K
512 1536
Data Memory (Bytes) 16 16 8192 16384
Interrupt sources
I/O Ports Ports A, B, C Ports A, B, C 512 1536
Timers 4 4
2 2 17 17
Capture/Compare/PWM modules
Serial Communications MSSP, MSSP, Ports A, B, C, D, E Ports A, B, C, D, E
Addressable Addressable
Parallel Communications 4 4
10-bit Analog-to-Digital Module USART USART
-- -- 2 2
Resets (and Delays)
5 input channels 5 input channels MSSP, MSSP,
Programmable Low Voltage Detect POR, BOR, POR, BOR, Addressable Addressable
Programmable Brown-out Reset
Instruction Set Reset Instruction, Reset Instruction, USART USART
Packages Stack Full, Stack Full,
PSP PSP
Stack Underflow Stack Underflow
(PWRT, OST) (PWRT, OST) 8 input channels 8 input channels
Yes Yes
Yes Yes POR, BOR, POR, BOR,
75 Instructions 75 Instructions Reset Instruction, Reset Instruction,
28-pin DIP 28-pin DIP
28-pin SOIC 28-pin SOIC Stack Full, Stack Full,
28-pin JW 28-pin JW Stack Underflow Stack Underflow
(PWRT, OST) (PWRT, OST)
Yes Yes
Yes Yes
75 Instructions 75 Instructions
40-pin DIP 40-pin DIP
40-pin PLCC 40-pin PLCC
40-pin TQFP 40-pin TQFP
40-pin JW 40-pin JW
7/99 Microchip Technology Inc. Preliminary DS39026B-page 5
PIC18CXX2
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2> Data Latch PORTA RA0/AN0
Data RAM PORTB RA1/AN1
88 8 PORTC RA2/AN2/VREF-
RA3/AN3/VREF+
21 inc/dec logic RA4/T0CKI
21 RA5/AN4/SS/LVDIN
Address Latch 20 PCLATU PCLATH Address Latch RA6
Program Memory
(up to 2M Bytes) PCU PCH PCL (2) RB0/INT0
Data Latch Program Counter RB1/INT1
12 RB2/INT2
16 Address<12> RB3/CCP2(1)
RB7:RB4
4 12 4
BSR Bank0, F RC0/T1OSO/T1CKI
FSR0 RC1/T1OSI/CCP2(1)
31 Level Stack FSR1 12 RC2/CCP1
FSR2 RC3/SCK/SCL
RC4/SDI/SDA
Decode inc/dec RC5/SDO
logic RC6/TX/CK
TABLELATCH RC7/RX/DT
8
ROMLATCH
Instruction Instruction 8
Decode & Register
PRODH PRODL
Control Power-up
OSC2/CLKO Timer 3 8 x 8 Multiply
OSC1/CLKI Timing
Generation Oscillator 8
T1OSI Start-up Timer
T1OSO 4X PLL BIT OP WREG 8
Power-on
Precision Reset 8 8
Voltage
Reference Watchdog 8
Timer ALU<8>
Brown-out 8
Reset
MCLR VDD, VSS
Timer0 Timer1 Timer2 Timer3 A/D Converter
CCP1 CCP2 Master Addressable
Synchronous USART
Serial Port
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The
multiplexing combinations are device dependent.
DS39026B-page 6 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2> Data Latch PORTA RA0/AN0
PORTB RA1/AN1
88 8 Data RAM PORTC RA2/AN2/VREF-
(up to 4K PORTD RA3/AN3/VREF+
21 inc/dec logic address reach) PORTE RA4/T0CKI
21 RA5/AN4/SS/LVDIN
Address Latch 20 PCLATU PCLATH Address Latch RA6
Program Memory
(up to 2M Bytes) PCU PCH PCL (2) RB0/INT0
Data Latch Program Counter RB1/INT1
12 RB2/INT2
16 Address<12> RB3/CCP2(1)
RB7:RB4
4 12 4
RC0/T1OSO/T1CKI
BSR FSR0 Bank0, F RC1/T1OSI/CCP2(1)
RC2/CCP1
31 Level Stack FSR1 RC3/SCK/SCL
RC4/SDI/SDA
FSR2 12 RC5/SDO
RC6/TX/CK
Decode inc/dec RC7/RX/DT
logic
TABLELATCH RD7/PSP7:RD0/PSP0
8
RE0/AN5/RD
ROMLATCH RE1/AN6/WR
RE2/AN7/CS
Instruction Instruction 8
Decode & Register
PRODH PRODL
Control Power-up
OSC2/CLKO Timer 3 8 x 8 Multiply
OSC1/CLKI Timing
Generation Oscillator 8
T1OSI Start-up Timer
T1OSO 4X PLL BIT OP WREG 8
Power-on
Precision Reset 8 8
Voltage
Reference Watchdog 8
Timer ALU<8>
Brown-out 8
Reset
MCLR VDD, VSS
Timer0 Timer1 Timer2 Timer3 A/D Converter
CCP1 CCP2 Master Addressable Parallel Slave Port
Synchronous USART
Serial Port
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions.
The multiplexing combinations are device dependent.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 7
PIC18CXX2
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin Buffer
DIP SOIC Type Type Description
MCLR/VPP 1 1
MCLR
I ST Master clear (reset) input. This pin is an active low reset
VPP to the device.
P Programming voltage input.
NC -- ---- -- These pins should be left unconnected.
OSC1/CLKI 9 9
OSC1
I ST Oscillator crystal input or external clock source input.
CLKI ST buffer when configured in RC mode. CMOS otherwise.
I CMOS External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins).
OSC2/CLKO/RA6 10 10
OSC2 O -- Oscillator crystal output. Connects to crystal or
resonator in crystal oscillator mode.
CLKO O -- In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
RA6 I/O TTL cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2
RA0
AN0 I/O TTL Digital I/O.
Analog input 0.
I Analog
RA1/AN1 3 3
RA1
AN1 I/O TTL Digital I/O.
Analog input 1.
I Analog
RA2/AN2/VREF- 4 4
RA2
AN2 I/O TTL Digital I/O.
VREF- Analog input 2.
I Analog A/D Reference Voltage (Low) input.
I Analog
RA3/AN3/VREF+ 5 5
RA3
AN3 I/O TTL Digital I/O.
VREF+ Analog input 3.
I Analog A/D Reference Voltage (High) input.
I Analog
RA4/T0CKI 6 6
RA4
T0CKI I/O ST/OD Digital I/O. Open drain when configured as output.
Timer0 external clock input.
I ST
RA5/AN4/SS/LVDIN 7 7
RA5
AN4 I/O TTL Digital I/O.
SS Analog input 4.
LVDIN I Analog SPI Slave Select input.
Low Voltage Detect Input.
I ST
I Analog
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
DS39026B-page 8 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.'d)
Pin Name Pin Number Pin Buffer
DIP SOIC Type Type Description
RB0/INT0 21 21 PORTB is a bi-directional I/O port. PORTB can be software
RB0 I/O programmed for internal weak pull-ups on all inputs.
INT0 I
TTL Digital I/O.
RB1/INT1 22 22 ST External Interrupt 0.
RB1 I/O
INT1 I TTL
ST External Interrupt 1.
RB2/INT2 23 23
RB2 I/O TTL Digital I/O.
INT2 I ST External Interrupt 2.
RB3/CCP2 24 24 TTL Digital I/O.
RB3 I/O ST Capture2 input, Compare2 output, PWM2 output.
CCP2 I/O TTL Digital I/O.
RB4 25 25 I/O Interrupt on change pin.
RB5 26 26 I/O TTL Digital I/O.
Interrupt on change pin.
RB6 27 27 I/O TTL Digital I/O.
Interrupt on change pin.
I ST ICSP programming clock.
RB7 28 28 I/O TTL Digital I/O.
Interrupt on change pin.
I/O ST ICSP programming data.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 9
PIC18CXX2
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.'d)
Pin Name Pin Number Pin Buffer
DIP SOIC Type Type Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11
RC0 I/O ST Digital I/O.
Timer1 oscillator output.
T1OSO O -- Timer1/Timer3 external clock input.
T1CKI I ST
RC1/T1OSI/CCP2 12 12
RC1 I/O ST Digital I/O.
Timer1 oscillator input.
T1OSI I CMOS Capture2 input, Compare2 output, PWM2 output.
CCP2 I/O ST
RC2/CCP1 13 13
RC2
CCP1 I/O ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
I/O ST
RC3/SCK/SCL 14 14
RC3
SCK I/O ST Digital I/O.
SCL
I/O ST Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode
I/O ST
RC4/SDI/SDA 15 15
RC4
SDI I/O ST Digital I/O.
SDA
I ST SPI Data In.
I2C Data I/O.
I/O ST
RC5/SDO 16 16
RC5
SDO I/O ST Digital I/O.
SPI Data Out.
O --
RC6/TX/CK 17 17
RC6
TX I/O ST Digital I/O.
CK USART Asynchronous Transmit.
O -- USART Synchronous Clock.
(See related RX/DT)
I/O ST
RC7/RX/DT 18 18
RC7
RX I/O ST Digital I/O.
DT USART Asynchronous Receive.
I ST USART Synchronous Data.
(See related TX/CK)
I/O ST
VSS 8, 19 8, 19 P -- Ground reference for logic and I/O pins.
VDD 20 20 P -- Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
DS39026B-page 10 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Number Pin Buffer
Pin Name DIP PLCC TQFP Type Type Description
MCLR/VPP 1 2 18
MCLR
I ST Master clear (reset) input. This pin is an active
VPP low reset to the device.
P Programming voltage input.
NC -- -- -- These pins should be left unconnected.
OSC1/CLKI 13 14 30
OSC1
I ST Oscillator crystal input or external clock
CLKI source input. ST buffer when configured in
I CMOS RC mode. CMOS otherwise.
External clock source input. Always
associated with pin function OSC1. (See
related OSC1/CLKIN, OSC2/CLKOUT pins).
OSC2/CLKO/RA6 14 15 31
OSC2 O -- Oscillator crystal output. Connects to crystal
or resonator in crystal oscillator mode.
CLKO O -- In RC mode, OSC2 pin outputs CLKOUT,
which has 1/4 the frequency of OSC1 and
RA6 I/O TTL denotes the instruction cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19
RA0
AN0 I/O TTL Digital I/O.
Analog input 0.
I Analog
RA1/AN1 3 4 20
RA1
AN1 I/O TTL Digital I/O.
Analog input 1.
I Analog
RA2/AN2/VREF- 4 5 21
RA2
AN2 I/O TTL Digital I/O.
VREF- Analog input 2.
I Analog A/D Reference Voltage (Low) input.
I Analog
RA3/AN3/VREF+ 5 6 22
RA3
AN3 I/O TTL Digital I/O.
VREF+ Analog input 3.
I Analog A/D Reference Voltage (High) input.
I Analog
RA4/T0CKI 6 7 23
RA4
T0CKI I/O ST/OD Digital I/O. Open drain when configured as output.
Timer0 external clock input.
I ST
RA5/AN4/SS/LVDIN 7 8 24
RA5
AN4 I/O TTL Digital I/O.
SS Analog input 4.
LVDIN I Analog SPI Slave Select input.
Low Voltage Detect Input.
I ST
I Analog
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 11
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.'d)
Pin Number Pin Buffer
Pin Name DIP PLCC TQFP Type Type Description
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0 33 36 8
RB0 I/O
INT0 I TTL Digital I/O.
ST External Interrupt 0.
RB1/INT1 34 37 9
RB1 I/O
INT1 I TTL
ST External Interrupt 1.
RB2/INT2 35 38 10 TTL Digital I/O.
RB2 I/O ST External Interrupt 2.
INT2 I
RB3/CCP2 36 39 11 TTL Digital I/O.
RB3 I/O ST Capture2 input, Compare2 output, PWM2 output.
CCP2 I/O
RB4 37 41 14 I/O TTL Digital I/O.
Interrupt on change pin.
RB5 38 42 15 I/O TTL Digital I/O.
Interrupt on change pin.
RB6 39 43 16 I/O TTL Digital I/O.
Interrupt on change pin.
I ST ICSP programming clock.
RB7 40 44 17 I/O TTL Digital I/O.
Interrupt on change pin.
I/O ST ICSP programming data.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
DS39026B-page 12 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.'d)
Pin Number Pin Buffer
Pin Name DIP PLCC TQFP Type Type Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32
RC0 I/O ST Digital I/O.
Timer1 oscillator output.
T1OSO O -- Timer1/Timer3 external clock input.
T1CKI I ST
RC1/T1OSI/CCP2 16 18 35
RC1
T1OSI I/O ST Digital I/O.
CCP2 Timer1 oscillator input.
I CMOS Capture2 input, Compare2 output, PWM2 output.
I/O ST
RC2/CCP1 17 19 36
RC2
CCP1 I/O ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
I/O ST
RC3/SCK/SCL 18 20 37
RC3
SCK I/O ST Digital I/O.
SCL I/O ST Synchronous serial clock input/output for
I/O ST SPI mode.
Synchronous serial clock input/output for
I2C mode.
RC4/SDI/SDA 23 25 42
RC4
SDI I/O ST Digital I/O.
SDA
I ST SPI Data In.
I2C Data I/O.
I/O ST
RC5/SDO 24 26 43
RC5
SDO I/O ST Digital I/O.
SPI Data Out.
O --
RC6/TX/CK 25 27 44
RC6
TX I/O ST Digital I/O.
CK USART Asynchronous Transmit.
O -- USART Synchronous Clock.
(See related RX/DT)
I/O ST
RC7/RX/DT 26 29 1
RC7
RX I/O ST Digital I/O.
DT USART Asynchronous Receive.
I ST USART Synchronous Data.
(See related TX/CK)
I/O ST
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 13
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.'d)
Pin Number Pin Buffer
Pin Name DIP PLCC TQFP Type Type Description
PORTD is a bi-directional I/O port.
Parallel Slave Port (PSP) for interfacing to a micropro-
cessor port. These pins have TTL input buffers when
PSP module is enabled.
RD0/PSP0 19 21 38 I/O ST Digital I/O.
RD1/PSP1 20 22 39 I/O
RD2/PSP2 21 23 40 I/O TTL Parallel Slave Port Data.
RD3/PSP3 22 24 41 I/O
RD4/PSP4 27 30 2 I/O ST Digital I/O.
RD5/PSP5 28 31 3 I/O
RD6/PSP6 29 32 4 I/O TTL Parallel Slave Port Data.
RD7/PSP7 30 33 5 I/O
ST Digital I/O.
TTL Parallel Slave Port Data.
ST Digital I/O.
TTL Parallel Slave Port Data.
ST Digital I/O.
TTL Parallel Slave Port Data.
ST Digital I/O.
TTL Parallel Slave Port Data.
ST Digital I/O.
TTL Parallel Slave Port Data.
ST Digital I/O.
TTL Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5 8 9 25 I/O
RE0
RD ST Digital I/O.
Read control for parallel slave port.
AN5 TTL (See also WR and CS pins)
RE1/WR/AN6 Analog input 5.
Analog
RE1 Digital I/O.
WR 9 10 26 I/O Write control for parallel slave port.
ST (See CS and RD pins)
AN6 TTL Analog input 6.
RE2/CS/AN7
Analog Digital I/O.
RE2 Chip Select control for parallel slave port.
CS 10 11 27 I/O (See related RD and WR)
ST Analog input 7.
AN7 TTL
Analog
VSS 12, 31 13, 34 6, 29 P -- Ground reference for logic and I/O pins.
VDD 11, 32 12, 35 7, 28 P -- Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
DS39026B-page 14 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC
CONFIGURATIONS RESONATOR OPERATION
(HS, XT OR LP
2.1 Oscillator Types OSC CONFIGURATION)
The PIC18CXX2 can be operated in eight different C1(1) OSC1
oscillator modes. The user can program three configu-
ration bits (FOSC2, FOSC1, and FOSC0) to select one XTAL RF(3) To
of these eight modes: internal
logic
1. LP Low Power Crystal SLEEP
2. XT Crystal/Resonator RS(2) PIC18CXXX
3. HS High Speed Crystal/Resonator C2(1) OSC2
4. HS + PLL High Speed Crystal/Resonator with Note 1: See Table 2-1 and Table 2-2 for recom-
PLL enabled mended values of C1 and C2.
5. RC External Resistor/Capacitor Note 2: A series resistor (RS) may be required
for AT strip cut crystals.
6. RCIO External Resistor/Capacitor with
I/O pin enabled Note 3: RF varies with the crystal chosen.
7. EC External Clock
8. ECIO External Clock with I/O pin enabled
2.2 Crystal Oscillator/Ceramic FIGURE 2-2: EXTERNAL CLOCK INPUT
Resonators OPERATION (HS, XT OR LP
OSC CONFIGURATION)
In XT, LP, HS or HS-PLL oscillator modes, a crystal or Clock from OSC1
ceramic resonator is connected to the OSC1 and ext. system
OSC2 pins to establish oscillation. Figure 2-1 shows PIC18CXXX
the pin connections. An external clock source may also Open
be connected to the OSC1 pin in these modes, as OSC2
shown in Figure 2-2.
The PIC18CXX2 oscillator design requires the use of a
parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 15
PIC18CXX2
TABLE 2-1: CERAMIC RESONATORS 2.3 RC Oscillator
Ranges Tested: For timing insensitive applications, the "RC" and
"RCIO" device options offer additional cost savings.
Mode Freq OSC1 OSC2 The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
XT 455 kHz 68 - 100 pF 68 - 100 pF ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due
2.0 MHz 15 - 68 pF 15 - 68 pF to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between
4.0 MHz 15 - 68 pF 15 - 68 pF package types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
HS 8.0 MHz 10 - 68 pF 10 - 68 pF take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
16.0 MHz 10 - 22 pF 10 - 22 pF R/C combination is connected.
These values are for design guidance only. See In the RC oscillator mode, the oscillator frequency
notes at bottom of page. divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
Resonators Used: logic.
455 kHz Panasonic EFO-A455K04B 0.3%
2.0 MHz Murata Erie CSA2.00MG 0.5%
4.0 MHz Murata Erie CSA4.00MG 0.5%
8.0 MHz Murata Erie CSA8.00MT 0.5%
16.0 MHz Murata Erie CSA16.00MX 0.5%
All resonators used did not have built-in capacitors.
TABLE 2-2: CAPACITOR SELECTION FOR FIGURE 2-3: RC OSCILLATOR MODE
CRYSTAL OSCILLATOR
Crystal Cap. Range Cap. VDD
Freq C1 Range
Osc Type C2
REXT
LP 32.0 kHz 33 pF 33 pF OSC1 Internal
clock
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF CEXT PIC18CXXX
1.0 MHz 15 pF 15 pF VSS
OSC2/CLKO
4.0 MHz 15 pF 15 pF
FOSC/4
HS 4.0 MHz 15 pF 15 pF Recommended values: 3 k REXT 100 k
CEXT > 20pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz TBD TBD The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
These values are for design guidance only. See eral purpose I/O pin. The I/O pin becomes bit 6 of
notes at bottom of page. PORTA (RA6).
Crystals Used
32.0 kHz Epson C-001R32.768K-A 20 PPM
200 kHz STD XTL 200.000KHz 20 PPM 2.4 External Clock Input
1.0 MHz ECS ECS-10-13-1 50 PPM The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
4.0 MHz ECS ECS-40-20-1 50 PPM feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
8.0 MHz EPSON CA-301 8.000M-C 30 PPM tor startup time required after a Power-On-Reset or
after a recovery from SLEEP mode.
20.0 MHz EPSON CA-301 20.000M-C 30 PPM
In the EC oscillator mode, the oscillator frequency
Note 1: Recommended values of C1 and C2 are divided by 4 is available on the OSC2 pin. This signal
identical to the ranges tested (Table 2-1). may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
2: Higher capacitance increases the stability oscillator mode.
of the oscillator, but also increases the start-
up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
DS39026B-page 16 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 2-4: EXTERNAL CLOCK INPUT 2.5 HS/PLL
OPERATION
(EC OSC CONFIGURATION) A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
Clock from OSC1 quency of the incoming crystal oscillator signal by 4.
ext. system For an input clock frequency of 10 MHz, the internal
PIC18CXXX clock frequency will be multiplied to 40 MHz. This is
FOSC/4 useful for customers who are concerned with EMI due
OSC2 to high frequency crystals.
The ECIO oscillator mode functions like the EC mode, The PLL can only be enabled when the oscillator con-
except that the OSC2 pin becomes an additional gen- figuration bits are programmed for HS mode. If they
eral purpose I/O pin. The I/O pin becomes Bit 6 of are programmed for any other mode, the PLL is not
PORTA (RA6). Figure 2-5 shows the pin connections enabled and the system clock will come directly from
for the ECIO oscillator mode. OSC1.
FIGURE 2-5: EXTERNAL CLOCK INPUT The PLL is one of the modes of the FOSC<2:0> con-
OPERATION figuration bits. The oscillator mode is specified during
(ECIO CONFIGURATION) device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
Clock from OSC1
ext. system
PIC18CXXX
RA6
I/O (OSC2)
FIGURE 2-6: PLL BLOCK DIAGRAM
(from configuration HS Osc
bit register)
PLL Enable
OSC2 Crystal Phase Loop VCO
OSC1 Osc Comparator Filter
FIN
MUX SYSCLK
FOUT
Divide by 4
7/99 Microchip Technology Inc. Preliminary DS39026B-page 17
PIC18CXX2
2.6 Oscillator Switching Feature been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
The PIC18CXX2 devices include a feature that allows the system clock sources. The clock switching feature
the system clock source to be switched from the main is enabled by programming the Oscillator Switching
oscillator to an alternate low frequency clock source. Enable (OSCSEN) bit in Configuration Register1H to a
For the PIC18CXX2 devices, this alternate clock '0'. Clock switching is disabled in an erased device.
source is the Timer1 oscillator. If a low-frequency crys- See Section 9 for further details of the Timer1 oscillator.
tal (32 KHz, for example) has been attached to the See Section 18.0 for Configuration Register details.
Timer1 oscillator pins and the Timer1 oscillator has
FIGURE 2-7: DEVICE CLOCK SOURCES
OSC2 PIC18CXXX
Main Oscillator 4 x PLL Tosc/4
Sleep TOSC
OSC1 MUX TSCLK
T1OSO
T1OSI Timer1 Oscillator TT1P
T1OSCEN Clock
Enable Source
Oscillator
Clock Source option
for other modules
2.6.1 SYSTEM CLOCK SWITCH BIT Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
The system clock source switching is performed under Timer1 oscillator is enabled by setting the
software control. The system clock switch bit, SCS T1OSCEN bit in the Timer1 control register
(OSCCON<0>) controls the clock switching. When the (T1CON). If the Timer1 oscillator is not
SCS bit is '0', the system clock source comes from the enabled, then any write to the SCS bit will
main oscillator that is selected by the FOSC configura- be ignored (SCS bit forced cleared) and
tion bits in Configuration Register1H. When the SCS the main oscillator will continue to be the
bit is set, the system clock source will come from the system clock source.
Timer1 oscillator. The SCS bit is cleared on all forms
of reset.
Register 2-1: OSCCON Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
-- -- -- -- -- -- -- SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0
SCS: System Clock Switch bit
when OSCSEN configuration bit = '0' and T1OSCEN bit is set:
1 = Switch to Timer1 Oscillator/Clock pin
0 = Use primary Oscillator/Clock input pin
when OSCSEN and T1OSCEN are in other states:
bit is forced clear
Legend W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 18 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the
main oscillator to the Timer1 oscillator is shown in
The PIC18CXX2 devices contain circuitry to prevent Figure 2-8. The Timer1 oscillator is assumed to be
"glitches" when switching between oscillator sources. running all the time. After the SCS bit is set, the pro-
Essentially, the circuitry waits for eight rising edges of cessor is frozen at the next occurring Q1 cycle. After
the clock source that the processor is switching to. This eight synchronization cycles are counted from the
ensures that the new clock source is stable and that its Timer1 oscillator, operation resumes. No additional
pulse width will not be less than the shortest pulse delays are required after the synchronization cycles.
width of the two clock sources.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TT1P
T1OSI 1 2 3 4 5 6 7 8
OSC1
Tscs
TOSC TDLY
Internal
System
Clock
SCS
(OSCCON<0>)
Program PC PC + 2 PC + 4
Counter
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switch- If the main oscillator is configured for an external crys-
ing from the Timer1 oscillator to the main oscillator will tal (HS, XT, LP), then the transition will take place after
depend on the mode of the main oscillator. In addition an oscillator startup time (TOST) has occurred. A timing
to eight clock cycles of the main oscillator, additional diagram indicating the transition from the Timer1 oscil-
delays may take place. lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP)
Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI TOST 1 2 34 567 8
OSC1 TOSC TSCS
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC PC + 2 PC + 6
Note 1: TOST = 1024TOSC (drawing not to scale).
7/99 Microchip Technology Inc. Preliminary DS39026B-page 19
PIC18CXX2
If the main oscillator is configured for HS-PLL mode, an quency. A timing diagram indicating the transition from
oscillator startup time (TOST) plus an additional PLL the Timer1 oscillator to the main oscillator for HS-PLL
timeout (TPLL) will occur. The PLL timeout is typically 2 mode is shown in Figure 2-10.
ms and allows the PLL to lock to the main oscillator fre-
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI TOST TPLL
OSC1
OSC2
PLL Clock TOSC TSCS
Input 1 2 34 56 78
Internal System PC + 2 PC + 4
Clock
SCS
(OSCCON<0>)
Program Counter PC
Note 1: TOST = 1024TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC ing the transition from the Timer1 oscillator to the main
or ECIO modes, there is no oscillator startup timeout. oscillator for RC, RCIO, EC and ECIO modes is shown
Operation will resume after eight cycles of the main in Figure 2-11.
oscillator have been counted. A timing diagram indicat-
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI TOSC
12 34 5 6 7 8
OSC1
TSCS
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC PC + 2 PC + 4
Note 1: RC oscillator mode assumed.
DS39026B-page 20 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
2.7 Effects of Sleep Mode on the On-chip ing currents have been removed, sleep mode achieves
Oscillator the lowest current consumption of the device (only
leakage currents). Enabling any on-chip feature that
When the device executes a SLEEP instruction, the on- will operate during sleep will increase the current con-
chip clocks and oscillator are turned off and the device sumed during sleep. The user can wake from SLEEP
is held at the beginning of an instruction cycle (Q1 through external reset, Watchdog Timer Reset or
state). With the oscillator off, the OSC1 and OSC2 sig- through an interrupt.
nals will stop oscillating. Since all the transistor switch-
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull At logic low
high
RCIO Floating, external resistor should pull Configured as Port A, bit 6
high
ECIO Floating Configured as Port A, bit 6
EC Floating At logic low
LP, XT, and HS Feedback inverter disabled, at quies- Feedback inverter disabled, at quies-
cent voltage level cent voltage level
See Table 3-1, in the "Reset" section, for time-outs due to Sleep and MCLR reset.
2.8 Power-up Delays With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a power-on reset is differ-
Power up delays are controlled by two timers, so that no ent from other oscillator modes. The time-out sequence
external reset circuitry is required for most applications. is as follows: First the PWRT time-out is invoked after a
The delays ensure that the device is kept in RESET POR time delay has expired. Then the Oscillator Start-
until the device power supply and clock are stable. For up Timer (OST) is invoked. However, this is still not a
additional information on RESET operation, see the sufficient amount of time to allow the PLL to lock at high
"Reset" section. frequencies. The PWRT timer is used to provide an
additional fixed 2ms (nominal) time-out to allow the PLL
The first timer is the Power-up Timer (PWRT), which ample time to lock to the incoming clock frequency.
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 21
PIC18CXX2
NOTES:
DS39026B-page 22 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
3.0 RESET Power-on Reset, MCLR, WDT reset, Brown-out Reset,
MCLR reset during SLEEP and by the RESET instruc-
The PIC18CXXX differentiates between various kinds tion.
of reset:
Most registers are not affected by a WDT wake-up,
a) Power-on Reset (POR) since this is viewed as the resumption of normal oper-
b) MCLR reset during normal operation ation. Status bits from the RCON register, RI, TO, PD,
c) MCLR reset during SLEEP POR and BOR, are set or cleared differently in different
d) Watchdog Timer (WDT) Reset (during normal reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
operation) reset. See Table 3-3 for a full description of the reset
e) Programmable Brown-out Reset (BOR) states of all registers.
f) Reset Instruction
g) Stack Full reset A simplified block diagram of the on-chip reset circuit is
h) Stack Underflow reset shown in Figure 3-1.
Most registers are unaffected by a reset. Their status is The Enhanced MCU devices have a MCLR noise filter
unknown on POR and unchanged by all other resets. in the MCLR reset path. The filter will detect and ignore
The other registers are forced to a "reset state" on small pulses.
A WDT reset does not drive MCLR pin low.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Stack Full/Underflow Reset
Pointer
External Reset
MCLR SLEEP
VDD WDT WDT
Module Time-out
S
Reset
VDD rise
detect
Power-on Reset
Brown-out
Reset BOREN
OST/PWRT Chip_Reset
OST
R Q
10-bit Ripple counter
OSC1
PWRT
On-chip 10-bit Ripple counter
RC OSC(1)
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 23
PIC18CXX2
3.1 Power-On Reset (POR) 3.2 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when The Power-up Timer provides a fixed nominal time-out
VDD rise is detected. To take advantage of the POR cir- (parameter #33) only on power-up from the POR. The
cuitry, just tie the MCLR pin directly (or through a resis- Power-up Timer operates on an internal RC oscillator.
tor) to VDD. This will eliminate external RC components The chip is kept in reset as long as the PWRT is active.
usually needed to create a Power-on Reset delay. A The PWRT's time delay allows VDD to rise to an accept-
maximum rise time for VDD is specified (parameter able level. A configuration bit is provided to enable/dis-
D004). For a slow rise time, see Figure 3-2. able the PWRT.
When the device starts normal operation (exits the The power-up time delay will vary from chip-to-chip due
reset condition), device operating parameters (voltage, to VDD, temperature and process variation. See DC
frequency, temperature,...) must be met to ensure oper- parameter #33 for details.
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met. 3.3 Oscillator Start-up Timer (OST)
Brown-out Reset may be used to meet the voltage
start-up condition. The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
FIGURE 3-2: EXTERNAL POWER-ON PWRT delay is over (parameter #32). This ensures that
RESET CIRCUIT (FOR SLOW the crystal oscillator or resonator has started and stabi-
VDD POWER-UP) lized.
VDD The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
D R SLEEP.
C R1 3.4 PLL Lock Timeout
MCLR
With the PLL enabled, the timeout sequence following
PIC18CXXX a power-on reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
Note 1: External Power-on Reset circuit is required vide a fixed timeout that is sufficient for the PLL to lock
only if the VDD power-up slope is too slow. to the main oscillator frequency. This PLL lock timeout
The diode D helps discharge the capacitor (TPLL) is typically 2 ms and follows the oscillator startup
quickly when VDD powers down. timeout (OST).
2: R < 40 k is recommended to make sure 3.5 Brown-Out Reset (BOR)
that the voltage drop across R does not
violate the device's electrical specification. A configuration bit, BOREN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
3: R1 = 100 to 1 k will limit any current cuitry. If VDD falls below parameter D005 for greater
flowing into MCLR from external capacitor than parameter #35, the brown-out situation will reset
C in the event of MCLR/VPP pin break- the chip. A reset may not occur if VDD falls below
down due to Electrostatic Discharge parameter D005 for less than parameter #35. The chip
(ESD) or Electrical Overstress (EOS). will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and will
keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay.
DS39026B-page 24 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
3.6 Time-out Sequence Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
On power-up, the time-out sequence is as follows: First, Bringing MCLR high will begin execution immediately
PWRT time-out is invoked after the POR time delay has (Figure 3-5). This is useful for testing purposes or to
expired. Then, OST is activated. The total time-out will synchronize more than one PIC18CXXX device operat-
vary based on oscillator configuration and the status of ing in parallel.
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 3-3, Table 3-2 shows the reset conditions for some Special
Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 Function Registers, while Table 3-3 shows the reset
depict time-out sequences on power-up. conditions for all the registers.
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Wake-up from
Power-up (2) SLEEP or
Oscillator Oscillator Switch
Configuration PWRTE = 0 PWRTE = 1 Brown-out (2)
HS with PLL enabled (1) 72 ms + 1024Tosc + 2ms 1024Tosc + 2 ms 72 ms + 1024Tosc + 2ms 1024Tosc + 2 ms
HS, XT, LP 72 ms + 1024Tosc 1024Tosc 72 ms + 1024Tosc 1024Tosc
EC 72 ms -- 72 ms --
External RC 72 ms -- 72 ms --
Note 1: 2 ms = Nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal power-up timer delay
Register 3-1: RCON Register Bits and Positions
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PD POR BOR
IPEN LWRT -- RI TO
bit 0
bit 7
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition Program RCON RI TO PD POR BOR STKFUL STKUNF
Counter Register
Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u
MCLR Reset during normal 0000h 00-u uuuu u u u u u u u
operation
Software Reset during normal 0000h 0u-0 uuuu 0 u u u u u u
operation
Stack Full Reset during normal 0000h 0u-u uu11 u u u u u u 1
operation
Stack Underflow Reset during 0000h 0u-u uu11 u u u u u 1 u
normal operation
MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u
WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u
Interrupt wake-up from SLEEP PC + 2(1) uu-u 00uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, -- = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
7/99 Microchip Technology Inc. Preliminary DS39026B-page 25
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT
Brown-out Reset WDT Reset or Interrupt
Reset Instruction
Stack Resets
TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu
PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PCL 242 442 252 452 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 242 442 252 452 N/A N/A N/A
POSTINC0 242 442 252 452 N/A N/A N/A
POSTDEC0 242 442 252 452 N/A N/A N/A
PREINC0 242 442 252 452 N/A N/A N/A
PLUSW0 242 442 252 452 N/A N/A N/A
FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 242 442 252 452 N/A N/A N/A
POSTINC1 242 442 252 452 N/A N/A N/A
POSTDEC1 242 442 252 452 N/A N/A N/A
PREINC1 242 442 252 452 N/A N/A N/A
PLUSW1 242 442 252 452 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read '0'.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read '0'.
DS39026B-page 26 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d)
Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT
Brown-out Reset WDT Reset or Interrupt
Reset Instruction
Stack Resets
FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
INDF2 242 442 252 452 N/A N/A N/A
POSTINC2 242 442 252 452 N/A N/A N/A
POSTDEC2 242 442 252 452 N/A N/A N/A
PREINC2 242 442 252 452 N/A N/A N/A
PLUSW2 242 442 252 452 N/A N/A N/A
FSR2H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu
TMR0H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu
WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
RCON(4, 6) 242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu
TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PR2 242 442 252 452 1111 1111 1111 1111 1111 1111
T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu
SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read '0'.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read '0'.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 27
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d)
Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT
Brown-out Reset WDT Reset or Interrupt
Reset Instruction
Stack Resets
ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
ADCON1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu
CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
RCREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu
RCSTA 242 442 252 452 0000 000x 0000 000u uuuu uuuu
IPR2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu
PIR2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu(1)
PIE2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
IPR1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
242 442 252 452 -111 1111 -111 1111 -uuu uuuu
PIR1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(1)
242 442 252 452 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
242 442 252 452 -000 0000 -000 0000 -uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read '0'.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read '0'.
DS39026B-page 28 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d)
Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT
Brown-out Reset WDT Reset or Interrupt
Reset Instruction
Stack Resets
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA(5, 7) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5, 7) 242 442 252 452 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5, 7) 242 442 252 452 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read '0'.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read '0'.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 29
PIC18CXX2
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR TPWRT
INTERNAL POR
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
DS39026B-page 30 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
VDD 0V 1V 5V
MCLR TOST
INTERNAL POR TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD TPWRT
MCLR
IINTERNAL POR TOST
TPLL
PWRT TIME-OUT
OST TIME-OUT
PLL TIME-OUT
INTERNAL RESET
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 31
PIC18CXX2
NOTES:
DS39026B-page 32 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.0 MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
Program Memory
Data Memory
Each block has its own bus so that concurrent access
can occur.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all '0's (a NOP
instruction).
PIC18C252 and PIC18C452 have 32-KBytes of
EPROM, while PIC18C242 and PIC18C442 have
16-KBytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instruc-
tions, and PIC18CX42 devices can store up to 8K of
single word instructions.
The reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 33
PIC18CXX2
FIGURE 4-1: PROGRAM MEMORY MAP FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR PIC18C442/ AND STACK FOR PIC18C452/
242 252
PC<20:0> PC<20:0>
CALL,BSUB,RETURN 21 CALL,BSUB,RETURN 21
RETFIE,RETLW RETFIE,RETLW
Stack Level 1 Stack Level 1
Stack Level 31 Stack Level 31
Reset Vector 0000h Reset Vector 0000h
High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h
On-chip
Program Memory
3FFFh
4000h
On-chip
Program Memory
User Memory Space
User Memory Space
Read '0' 7FFFh
8000h
1FFFFFh
200000h Read '0'
1FFFFFh
200000h
DS39026B-page 34 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.2 Return Address Stack After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
The return address stack allows any combination of up set. The STKFUL bit can only be cleared in software or
to 31 program calls and interrupts to occur. The PC by a POR.
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed or an interrupt is The action that takes place when the stack becomes
acknowledged. The PC value is pulled off the stack on full depends on the state of the STVREN (stack over-
a RETURN, RETLW or a RETFIE instruction. PCLATU flow reset enable) configuration bit. Refer to Section 18
and PCLATH are not affected by any of the return for a description of the device configuration bits. If
instructions. STVREN is set (default) the 31st push will push the (PC
+ 2) value onto the stack, set the STKFUL bit, and reset
The stack operates as a 31 word by 21-bit RAM and a the device. The STKFUL bit will remain set and the
5-bit stack pointer, with the stack pointer initialized to stack pointer will be set to 0.
00000b after all resets. There is no RAM associated
with stack pointer 00000b. This is only a reset value. If STVREN is cleared, the STKFUL bit will be set on the
During a CALL type instruction causing a push onto the 31st push and the stack pointer will increment to 31.
stack, the stack pointer is first incremented and the The 32nd push will overwrite the 31st push (and so on),
RAM location pointed to by the stack pointer is written while STKPTR remains at 31.
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents When the stack has been popped enough times to
of the RAM location pointed to by the STKPTR is trans- unload the stack, the next pop will return a value of zero
ferred to the PC and then the stack pointer is decre- to the PC and sets the STKUNF bit, while the stack
mented. pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and Note: Returning a value of zero to the PC on an
the address on the top of the stack is readable and writ- underflow has the effect of vectoring the
able through SFR registers. Data can also be pushed program to the reset vector, where the
to or popped from the stack using the top-of-stack stack conditions can be verified and appro-
SFRs. Status bits indicate if the stack pointer is at or priate actions can be taken.
beyond the 31 levels provided.
4.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
4.2.2 RETURN STACK POINTER (STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At reset, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 35
PIC18CXX2
Register 4-1: STKPTR - Stack Pointer Register
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SP4 SP3 SP2 SP1 SP0
STKFUL STKUNF - R = Readable bit
4 3 2 1 bit0 W = Writeable bit
bit7 6 5 C = Clearable bit
U = Unimplemented bit,
Read as `0'
- n = Value at POR reset
bit 7(1): STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1): STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5: Unimplemented: Read as '0'
bit 4-0: SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and Bit 6 can only be cleared in user software or by a POR.
FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
TOSU TOSH TOSL 11111
0x00 0x1A 0x34 11110
11101
STKPTR<4:0>
00010
00011
Top of Stack 0x001A34 00010
0x000D58 00001
00000
4.2.3 PUSH AND POP INSTRUCTIONS 4.2.4 STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable, These resets are enabled by programming the
the ability to push values onto the stack and pull values STVREN configuration bit. When the STVREN bit is
off the stack without disturbing normal program execu- disabled, a full or underflow condition will set the appro-
tion is a desirable option. To push the current PC value priate STKFUL or STKUNF bit, but not cause a device
onto the stack, a PUSH instruction can be executed. reset. When the STVREN bit is enabled, a full or under-
This will increment the stack pointer and load the cur- flow will set the appropriate STKFUL or STKUNF bit
rent PC value onto the stack. TOSU, TOSH and TOSL and then cause a device reset. The STKFUL or
can then be modified to place a return address on the STKUNF bits are only cleared by the user software or
stack. a POR reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
DS39026B-page 36 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.3 Fast Register Stack 4.4 PCL, PCLATH and PCLATU
A "fast interrupt return" option is available for interrupts. The program counter (PC) specifies the address of the
A Fast Register Stack is provided for the STATUS, instruction to fetch for execution. The PC is 21-bits
WREG and BSR registers and are only one in depth. wide. The low byte is called the PCL register. This reg-
The stack is not readable or writable and is loaded with ister is readable and writable. The high byte is called
the current value of the corresponding register when the PCH register. This register contains the PC<15:8>
the processor vectors for an interrupt. The values in the bits and is not directly readable or writable. Updates to
registers are then loaded back into the working regis- the PCH register may be performed through the
ters if the fast return instruction is used to return from PCLATH register. The upper byte is called PCU. This
the interrupt. register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
A low or high priority interrupt source will push values be performed through the PCLATU register.
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be The PC addresses bytes in the program memory. To
used reliably for low priority interrupts. If a high priority prevent the PC from becoming misaligned with word
interrupt occurs while servicing a low priority interrupt, instructions, the LSB of PCL is fixed to a value of '0'.
the stack register valves stored by the low priority inter- The PC increments by 2 to address sequential instruc-
rupt will be overwritten. tions in the program memory.
If high priority interrupts are not disabled during low pri- The CALL, RCALL, GOTO and program branch
ority interrupts, users must save the key registers in instructions write to the program counter directly. For
software during a low priority interrupt. these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers The contents of PCLATH and PCLATU will be trans-
at the end of a subroutine call. To use the fast register ferred to the program counter by an operation that
stack for a subroutine call, a fast call instruction must be writes PCL. Similarly, the upper two bytes of the pro-
executed. gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
Example 4-1 shows a source code example that uses for computed offsets to the PC. (See Section 4.8.1)
the fast register stack.
4.5 Clocking Scheme/Instruction Cycle
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
CALL SUB1, FAST ;STATUS, WREG, BSR clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
;SAVED IN FAST REGISTER gram counter (PC) is incremented every Q1, the
;STACK instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
SUB1 through Q4. The clocks and instruction execution flow
is shown in Figure 4-4.
;RESTORE VALUES SAVED
RETURN FAST ;IN FAST REGISTER STACK
FIGURE 4-4: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 PC+2 PC+4
Fetch INST (PC+2) Fetch INST (PC+4)
Q1 Execute INST (PC) Execute INST (PC+2)
Q2 Internal
phase
Q3 clock
Q4
PC PC
OSC2/CLKOUT Fetch INST (PC)
(RC mode) Execute INST (PC-2)
7/99 Microchip Technology Inc. Preliminary DS39026B-page 37
PIC18CXX2
4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC)
incrementing in Q1.
An "Instruction Cycle" consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are In the execution cycle, the fetched instruction is latched
pipelined such that fetch takes one instruction cycle into the "Instruction Register" (IR) in cycle Q1. This
while decode and execute takes another instruction instruction is then decoded and executed during the
cycle. However, due to the pipelining, each instruction Q2, Q3, and Q4 cycles. Data memory is read during Q2
effectively executes in one cycle. If an instruction (operand read) and written during Q4 (destination
causes the program counter to change (e.g. GOTO) write).
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5
1. MOVLW 55h Fetch 1 Execute 1 Execute 2
Fetch 3
2. MOVWF PORTB Fetch 2
3. BRA SUB_1 Execute 3
Fetch 4
4. BSF PORTA, BIT3 (Forced NOP) Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
4.7 Instructions in Program Memory boundaries, the data contained in the instruction is a
word address. The word address is written to
The program memory is addressed in bytes. Instruc- PC<20:1>, which accesses the desired byte address
tions are stored as two bytes or four bytes in program in program memory. Instruction #2 in Figure 4-5
memory. The least significant byte of an instruction shows how the instruction "GOTO 000006h' is
word is always stored in a program memory location encoded in the program memory. Program branch
with an even address (LSB = '0'). Figure 4-5 shows an instructions which encode a relative address offset
example of how instruction words are stored in the pro- operate in the same manner. The offset value stored
gram memory. To maintain alignment with instruction in a branch instruction represents the number of sin-
boundaries, the PC increments in steps of 2 and the gle word instructions that the PC will be offset by.
LSB will always read '0'. (See Section 4.4) Section 19.0 provides further details of the instruction
set.
The CALL and GOTO instructions have an absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 LSB = 0 Word Address
Program Memory 55h
03h 000000h
Byte Locations 00h 000002h
23h 000004h
Instruction 1: MOVLW 055h 0Fh 56h 000006h
000008h
Instruction 2: GOTO 000006h EFh 00000Ah
00000Ch
F0h 00000Eh
000010h
Instruction 3: MOVFF 123h, 456h C1h 000012h
000014h
F4h
DS39026B-page 38 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.7.1 TWO-WORD INSTRUCTIONS the instruction is executed by itself (first word was
skipped), it will execute as a NOP. This action is neces-
The PIC18CXX2 devices have 4 two-word instructions: sary when the two word instruction is preceded by a
MOVFF, CALL, GOTO and LFSR. The second word of conditional instruction that changes the PC. A program
these instructions has the 4 MSB's set to 1's and is a example that demonstrates this concept is shown in
special kind of NOP instruction. The lower 12 bits of the Example 4-3. Refer to Section 19.0 for further details of
second word contain data to be used by the instruction. the instruction set.
If the first word of the instruction is executed, the data
in the second word is accessed. If the second word of
EXAMPLE 4-3: TWO-WORD INSTRUCTIONS
CASE 1:
Object code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction
1111 0100 0101 0110 ; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2: Source Code
Object code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110 REG1, REG2 ; Yes
0010 0100 0000 0000 ADDWF
; 2nd operand becomes NOP
REG3 ; continue code
4.8 Lookup Tables 4.8.2 TABLE READS/TABLE WRITES
Look-up tables are implemented two ways. These are: A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
Computed GOTO location.
Table Reads
Lookup table data may be stored 2 bytes per program
4.8.1 COMPUTED GOTO word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
A computed GOTO is accomplished by adding an offset latch (TABLAT) contains the data that is read from or
to the program counter (ADDWF PCL). written to program memory. Data is transferred to/from
program memory one byte at a time.
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions. A description of the Table Read/Table Write operation
WREG is loaded with an offset into the table before is shown in Section 5.0.
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 39
PIC18CXX2 4.9.2 SPECIAL FUNCTION REGISTERS
4.9 Data Memory Organization The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for controlling
The data memory is implemented as static RAM. Each the desired operation of the device. These registers are
register in the data memory has a 12-bit address, implemented as static RAM. A list of these registers is
allowing up to 4096 bytes of data memory. Figure 4-6 given in Table 4-1 and Table 4-2.
and Figure 4-7 show the data memory organization for
the PIC18CXX2 devices. The SFRs can be classified into two sets; those asso-
ciated with the "core" function and those related to the
Banking is required to allow more than 256 bytes to be peripheral functions. Those registers related to the
accessed. The data memory map is divided into as "core" are described in this section, while those related
many as 16 banks that contain 256 bytes each. The to the operation of the peripheral features are
lower 4 bits of the Bank Select Register (BSR<3:0>) described in the section of that peripheral feature.
select which bank will be accessed. The upper 4 bits
for the BSR are not implemented. The SFRs are typically distributed among the peripher-
als whose functions they control.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The The unused SFR locations will be unimplemented and
SFRs are used for control and status of the controller read as '0's. See Table 4-1 for addresses for the SFRs.
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user's appli-
cation. The SFRs start at the last location of Bank 15
(OxFFF) and grow downwards. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as '0's.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a 12-
bit address value that can be used to access any loca-
tion in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction.
The MOVFF instruction is a two word/two cycle instruc-
tion that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle regard-
less of the current BSR values, an Access Bank is
implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
4.9.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other resets.
Data RAM is available for use as GPR registers by all
instructions. The top half of bank 15 (0xF80 to 0xFFF)
contains SFRs. All other banks of data memory contain
GPR registers starting with bank 0.
DS39026B-page 40 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-6: DATA MEMORY MAP FOR PIC18C242/442
BSR<3:0> Data Memory Map
= 0000b
= 0001b 00h Access RAM 000h
Bank 0 GPR 07Fh
080h
FFh GPR 0FFh
00h 100h
Bank 1 1FFh
FFh
200h
Access Bank
00h
Access RAM low 7Fh
= 0010b Bank 2 Unused Access RAM high 80h
= 1110b to Read '00h' (SFR's) FFh
Bank 14
= 1111b 00h Unused EFFh When a = 0,
Bank 15 SFR F00h the BSR is ignored and the
F7Fh Access Bank is used.
FFh The first 128 bytes are
F80h General Purpose RAM
FFFh (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 41
PIC18CXX2
FIGURE 4-7: DATA MEMORY MAP FOR PIC18C252/452
BSR<3:0> Data Memory Map
= 0000b
= 0001b 00h Access RAM 000h
= 0010b Bank 0 GPR 07Fh
= 0011b GPR 080h
= 0100b FFh 0FFh
= 0101b 00h GPR 100h
Bank 1 GPR 1FFh
FFh 200h
00h
2FFh
Bank 2 300h
FFh 3FFh
00h 400h
Bank 3
4FFh
FFh 500h
Bank 4 GPR 5FFh Access Bank
600h
00h
00h Access RAM low 7Fh
Bank 5 GPR
Access RAM high 80h
FFh FFh
(SFR's)
= 0110b Bank 6 Unused When a = 0,
= 1110b to Read '00h' the BSR is ignored and the
Access Bank is used.
Bank 14 The first 128 bytes are
General Purpose RAM
= 1111b 00h Unused EFFh (from Bank 0).
Bank 15 SFR F00h The second 128 bytes are
Special Function Registers
FFh F7Fh (from Bank 15).
F80h
FFFh
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
DS39026B-page 42 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 4-1: SPECIAL FUNCTION REGISTER MAP
FFFh TOSU FDFh INDF2 (3) FBFh CCPR1H F9Fh IPR1
FFEh POSTINC2 (3) FBEh CCPR1L F9Eh PIR1
FFDh TOSH FDEh POSTDEC2 (3) FBDh CCP1CON F9Dh PIE1
FFCh PREINC2 (3) FBCh CCPR2H F9Ch --
FFBh TOSL FDDh PLUSW2 (3) FBBh CCPR2L F9Bh --
FFAh FSR2H FBAh CCP2CON F9Ah --
FF9h STKPTR FDCh FSR2L FB9h -- F99h --
FF8h STATUS FB8h -- F98h --
FF7h PCLATU FDBh TMR0H FB7h -- F97h --
FF6h TMR0L FB6h -- F96h TRISE (2)
FF5h PCLATH FDAh T0CON FB5h -- F95h TRISD (2)
FF4h PCL FD9h -- FB4h -- F94h TRISC
FF3h TBLPTRU FD8h OSCCON FB3h TMR3H F93h TRISB
FF2h TBLPTRH FD7h LVDCON FB2h TMR3L F92h TRISA
FF1h TBLPTRL FD6h WDTCON FB1h T3CON F91h --
FF0h RCON FB0h -- F90h --
FEFh TABLAT FD5h TMR1H FAFh SPBRG F8Fh --
FEEh TMR1L FAEh RCREG F8Eh --
FEDh PRODH FD4h T1CON FADh TXREG F8Dh
FECh PRODL FD3h TMR2 FACh TXSTA F8Ch LATE (2)
FEBh INTCON FD2h PR2 FABh RCSTA F8Bh LATD (2)
FEAh INTCON2 FD1h T2CON FAAh -- F8Ah LATC
FE9h INTCON3 FD0h SSPBUF FA9h -- F89h LATB
FE8h INDF0 (3) FCFh SSPADD FA8h -- F88h LATA
FE7h POSTINC0 (3) FCEh SSPSTAT FA7h -- F87h --
FE6h POSTDEC0 (3) FCDh SSPCON1 FA6h -- F86h --
FE5h PREINC0 (3) FCCh SSPCON2 FA5h -- F85h --
FE4h PLUSW0 (3) FCBh ADRESH FA4h -- F84h --
FE3h FSR0H FCAh ADRESL FA3h -- F83h
FE2h FSR0L FC9h ADCON0 FA2h IPR2 F82h PORTE (2)
FE1h WREG FC8h ADCON1 FA1h PIR2 F81h PORTD (2)
FE0h INDF1 (3) FC7h -- FA0h PIE2 F80h PORTC
POSTINC1 (3) FC6h PORTB
POSTDEC1 (3) FC5h PORTA
PREINC1 (3) FC4h
PLUSW1 (3) FC3h
FSR1H FC2h
FSR1L FC1h
BSR FC0h
Note 1: Unimplemented registers are read as '0'
2: This registers is not available on PIC18C2X2 devices
3: This is not a physical register
7/99 Microchip Technology Inc. Preliminary DS39026B-page 43
PIC18CXX2
TABLE 4-2: REGISTER FILE SUMMARY
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
(note 3)
TOSU -- -- -- Top-of-Stack upper Byte (TOS<20:16>) ---0 0000 ---0 0000
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 0000 0000
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 0000 0000
STKPTR STKFUL STKUNF -- Return Stack Pointer 00-0 0000 00-0 0000
PCLATU -- -- -- Holding Register for PC<20:16> ---0 0000 ---0 0000
PCLATH Holding Register for PC<15:8> 0000 0000 0000 0000
PCL PC Low Byte (PC<7:0>) 0000 0000 0000 0000
TBLPTRU -- -- bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 ---0 0000
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 0000 0000
TABLAT Program Memory Table Latch 0000 0000 0000 0000
PRODH Product Register High Byte xxxx xxxx uuuu uuuu
PRODL Product Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP 1111 -1-1 1111 -1-1
INTCON3 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF 11-0 0-00 11-0 0-00
INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) n/a n/a
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) n/a n/a
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) n/a n/a
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) n/a n/a
PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - n/a n/a
value of FSR0 offset by value in WREG
FSR0H -- -- -- -- Indirect Data Memory Address Pointer 0 High Byte ---- 0000 ---- 0000
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx uuuu uuuu
WREG Working Register xxxx xxxx uuuu uuuu
INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) n/a n/a
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) n/a n/a
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) n/a n/a
PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) n/a n/a
PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - n/a n/a
value of FSR1 offset by value in WREG
FSR1H -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte ---- 0000 ---- 0000
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx uuuu uuuu
BSR -- -- -- -- Bank Select Register ---- 0000 ---- 0000
INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) n/a n/a
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) n/a n/a
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) n/a n/a
PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) n/a n/a
PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - n/a n/a
value of FSR2 offset by value in WREG
FSR2H -- -- -- -- Indirect Data Memory Address Pointer 2 High Byte ---- 0000 ---- 0000
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx uuuu uuuu
STATUS -- -- -- N OV Z DC C ---x xxxx ---u uuuu
TMR0H Timer0 register high byte 0000 0000 0000 0000
TMR0L Timer0 register low byte xxxx xxxx uuuu uuuu
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read '0' in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
DS39026B-page 44 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 4-2: REGISTER FILE SUMMARY (Cont.'d)
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
(note 3)
OSCCON -- -- -- -- -- -- -- SCS ---- ---0 ---- ---0
LVDCON -- -- IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 --00 0101
WDTCON -- -- -- -- -- -- -- SWDTE ---- ---0 ---- ---0
RCON IPEN LWRT -- RI TO PD POR BOR 0q-1 11qq 0q-q qquu
TMR1H Timer1 Register High Byte xxxx xxxx uuuu uuuu
TMR1L Timer1 Register Low Byte xxxx xxxx uuuu uuuu
T1CON RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR2 Timer2 Register 0000 0000 0000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPADD SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 0000 0000
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0
ADCON1 ADFM ADCS2 -- -- PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu
CCP1CON -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx uuuu uuuu
CCP2CON -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
TMR3H Timer3 Register High Byte xxxx xxxx uuuu uuuu
TMR3L Timer3 Register Low Byte xxxx xxxx uuuu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
SPBRG USART1 Baud Rate Generator 0000 0000 0000 0000
RCREG USART1 Receive Register 0000 0000 0000 0000
TXREG USART1 Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read '0' in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 45
PIC18CXX2
TABLE 4-2: REGISTER FILE SUMMARY (Cont.'d)
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
(note 3)
IPR2 -- -- -- -- BCLIP LVDIP TMR3IP CCP2IP ---- 1111 ---- 1111
PIR2 -- -- -- -- BCLIF LVDIF TMR3IF CCP2IF ---- 0000 ---- 0000
PIE2 -- -- -- -- BCLIE LVDIE TMR3IE CCP2IE ---- 0000 ---- 0000
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISE IBF OBF IBOV PSP- -- Data Direction bits for PORTE 0000 -111 0000 -111
MODE
TRISD Data Direction Control Register for PORTD 1111 1111 1111 1111
TRISC Data Direction Control Register for PORTC 1111 1111 1111 1111
TRISB Data Direction Control Register for PORTB 1111 1111 1111 1111
TRISA -- TRISA6(1) Data Direction Control Register for PORTA -111 1111 -111 1111
LATE -- -- -- -- -- Read PORTE Data Latch, Write ---- -xxx ---- -uuu
PORTE Data Latch
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx uuuu uuuu
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx uuuu uuuu
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx uuuu uuuu
LATA -- LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx -uuu uuuu
PORTE Read PORTE pins, Write PORTE Data Latch ---- -000 ---- -000
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx uuuu uuuu
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx uuuu uuuu
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx uuuu uuuu
PORTA -- RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 -u0u 0000
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read '0' in all
other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4.10 Access Bank A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
The Access Bank is an architectural enhancement the Access Bank. This bit is denoted by the 'a' bit (for
which is very useful for C compiler code optimization. access bit).
The techniques used by the C compiler may also be
useful for programs written in assembly. When forced in the Access Bank (a = '0'), the last
address in Access RAM Low is followed by the first
This data memory region can be used for: address in Access RAM High. Access RAM High maps
the Special Function registers so that these registers
Intermediate computational values can be accessed without any software overhead. This
Local variables of subroutines is useful for testing status flags and modifying control
Faster context saving/switching of variables bits.
Common variables
Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
DS39026B-page 46 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.11 Bank Select Register (BSR) If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
The need for a large general purpose memory space STATUS register bits will be set/cleared as appropriate
dictates a RAM banking scheme. The data memory is for the instruction performed.
partitioned into sixteen banks. When using direct Each Bank extends up to FFh (256 bytes). All data
addressing, the BSR should be configured for the memory is implemented as static RAM.
desired bank. A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM Section 4.12 provides a description of indirect address-
address. The BSR<7:4> bits will always read '0's, and ing, which allows linear addressing of the entire RAM
writes will have no effect. space.
A MOVLB instruction has been provided in the instruc- 0
tion set to assist in selecting banks.
FIGURE 4-8: DIRECT ADDRESSING
Direct Addressing
BSR<3:0> 7 from opcode(3)
bank select(2) location select(3)
00h 01h 0Eh 0Fh
E00h F00h
000h 100h
Data
Memory(1)
0FFh 1FFh EFFh FFFh
Bank 0 Bank 1 Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank
(BSR<3:0>) to the registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 47
PIC18CXX2
4.12 Indirect Addressing, INDF and FSR If INDF0, INDF1 or INDF2 are read indirectly via an
Registers FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
Indirect addressing is a mode of addressing data mem- operation will be equivalent to a NOP instruction and the
ory, where the data memory address in the instruction STATUS bits are not affected.
is not fixed. An SFR register is used as a pointer to the
data memory location that is to be read or written. 4.12.1 INDIRECT ADDRESSING OPERATION
Since this pointer is in RAM, the contents can be mod-
ified by the program. This can be useful for data tables Each FSR register has an INDF register associated
in the data memory and for software stacks. Figure 4-9 with it, plus four additional register addresses. Per-
shows the operation of indirect addressing. This shows forming an operation on one of these five registers
the moving of the value to the data memory address determines how the FSR will be modified during indi-
specified by the value of the FSR register. rect addressing.
Indirect addressing is possible by using one of the When data access is done to one of the five INDFn
INDF registers. Any instruction using the INDF register locations, the address selected will configure the FSRn
actually accesses the register pointed to by the File register to:
Select Register, FSR. Reading the INDF register itself
indirectly (FSR = '0') will read 00h. Writing to the INDF Do nothing to FSRn after an indirect access (no
register indirectly results in a no-operation. The FSR change) - INDFn
register contains a 12-bit address, which is shown in
Figure 4-10. Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose Auto-increment FSRn after an indirect access
address is contained in the FSRn register (FSRn is a (post-increment) - POSTINCn
pointer). This is indirect addressing.
Auto-increment FSRn before an indirect access
Example 4-4 shows a simple use of indirect addressing (pre-increment) - PREINCn
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions. Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
EXAMPLE 4-4: HOW TO CLEAR RAM the FSRn register after an indirect access (no
(BANK1) USING INDIRECT change) - PLUSWn
ADDRESSING
When using the auto-increment or auto-decrement
LFSR 0x100, FSR0 ; features, the effect on the FSR is not reflected in the
NEXT CLRF POSTINC0 ; Clear INDF register STATUS register. For example, if the indirect address
; & inc pointer causes the FSR to equal '0', the Z bit will not be set.
BTFSS FSR0H, 1 ; All done w/ Bank1?
GOTO NEXT ; NO, clear next Incrementing or decrementing an FSR affects all 12
CONTINUE ; bits. That is, when FSRnL overflows from an increment,
; YES, continue FSRnH will be incremented automatically.
:
Adding these features allows the FSRn to be used as a
There are three indirect addressing registers. To stack pointer in addition to its uses for table operations
address the entire data memory space (4096 bytes), in data memory.
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are Each FSR has an address associated with it that per-
required. These indirect addressing registers are: forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
1. FSR0: composed of FSR0H:FSR0L configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
2. FSR1: composed of FSR1H:FSR1L indirect access. The FSR value is not changed.
3. FSR2: composed of FSR2H:FSR2L If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
In addition, there are registers INDF0, INDF1 and set), while an indirect write will be equivalent to a NOP
INDF2, which are not physically implemented. Reading (STATUS bits are not affected).
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register If an indirect addressing operation is done where the
being the address of the data. target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
If an instruction writes a value to INDF0, the value will increment/decrement functions.
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
DS39026B-page 48 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-9: INDIRECT ADDRESSING OPERATION
RAM 0h
Instruction Address
Executed
Opcode
FFFh
12
File Address = access of an indirect addressing register
BSR<3:0> 12 12
FSR
Instruction 48
Fetched
Opcode File
FIGURE 4-10: INDIRECT ADDRESSING
Indirect Addressing
11 FSR register 0
location select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 49
PIC18CXX2
4.13 STATUS Register For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 4-2, contains as 000u u1uu (where u = unchanged).
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any It is recommended, therefore, that only BCF, BSF,
other register. If the STATUS register is the destination SWAPF, MOVFF and MOVWF instructions are used to
for an instruction that affects the Z, DC, C, OV or N bits, alter the STATUS register, because these instruc-
then the write to these five bits is disabled. These bits tions do not affect the Z, C, DC, OV or N bits from
are set or cleared according to the device logic. There- the STATUS register. For other instructions not
fore, the result of an instruction with the STATUS regis- affecting any status bits, see Table 19-2.
ter as destination may be different than intended.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
Register 4-2: STATUS Register
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
N OV Z DC C
-- -- --
bit 0
bit 7
bit 7:5 Unimplemented: Read as '0'
bit 4
bit 3 N: Negative bit
bit2 This bit is used for signed arithmatic (2's complement). It indicates whether the result was neg-
bit 1 ative, (ALU MSB = 1)
1 = Result was negative
bit 0 0 = Result was positive
OV: Overflow bit
This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit mag-
nitude, which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmatic (in this arithmetic operation)
0 = No overflow occurred
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 50 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
4.13.1 RCON REGISTER Note 1: If the BOREN configuration bit is set, BOR
is '1' on Power-on Reset. If the BOREN
The Reset Control (RCON) register contains flag bits, configuration bit is clear, BOR is unknown
that allow differentiation between the sources of a on Power-on Reset.
device reset. These flags include the TO, PD, POR, The BOR status bit is a "don't care" and is
BOR and RI bits. This register is readable and writable. not necessarily predictable if the brown-
out circuit is disabled (the BOREN config-
uration bit is clear). BOR must then be set
by the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
Register 4-3: RCON Register
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
RI TO PD POR BOR
IPEN LWRT --
bit 0
bit 7
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR reset.
0 = Disable TBLWT to internal program memory; TBLWT only to external program memory
bit 5 Unimplemented: Read as '0'
bit 4 RI: Reset Instruction Flag bit
1 = The Reset instruction was not executed
0 = The Reset instruction was executed causing a device reset
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 51
PIC18CXX2
NOTES:
DS39026B-page 52 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.0 TABLE READS/TABLE WRITES Table Read operations retrieve data from program
memory and place it into the Data memory space.
Enhanced devices have two memory spaces: the pro- Figure 5-1 shows the operation of a Table Read with
gram memory space and the data memory space. The program and data memory.
program memory space is 16 bits wide, while the data Table Write operations store data from the data mem-
memory space is 8 bits wide. Table Reads and Table ory space into program memory. Figure 5-2 shows the
Writes have been provided to move data between operation of a Table Write with program and data mem-
these two memory spaces through an 8 bit register ory.
(TABLAT). Table operations work with byte entities. A table block
The operations that allow the processor to move data containing data is not required to be word aligned, so a
between the data and program memory spaces are: table block can start and end at any byte address. If a
Table Read (TBLRD) table write is being used to write an executable program
Table Write (TBLWT) to program memory, program instructions will need to
be word aligned.
FIGURE 5-1: TABLE READ OPERATION
TABLE LATCH (8-bit)
TABLE POINTER (1)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
PROGRAM MEMORY
Instruction: TBLRD* Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in
program memory
FIGURE 5-2: TABLE WRITE OPERATION TABLE LATCH (8-bit)
TABLAT
TABLE POINTER (1)
TBLPTRU TBLPTRH TBLPTRL
PROGRAM MEMORY
Instruction: TBLWT* Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in
program memory
7/99 Microchip Technology Inc. Preliminary DS39026B-page 53
PIC18CXX2
5.1 Control Registers 5.1.1 RCON REGISTER
Several control registers are used in conjunction with The LWRT bit specifies the operation of Table Writes to
the TBLRD and TBLWT instructions. These include the: internal memory when the VPP voltage is applied to the
TBLPTR registers MCLR pin. When the LWRT bit is set, the controller
TABLAT register continues to execute user code, but long table writes
RCON register are allowed (for programming internal program mem-
ory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR reset.
Register 5-1: RCON Register (Address: 08h)
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
TO PD POR BOR
IPEN LWRT -- RI
bit 0
bit 7
bit 7 IPEN: Interrupt Priority Enable
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note 1: Only cleared on a POR or MCLR reset.
This bit has no effect on TBLWTs to external program memory.
bit 5 Unimplemented: Read as '0'
bit 4 RI: Reset Instruction Flag bit
1 = No Reset instruction occurred
0 = A Reset instruction occurred
bit 3 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset nor POR reset occurred
0 = A Brown-out Reset nor POR reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 54 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.1.2 TABLAT - TABLE LATCH REGISTER address up to 2M bytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
The Table Latch (TABLAT) is an 8-bit register mapped and the Configuration bits.
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program The table pointer TBLPTR is used by the TBLRD and
memory and data memory. TBLWT instructions. These instructions can update
the TBLPTR in one of four ways based on the table
5.1.3 TBLPTR - TABLE POINTER REGISTER operation. These operations are shown in Table 5-1.
These operations on the TBLPTR only affect the low
The Table Pointer (TBLPTR) addresses a byte within order 21-bits.
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte and Low byte). These three registers (TBLP-
TRU:TBLPTRH:TBLPTRL) join to form a 22-bit wide
pointer. The low order 21-bits allow the device to
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLPTR is not modified
TBLRD*
TBLWT* TBLPTR is incremented after the read/write
TBLRD*+ TBLPTR is decremented after the read/write
TBLWT*+
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
7/99 Microchip Technology Inc. Preliminary DS39026B-page 55
PIC18CXX2
5.2 Internal Program Memory Read/ When a Table Write occurs to an even program mem-
Writes ory address (TBLPTR<0> = 0), the contents of TABLAT
are transferred to an internal holding register. This is
5.2.1 TABLE READ OVERVIEW (TBLRD) performed as a short write and the program memory
block is not actually programmed at this time. The hold-
The TBLRD instructions are used to read data from pro- ing register is not accessible by the user.
gram memory to data memory.
When a Table Write occurs to an odd program memory
TBLPTR points to a byte address in program space. address (TBLPTR,)>=1), a long write is started. During
Executing TBLRD places the byte pointed to into TAB- the long write, the contents of TABLAT are written to the
LAT. In addition, TBLPTR can be modified automati- high byte of the program memory block and the con-
cally for the next Table Read operation. tents of the holding register are transferred to the low
byte of the program memory block.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the Figure 5-3 shows the holding register and the program
one byte from program memory pointed to by TBLPTR. memory write blocks.
5.2.2 INTERNAL PROGRAM MEMORY WRITE If a single byte is to be programmed, the low (even) byte
BLOCK SIZE of the destination program word should be read using
TBLRD*, modified or changed, if required, and written
The internal program memory of PIC18CXXX devices back to the same address using TBLWT*+. The high
is written in blocks. For PIC18CXX2 devices, the write (odd) byte should be read using TBLRD*, modified or
block size is 2 bytes. Consequently, Table Write oper- changed if required, and written back to the same
ations to internal program memory are performed in address using TBLWT. The write to an odd address will
pairs, one byte at a time. cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
FIGURE 5-3: HOLDING REGISTER AND THE WRITE BLOCK
Program Memory (x 2-bits)
Block n Write Block
MSB
Holding Register
Block n + 1 The write to the MSB of the Write Block
Block n + 2 causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
DS39026B-page 56 Preliminary 7/99 Microchip Technology Inc.
5.2.2.1 OPERATION PIC18CXX2
The long write is what actually programs words of data 5.2.2.2 SEQUENCE OF EVENTS
into the internal memory. When a TBLWT to the MSB of
the write block occurs, instruction execution is halted. The sequence of events for programming an internal
During this time, programming voltage and the data program memory location should be:
stored in internal latches is applied to program memory.
1. Enable the interrupt that terminates the long
For a long write to occur: write. Disable all other interrupts.
1. MCLR/VPP pin must be at the programming volt- 2. Clear the source interrupt flag.
age 3. If Interrupt Service Routine execution is desired
2. LWRT bit must be set when the device wakes, enable global inter-
3. TBLWT to the address of the MSB of the write rupts.
4. Set LWRT bit in the RCON register.
block 5. Raise MCLR/VPP pin to the programming volt-
age, VPP.
If the LWRT bit is clear, a short write will occur and pro- 6. Clear the WDT (if enabled).
gram memory will not be changed. If the TBLWT is not 7. Set the interrupt source to interrupt at the
to the MSB of the write block, then the programming required time.
phase is not initiated. 8. Execute the table write for the lower (even) byte.
This will be a short write.
Setting the LWRT bit enables long writes when the 9. Execute the table write for the upper (odd) byte.
MCLR pin is taken to VPP voltage. Once the LWRT bit This will be a long write. The controller will go to
is set, it can be cleared only by performing a POR or sleep while programming. The interrupt wakes
MCLR reset. the controller.
10. If GIE was set, service the interrupt request.
To ensure that the memory location has been well pro- 11. Lower MCLR/VPP pin to VDD.
grammed, a minimum programming time is required. 12. Verify the memory location (table read).
The long write can be terminated after the program-
ming time has expired by a reset or an interrupt. Having
only one interrupt source enabled to terminate the long
write ensures that no unintended interrupts will prema-
turely terminate the long write.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 57
PIC18CXX2
5.2.3 INTERRUPTS Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
The long write must be terminated by a reset or any can either be vectored to the high or low priority Inter-
interrupt. rupt Service Routine (ISR) or continue execution from
where programming commenced.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program- In either case, the interrupt flag will not be cleared
ming will terminate. This will occur regardless of the when programming is terminated and will need to be
settings of interrupt priority bits, the GIE/GIEH bit or the cleared by the software.
PIE/GIEL bit.
TABLE 5-2: SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/ PIE/ Priority Interrupt Interrupt Action
GIEH GIEL
Enable Flag
X X X 0 X Long write continues even if interrupt
(default) flag becomes set during sleep.
X X X 1 0 Long write continues, will wake when
the interrupt flag is set.
0 0 X 1 1 Terminates long write,
(default) (default) executes next instruction. Interrupt flag
not cleared.
0 1 1 1 1 Terminates long write,
(default) high priority executes next instruction. Interrupt flag
(default) not cleared.
1 0 0 1 1 Terminates long write, executes next
(default) low instruction. Interrupt flag not cleared.
0 1 0 1 1 Terminates long write, branches to low
(default) low priority interrupt vector.
Interrupt flag can be cleared by ISR.
1 0 1 1 1 Terminates long write, branches to high
(default) high priority priority interrupt vector.
(default) Interrupt flag can be cleared by ISR.
DS39026B-page 58 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
5.2.4 UNEXPECTED TERMINATION OF WRITE
OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected reset, or an interrupt that
was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 59
PIC18CXX2
NOTES:
DS39026B-page 60 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
6.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
6.1 Introduction
Higher computational throughput
An 8 x 8 hardware multiplier is included in the ALU of Reduces code size requirements for multiply algo-
the PIC18CXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction rithms
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis- The performance increase allows the device to be used
ter pair (PRODH:PRODL). The multiplier does not in applications previously reserved for Digital Signal
affect any flags in the ALUSTA register. Processors.
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1: PERFORMANCE COMPARISON
Routine Multiply Method Program Cycles Time
Memory (Max) @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
8 x 8 unsigned Without hardware multiply 13 69 6.9 s 27.6 s 69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed Without hardware multiply 33 91 9.1 s 36.4 s 91 s
Hardware multiply 6 6 600 ns 2.4 s 6 s
16 x 16 unsigned Without hardware multiply 21 242 24.2 s 96.8 s 242 s
Hardware multiply 24 24 2.4 s 9.6 s 24 s
16 x 16 signed Without hardware multiply 52 254 25.4 s 102.6 s 254 s
Hardware multiply 36 36 3.6 s 14.4 s 36 s
7/99 Microchip Technology Inc. Preliminary DS39026B-page 61
PIC18CXX2
6.2 Operation EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required MOVFF ARG1L, WREG
when one argument of the multiply is already loaded in MULWF
the WREG register. ARG2L ; ARG1L * ARG2L ->
MOVFF
Example 6-2 shows the sequence to do an 8 x 8 signed MOVFF ; PRODH:PRODL
multiply. To account for the sign bits of the arguments, ;
each argument's most significant bit (MSb) is tested MOVFF PRODH, RES1 ;
and the appropriate subtractions are done. MULWF
PRODL, RES0 ;
MOVFF
MOVFF ARG1H, WREG
;
MOVFF ARG2H ; ARG1H * ARG2H ->
MULWF
; PRODH:PRODL
MOVFF
EXAMPLE 6-1: 8 x 8 UNSIGNED MULTIPLY ADDWF PRODH, RES3 ;
ROUTINE MOVFF
ADDWFC PRODL, RES2 ;
CLRF
MOVFF ARG1, WREG ; ADDWFC ARG1L, WREG
MULWF ;
ARG2 ; ARG1 * ARG2 -> MOVFF ARG2H ; ARG1L * ARG2H ->
MULWF
; PRODH:PRODL ; PRODH:PRODL
MOVFF
ADDWF PRODL, WREG ;
MOVFF
ADDWFC RES1, F ; Add cross
CLRF
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY ADDWFC PRODH, WREG ; products
ROUTINE
RES2, F ;
MOVFF ARG1, WREG WREG, F ;
MULWF ARG2
; ARG1 * ARG2 -> RES3, F ;
BTFSC ARG2, SB
SUBWF PRODH, F ; PRODH:PRODL ARG1H, WREG ;
MOVFF ARG2, WREG ; Test Sign Bit ARG2L ; ARG1H * ARG2L ->
BTFSC ARG1, SB
SUBWF PRODH, F ; PRODH = PRODH ; PRODH:PRODL
; - ARG1 PRODL, WREG ;
; Test Sign Bit RES1, F ; Add cross
; PRODH = PRODH PRODH, WREG ; products
; - ARG2 RES2, F ;
WREG, F ;
RES3, F ;
Example 6-3 shows the sequence to do a 16 x 16 Example 6-4 shows the sequence to do an 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm signed multiply. Equation 6-2 shows the algorithm
that is used. The 32-bit result is stored in 4 registers used. The 32-bit result is stored in four registers
RES3:RES0. RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
EQUATION 6-1: 16 x 16 UNSIGNED is tested and the appropriate subtractions are done.
MULTIPLICATION
ALGORITHM EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L ALGORITHM
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+ RES3:RES0
(ARG1L ARG2H 28)+ = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1L ARG2L) (ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216)+
(-1 ARG1H<7> ARG2H:ARG2L 216)
DS39026B-page 62 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
EXAMPLE 6-4: 16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFF ARG1L, WREG
MULWF
ARG2L ; ARG1L * ARG2L ->
MOVFF
MOVFF ; PRODH:PRODL
;
MOVFF PRODH, RES1 ;
MULWF
PRODL, RES0 ;
MOVFF
MOVFF ARG1H, WREG
;
MOVFF ARG2H ; ARG1H * ARG2H ->
MULWF
; PRODH:PRODL
MOVFF
ADDWF PRODH, RES3 ;
MOVFF
ADDWFC PRODL, RES2 ;
CLRF
ADDWFC ARG1L, WREG
;
MOVFF ARG2H ; ARG1L * ARG2H ->
MULWF
; PRODH:PRODL
MOVFF
ADDWF PRODL, WREG ;
MOVFF
ADDWFC RES1, F ; Add cross
CLRF
ADDWFC PRODH, WREG ; products
;
BTFSS RES2, F ;
GOTO
MOVFF WREG, F ;
SUBWF
MOVFF RES3, F ;
SUBWFB
; ARG1H, WREG ;
SIGN_ARG1
BTFSS ARG2L ; ARG1H * ARG2L ->
GOTO
MOVFF ; PRODH:PRODL
SUBWF
MOVFF PRODL, WREG ;
SUBWFB
; RES1, F ; Add cross
CONT_CODE
PRODH, WREG ; products
:
RES2, F ;
WREG, F ;
RES3, F ;
ARG2H, 7 ; ARG2H:ARG2L neg?
SIGN_ARG1 ; no, check ARG1
ARG1L, WREG ;
RES2 ;
ARG1H, WREG ;
RES3
ARG1H, 7 ; ARG1H:ARG1L neg?
CONT_CODE ; no, done
ARG2L, WREG ;
RES2 ;
ARG2H, WREG ;
RES3
7/99 Microchip Technology Inc. Preliminary DS39026B-page 63
PIC18CXX2
NOTES:
DS39026B-page 64 Preliminary 7/99 Microchip Technology Inc.
7.0 INTERRUPTS PIC18CXX2
The PIC18CXX2 devices have multiple interrupt When the IPEN bit is cleared (default state), the inter-
sources and an interrupt priority feature that allows rupt priority feature is disabled and interrupts are com-
each interrupt source to be assigned a high priority patible with PICmicro mid-range devices. In
level or a low priority level. The high priority interrupt compatibility mode, the interrupt priority bits for each
vector is at 000008h and the low priority interrupt vector source have no effect. INTCON<6> is the PEIE bit,
is at 000018h. High priority interrupt events will over- which enables/disables all peripheral interrupt sources.
ride any low priority interrupts that may be in progress. INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
There are ten registers which are used to control inter- 000008h in compatibility mode.
rupt operation. These registers are:
When an interrupt is responded to, the Global Interrupt
RCON Enable bit is cleared to disable further interrupts. If the
INTCON IPEN bit is cleared, this is the GIE bit. If interrupt prior-
ity levels are used, this will be either the GIEH or GIEL
INTCON2 bit. High priority interrupt sources can interrupt a low
INTCON3 priority interrupt.
PIR1, PIR2
The return address is pushed onto the stack and the
PIE1, PIE2 PC is loaded with the interrupt vector address
IPR1, IPR2 (000008h or 000018h). Once in the interrupt service
routine, the source(s) of the interrupt can be deter-
It is recommended that the Microchip header files sup- mined by polling the interrupt flag bits. The interrupt
plied with MPLAB be used for the symbolic bit names flag bits must be cleared in software before re-enabling
in these registers. This allows the assembler/compiler interrupts to avoid recursive interrupts.
to automatically take care of the placement of these bits
within the specified register. The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
Each interrupt source has three bits to control its oper- if priority levels are used), which re-enables interrupts.
ation. The functions of these bits are:
For external interrupt events, such as the INT pins or
Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency
occurred will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
Enable bit that allows program execution to Individual interrupt flag bits are set regardless of the
branch to the interrupt vector address when status of their corresponding enable bit or the GIE bit.
the flag bit is set
Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts glo-
bally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable it are set, the
interrupt will vector immediately to address 000008h or
000018h depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 65
PIC18CXX2
FIGURE 7-1: INTERRUPT LOGIC
Peripheral Interrupt Flag bit T0IF Wake-up if in SLEEP mode
Peripheral Interrupt Enable bit T0IE
Peripheral Interrupt Priority bit T0IP Interrupt to CPU
RBIF Vector to location
TMR1IF RBIE 0008h
TMR1IE RBIP GIEH/GIE
TMR1IP
INT0F Interrupt to CPU
XXXXIF INT0E Vector to Location
XXXXIE 0018h
XXXXIP INT1F GIEL\PEIE
INT1E
High Priority Interrupt Generation INT1P
INT2F
Low Priority Interrupt Generation INT2E
INT2P
IPE
IPE
GIEL/PEIE
IPE
Additional Peripheral Interrupts
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF T0IF
TMR1IE T0IE
TMR1IP T0IP
XXXXIF RBIF
XXXXIE RBIE
XXXXIP RBIP
Additional Peripheral Interrupts INT0F
INT0E
INT1F
INT1E
INT1P
INT2F
INT2E
INT2P
DS39026B-page 66 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
7.0.1 INTCON REGISTERS
The INTCON Registers are readable and writable
registers, which contains various enable, priority and
flag bits.
Register 7-1: INTCON Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
GIE/GIEH PEIE/GIEL
bit 0
bit 7
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all interrupts
0 = Disables all interrupts
bit 6 PEIE/GEIL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 67
PIC18CXX2
Register 7-2: INTCON2 Register
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP -- RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0:External Interrupt0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as '0'
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as '0'
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39026B-page 68 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Register 7-3: INTCON3 Register
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP -- INT2IE INT1IE -- INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 =High priority
0 =Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 =High priority
0 =Low priority
bit 5 Unimplemented: Read as '0'
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 =Enables the INT2 external interrupt
0 =Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 =Enables the INT1 external interrupt
0 =Disables the INT1 external interrupt
bit 2 Unimplemented: Read as '0'
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 =The INT2 external interrupt occurred
(must be cleared in software)
0 =The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 =The INT1 external interrupt occurred
(must be cleared in software)
0 =The INT1 external interrupt did not occur
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 69
PIC18CXX2
7.0.2 PIR REGISTERS 7.0.3 PIE REGISTERS
The PIR registers contain the individual flag bits for the The PIE registers contain the individual enable bits for
peripheral interrupts. Due to he number of peripheral the peripheral interrupts. Due to the number of periph-
interrupt sources, there are two Peripheral Interrupt eral interrupt sources, there are two Peripheral Inter-
Flag Registers (PIR1, PIR2). rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these periph-
Note 1: Interrupt flag bits get set when an interrupt eral interrupts.
condition occurs, regardless of the state of
its corresponding enable bit or the global 7.0.4 IPR REGISTERS
enable bit, GIE (INTCON<7>).
The IPR registers contain the individual priority bits for
Note 2: User software should ensure the appropri- the peripheral interrupts. Due to on the number of
ate interrupt flag bits are cleared prior to peripheral interrupt sources, there are two Peripheral
enabling an interrupt, and after servicing Interrupt Priority Registers (IPR1, IPR2). The operation
that interrupt. of the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
7.0.5 RCON REGISTER
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
Register 7-4: RCON Register
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
RI TO PD POR BOR
IPEN LWRT --
bit 0
bit 7
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable
For details of bit operation see Register 4-1
bit 5 Unimplemented: Read as '0'
bit 4 RI: Reset Instruction Flag bit
For details of bit operation see Register 4-1
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-1
bit 2 PD: Power-down Detection Flag bit
For details of bit operation see Register 4-1
bit 1 POR: Power-on Reset Status bit
For details of bit operation see Register 4-1
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-1
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 70 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Register 7-5: Peripheral Interrupt Request (Flag) Registers
PIR1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PIR2 -- -- -- -- BCLIF LVDIF TMR3IF CCP2IF
bit 7 bit 0
PIR1 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place
(must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
(must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full
(cleared when RCREG is read)
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty
(cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
(must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred
(must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed
(must be cleared in software)
0 = TMR1 register did not overflow
7/99 Microchip Technology Inc. Preliminary DS39026B-page 71
PIC18CXX2
Register 7-5: Peripheral Interrupt Request (Flag) Registers (cont'd)
PIR2 bit 7-4 Unimplemented: Read as '0'
bit 3
BCLIF: Bus Collision Interrupt Flag bit
bit 2 1 = A Bus Collision occurred
bit 1 (must be cleared in software)
0 = No Bus Collision occurred
bit 0
LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurred
(must be cleared in software)
0 = The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed
(must be cleared in software)
0 = TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred
(must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred
(must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set
- n = Value at POR reset '0' = Bit is cleared x = Bit is unknown
DS39026B-page 72 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Register 7-6: Peripheral Interrupt Enable Registers
PIE1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7
bit 0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
PIE2 -- -- -- -- BCLIE LVDIE TMR3IE CCP2IE
PIE1
bit 7 bit 0
PIE2
bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
bit 7-4 Unimplemented: Read as '0'
bit 3
bit 2 BCLIE: Bus Collision Interrupt Enable bit
bit 1 1 = Enabled
bit 0 0 = Disabled
LVDIE: Low-voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 73
PIC18CXX2
Register 7-7: Peripheral Interrupt Priority Registers
IPR1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
IPR2 -- -- -- -- BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
IPR1 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
IPR2
1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 7-4 Unimplemented: Read as '0'
bit 3
bit 2 BCLIP: Bus Collision Interrupt Priority bit
bit 1 1 = High priority
bit 0 0 = Low priority
LVDIP: Low-voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set
- n = Value at POR reset '0' = Bit is cleared x = Bit is unknown
DS39026B-page 74 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
7.0.6 INT0 INTERRUPT TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
External interrupts on the RB0/INT0, RB1/INT1 and enable bit T0IE (INTCON<5>). Interrupt priority for
RB2/INT2 pins are edge triggered: either rising if the Timer0 is determined by the value contained in the
corresponding INTEDGx bit is set in the INTCON2 reg- interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
ister, or falling, if the INTEDGx bit is clear. When a valid tion 8.0 for further details on the Timer0 module.
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by 7.0.8 PORTB INTERRUPT ON CHANGE
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be cleared in software in the interrupt ser- An input change on PORTB<7:4> sets flag bit RBIF
vice routine before re-enabling the interrupt. All exter- (INTCON<0>). The interrupt can be enabled/disabled
nal interrupts (INT0, INT1 and INT2) can wake-up the by setting/clearing enable bit RBIE (INTCON<3>).
processor from SLEEP, if bit INTxE was set prior to Interrupt priority for PORTB Interrupt on change is
going into SLEEP. If the global interrupt enable bit GIE determined by the value contained in the interrupt pri-
set, the processor will branch to the interrupt vector fol- ority bit RBIP (INTCON2<0>).
lowing wake-up.
7.1 Context Saving During Interrupts
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP During an interrupt, the return PC value is saved on the
(INTCON3<6>) and INT2IP (INTCON3<7>). There is stack. Additionally, the WREG, STATUS and BSR reg-
no priority bit associated with INT0. It is always a high isters are saved on the fast return stack. If a fast return
priority interrupt source. from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
7.0.7 TMR0 INTERRUPT ters in software. Depending on the user's application,
other registers may also need to be saved. Example 6-
In 8-bit mode (which is the default), an overflow (FFh 1 saves and restores the WREG, STATUS and BSR
00h) in the TMR0 register will set flag bit TMR0IF. In registers during an interrupt service routine.
16-bit mode, an overflow (FFFFh 0000h) in the
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR located anywhere
;
; USER ISR CODE ; Restore BSR
; ; Restore WREG
MOVFF BSR_TEMP, BSR ; Restore STATUS
MOVF W_TEMP, W
MOVFF STATUS_TEMP, STATUS
7/99 Microchip Technology Inc. Preliminary DS39026B-page 75
PIC18CXX2
NOTES:
DS39026B-page 76 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
8.0 I/O PORTS The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
Depending on the device selected, there are either five register reads and writes the latched output value for
ports or three ports available. Some pins of the I/O PORTA.
ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when The RA4 pin is multiplexed with the Timer0 module
a peripheral is enabled, that pin may not be used as a clock input to become the RA4/T0CKI pin. The RA4/
general purpose I/O pin. T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
Each port has three registers for its operation. These full CMOS output drivers.
registers are:
The other PORTA pins are multiplexed with analog
TRIS register (Data Direction register) inputs and the analog VREF+ and VREF- inputs. The
PORT register (reads the levels on the pins of the operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
device) Register1).
LAT register (output latch)
Note: On a Power-on Reset, these pins are con-
The data latch (LAT register) is useful for read-modify- figured as analog inputs and read as '0'.
write operations on the value that the I/O pins are driv-
ing. The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
8.1 PORTA, TRISA and LATA Registers The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a EXAMPLE 8-1: INITIALIZING PORTA
TRISA bit (=1) will make the corresponding PORTA pin
an input, (i.e., put the corresponding output driver in a CLRF PORTA ; Initialize PORTA by
hi-impedance mode). Clearing a TRISA bit (=0) will ; clearing output
make the corresponding PORTA pin an output, (i.e., put CLRF LATA ; data latches
the contents of the output latch on the selected pin). ; Alternate method
MOVLW 0x07 ; to clear output
Note: On a Power-on Reset, these pins are con- MOVWF ADCON1 ; data latches
figured as inputs and read as '0'. MOVLW 0xCF ; Configure A/D
; for digital inputs
Reading the PORTA register reads the status of the MOVWF TRISA ; Value used to
pins, whereas writing to it will write to the port latch. ; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
7/99 Microchip Technology Inc. Preliminary DS39026B-page 77
PIC18CXX2
FIGURE 8-1: BLOCK DIAGRAM OF FIGURE 8-3: BLOCK DIAGRAM OF RA6
RA3:RA0 AND RA5 PINS
ECRA6 or
RCRA6 enable
Data
Bus
RD LATA
Data RD LATA
Bus
D Q
WR LATA
or VDD D Q
PORTA P
CK Q WR LATA VDD
WR TRISA or P
Data Latch PORTA CK Q
Data Latch
D Q N I/O pin(1)
D Q N I/O pin(1)
CK Q VSS WR VSS
TRIS Latch TRISA CK Q
Analog ECRA6 or
input TRIS Latch RCRA6
mode Data Bus enable
RD TRISA TTL
input
buffer TTL
input
Q D RD TRISA buffer
EN Data Bus
RD PORTA
SS input (RA5 only) Q D
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS. EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 8-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data RD LATA N I/O pin(1)
Bus DQ
VSS
WR LATA CK Q
or Data Latch Schmitt
PORTA Trigger
DQ input
WR TRISA buffer
CK Q
TRIS Latch
RD TRISA
Q D
ENEN
RD PORTA
TMR0 Cock Input
Note 1: I/O pin has protection diodes to VSS only.
DS39026B-page 78 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 8-1: PORTA FUNCTIONS
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-
RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4/LVDIN bit5 TTL Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input
OSC2/CLKO/RA6 bit6 OSC2 or clock output or I/O pin
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR resets
PORTA -- RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
LATA -- Latch A Data Output Register --xx xxxx --uu uuuu
TRISA -- PORTA Data Direction Register --11 1111 --11 1111
ADCON1 ADFM ADCS2 -- -- PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 79
PIC18CXX2
8.2 PORTB, TRISB and LATB Registers FIGURE 8-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
PORTB is an 8-bit wide bi-directional port. The corre- RBPU(2)
sponding data direction register is TRISB. Setting a VDD
TRISB bit (=1) will make the corresponding PORTB pin Data Bus
an input, (i.e., put the corresponding output driver in a WR LATB P weak
hi-impedance mode). Clearing a TRISB bit (=0) will or pull-up
make the corresponding PORTB pin an output, ( i.e. put PORTB
the contents of the output latch on the selected pin). Data Latch I/O
DQ pin(1)
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB CK
register reads and writes the latched output value for
PORTB. TRIS Latch
DQ
WR TRISB CK TTL
Input
Buffer ST
Buffer
EXAMPLE 8-2: INITIALIZING PORTB
CLRF PORTB ; Initialize PORTB by RD TRISB
CLRF LATB ; clearing output
MOVLW 0xCF ; data latches RD LATB Latch
MOVWF TRISB ; Alternate method QD
; to clear output
; data latches RD PORTB EN Q1
; Value used to
; initialize data Set RBIF
; direction
; Set RB<3:0> as inputs From other QD
; RB<5:4> as outputs RB7:RB4 pins RD PORTB
; RB<7:6> as inputs
RBx/INTx EN
Q3
Each of the PORTB pins has a weak internal pull-up. A Note 1: I/O pins have diode protection to VDD and VSS.
single control bit can turn on all the pull-ups. This is per- 2: To enable weak pull-ups, set the appropriate TRIS
formed by clearing bit RBPU (INTCON2<7>). The bit(s) and clear the RBPU bit (INTCON2<7>).
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis- FIGURE 8-5: BLOCK DIAGRAM OF
abled on a Power-on Reset. RB2:RB0 PINS
RBPU(2)
Four of PORTB's pins, RB7:RB4, have an interrupt on Data Bus VDD
change feature. Only pins configured as inputs can WR Port
cause this interrupt to occur (i.e. any RB7:RB4 pin con- P weak
figured as an output is excluded from the interrupt on WR TRIS pull-up
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of Data Latch
PORTB. The "mismatch" outputs of RB7:RB4 are DQ
OR'ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>). CK I/O
TRIS Latch pin(1)
This interrupt can wake the device from SLEEP. The DQ
user, in the interrupt service routine, can clear the inter- TTL
rupt in the following manner: CK Input
Buffer
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch RD TRIS QD
condition. RD Port EN
b) Clear flag bit RBIF. RB0/INT
A mismatch condition will continue to set flag bit RBIF. Schmitt Trigger RD Port
Reading PORTB will end the mismatch condition and Buffer
allow flag bit RBIF to be cleared.
Note 1: I/O pins have diode protection to VDD and VSS.
The interrupt on change feature is recommended for 2: To enable weak pull-ups, set the appropriate TRIS
wake-up on key depression operation and operations bit(s) and clear the RBPU bit (OPTION_REG<7>).
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
DS39026B-page 80 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-6: BLOCK DIAGRAM OF RB3
VDD
RBPU(2) P weak
CCP2MX pull-up
CCP Output(3) 1 VDD
P
Enable (3) 0
CCP Output Data Latch I/O
Data Bus DQ Pin(1)
WR LATB or
WR PORTB CK N
TRIS Latch
WR TRISB D VSS
CK Q TTL
Input
Buffer
RD TRISB Q D
RD LATB
EN
RD PORTB
RD PORTB
CCP2 input(3)
Schmitt Trigger
Buffer CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (='0') in the configuration register.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 81
PIC18CXX2
TABLE 8-3: PORTB FUNCTIONS
Name
Bit# Buffer Function
RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input1. Internal software
programmable weak pull-up.
RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input2. Internal software programma-
ble weak pull-up.
RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input3. Internal software programma-
ble weak pull-up.
RB3/CCP2 (3) bit3 TTL/ST(4) Input/output pin. Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled. Internal software programmable
weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programma-
ble weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 8-4: SUMMARY OF REGISTERS
ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
POR, other resets
BOR
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
LATB LATB Data Output Register RBIF 1111 1111 1111 1111
RBIP 0000 000x 0000 000u
TRISB PORTB Data Direction Register INT1IF 1111 -1-1 1111 -1-1
11-0 0-00 11-0 0-00
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEH GIEL
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 -- TMR0IP --
INTCON3 INT2IP INT1IP -- INT2IE INT1IE -- INT2IF
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39026B-page 82 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
8.3 PORTC, TRISC and LATC Registers make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit set-
PORTC is an 8 bit wide bi-directional port. The corre- tings.
sponding Data Direction Register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin The pin override value is not loaded into the TRIS reg-
an input, (i.e., put the corresponding output driver in a ister. This allows read-modify-write of the TRIS register,
hi-impedance mode). Clearing a TRISC bit (=0) will without concern due to peripheral overrides.
make the corresponding PORTC pin an output, (i.e.,
put the contents of the output latch on the selected pin). EXAMPLE 8-3: INITIALIZING PORTC
The Data Latch register (LATC) is also memory CLRF PORTC ; Initialize PORTC by
mapped. Read-modify-write operations on the LATC CLRF LATC ; clearing output
register reads and writes the latched output value for MOVLW 0xCF ; data latches
PORTC. MOVWF TRISC ; Alternate method
; to clear output
PORTC is multiplexed with several peripheral functions ; data latches
(Table 8-5). PORTC pins have Schmitt Trigger input ; Value used to
buffers. ; initialize data
; direction
When enabling peripheral functions, care should be ; Set RC<3:0> as inputs
taken in defining TRIS bits for each PORTC pin. Some ; RC<5:4> as outputs
peripherals override the TRIS bit to make a pin an out- ; RC<7:6> as inputs
put, while other peripherals override the TRIS bit to
FIGURE 8-7: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Peripheral Data Out
RD LATC
Data Bus 1 RC7: RC0
WR LATC or DQ 0
WR PORTC CK Q Peripheral Out
RD TRISC Select
Peripheral Output Enable
WR TRISC DQ
CK Q
QD ST Buffer
Q CK
RD PORTC
Peripheral Data In
7/99 Microchip Technology Inc. Preliminary DS39026B-page 83
PIC18CXX2
TABLE 8-5: PORTC FUNCTIONS
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK bit6 ST Input/output port pin, Addressable USART Asynchronous Transmit, or
Addressable USART Synchronous Clock
RC7/RX/DT bit7 ST Input/output port pin, Addressable USART Asynchronous Receive, or
Addressable USART Synchronous Data
Legend: ST = Schmitt Trigger input
TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
POR, other resets
BOR
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
LATC LATC Data Output Register 1111 1111 1111 1111
TRISC PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS39026B-page 84 Preliminary 7/99 Microchip Technology Inc.
8.4 PORTD, TRISD and LATD Registers PIC18CXX2
This section is applicable to only the PIC18C4X2 FIGURE 8-8: PORTD BLOCK DIAGRAM
devices. IN I/O PORT MODE
PORTD is an 8 bit wide bi-directional port. The corre- Data RD LATD
sponding Data Direction Register is TRISD. Setting a Bus
TRISD bit (=1) will make the corresponding PORTD pin D Q
an input, (i.e., put the corresponding output driver in a WR LATD
hi-impedance mode). Clearing a TRISD bit (=0) will or CK I/O pin(1)
make the corresponding PORTD pin an output, (i.e., PORTD
put the contents of the output latch on the selected pin). Data Latch Schmitt
WR TRISD DQ Trigger
The Data Latch Register (LATD) is also memory input
mapped. Read-modify-write operations on the LATD CK buffer
register reads and writes the latched output value for TRIS Latch
PORTD.
RD TRISD
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or Q D
output.
ENEN
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit RD PORTD
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 8.6 for additional information on
the Parallel Slave Port (PSP).
EXAMPLE 8-4: INITIALIZING PORTD Note 1: I/O pins have protection diodes to VDD and VSS.
CLRF PORTD ; Initialize PORTD by
CLRF LATD ; clearing output
MOVLW 0xCF ; data latches
MOVWF TRISD ; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
7/99 Microchip Technology Inc. Preliminary DS39026B-page 85
PIC18CXX2
TABLE 8-7: PORTD FUNCTIONS
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 8-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
POR, other resets
BOR
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
LATD LATD Data Output Register xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Register 1111 1111 1111 1111
TRISE IBF OBF IBOV PSPMODE -- PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
DS39026B-page 86 Preliminary 7/99 Microchip Technology Inc.
8.5 PORTE, TRISE and LATE Registers PIC18CXX2
This section is only applicable to the PIC18C4X2 FIGURE 8-9: PORTE BLOCK DIAGRAM
devices. IN I/O PORT MODE
PORTE is an 3 bit wide bi-directional port. The corre- Data RD LATE
sponding Data Direction Register is TRISE. Setting a Bus DQ
TRISE bit (=1) will make the corresponding PORTE pin
an input, (i.e., put the corresponding output driver in a WR LATE CK I/O pin(1)
hi-impedance mode). Clearing a TRISE bit (=0) will or
make the corresponding PORTE pin an output, (i.e., PORTE Data Latch Schmitt
put the contents of the output latch on the selected pin). DQ Trigger
input
The Data Latch Register (LATE) is also memory WR TRISE CK buffer
mapped. Read-modify-write operations on the LATE TRIS Latch
register reads and writes the latched output value for
PORTE. RD TRISE
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 Q D
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger ENEN
input buffers.
RD PORTE
Figure 8-1 shows the TRISE register, which also con-
trols the parallel slave port operation. Capture2 input/ To Analog Converter
Compare2 output/PWM output when CCP2MX config-
uration bit is enabled. Note 1: I/O pins have protection diodes to VDD and VSS.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
EXAMPLE 8-5: INITIALIZING PORTE
CLRF PORTE ; Initialize PORTE by
; clearing output
CLRF LATE ; data latches
; Alternate method
MOVLW 0x07 ; to clear output
MOVWF ADCON1 ; data latches
MOVLW 0x03 ; Configure A/D
; for digital inputs
MOVWF TRISC ; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
7/99 Microchip Technology Inc. Preliminary DS39026B-page 87
PIC18CXX2
Register 8-1: TRISE Register
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE
-- TRISE2 TRISE1 TRISE0
bit 7
bit 0
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3 Unimplemented: Read as '0'
bit 2 TRISE2: RE2 direction control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 direction control bit
1 = Input
0 = Output
bit 0 TRISE0: RE0 direction control bit
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as `0' - n = Value at POR reset
DS39026B-page 88 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 8-9: PORTE FUNCTIONS
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode
or analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on Value on all
POR, other
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOR resets
PORTE -- -- -- -- -- RE2 RE1 RE0 ---- -000 ---- -000
LATE -- -- -- -- -- LATE Data Output Register ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE -- PORTE Data Direction Bits 0000 -111 0000 -111
ADCON1 ADFM ADCS2 -- -- PCFG3 PCFG2 PCFG1 PCFG0 --0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 89
PIC18CXX2
8.6 Parallel Slave Port FIGURE 8-10: PORTD AND PORTE BLOCK
DIAGRAM
The Parallel Slave Port is implemented on the 40-pin (PARALLEL SLAVE PORT)
devices only (PIC18C4X2).
Data Bus
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE DQ
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD WR LATD CK RDx
control input pin RE0/RD and WR control input pin or Pin
RE1/WR. PORTD
TTL
It can directly interface to an 8-bit microprocessor data Data Latch
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE Q D
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip RD PORTD ENEN
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>) RD LATD
must be configured as inputs (set). The A/D port con-
figuration bits PCFG2:PCFG0 (ADCON1<2:0>) must One bit of PORTD
be set, which will configure pins RE2:RE0 as digital I/O. Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
Read RD
TTL
Chip Select
TTL CS
Write WR
TTL
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 8-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS39026B-page 90 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-12: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
POR, BOR other resets
PORTD Port data latch when written; port pins when read xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
LATD LATD Data Output Bits 1111 1111 1111 1111
---- -000 ---- -000
TRISD PORTD Data Direction Bits ---- -xxx ---- -uuu
0000 -111 0000 -111
PORTE -- -- -- -- -- RE2 RE1 RE0 0000 000x 0000 000u
LATE -- -- -- -- -- LATE Data Output Bits 0000 0000 0000 0000
0000 0000 0000 0000
TRISE IBF OBF IBOV PSPMODE -- PORTE Data Direction Bits 0000 0000 0000 0000
--0- -000 --0- -000
INTCON GIE/ PEIE/ TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF
GIEH GIEL
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
ADCON1 ADFM ADCS2 -- -- PCFG3 PCFG2 PCFG1 PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by the Parallel Slave Port.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 91
PIC18CXX2
NOTES:
DS39026B-page 92 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
9.0 TIMER0 MODULE Figure 9-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 9-1 shows a
The Timer0 module has the following features: simplified block diagram of the Timer0 module in 16-bit
mode.
Software selectable as an 8-bit or 16-bit timer/
counter The T0CON register is a readable and writable register
that controls all the aspects of Timer0, including the
Readable and writable prescale selection.
Dedicated 8-bit software programmable prescaler
Clock source selectable to be external or internal
Interrupt on overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
Edge select for external clock
Register 9-1: T0CON: Timer0 Control Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
bit 6 1 = Enables Timer0
bit 5 0 = Stops Timer0
bit 4
bit 3 T08BIT: Timer0 8-bit/16-bit Control bit
bit 2:0 1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output
T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 93
PIC18CXX2
FIGURE 9-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
FOSC/4 0 Data Bus
8
0 Sync with
Internal TMR0
1 clocks
Set Interrupt
RA4/T0CKI Programmable 1 (2 Tcy delay) Flag bit TMR0IF
Pin
Prescaler on overflow
T0SE
3 PSA
T0PS2, T0PS1, T0PS0
T0CS
Note: Upon reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 9-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4 0 Sync with TMR0L TMR0 Set Interrupt
0 Internal 8 High Byte Flag bit TMR0IF
T0CKI pin Clocks
T0SE 1 (2 Tcy delay) 8 on overflow
Programmable 1
Prescaler
3 Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS PSA
8
TMR0H
8
Data Bus<7:0>
Note: Upon reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39026B-page 94 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
9.1 Timer0 Operation 9.2.1 SWITCHING PRESCALER ASSIGNMENT
Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software con-
trol, (i.e., it can be changed "on-the-fly" during program
Timer mode is selected by clearing the T0CS bit. In execution).
timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis- 9.3 Timer0 Interrupt
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this The TMR0 interrupt is generated when the TMR0 reg-
by writing an adjusted value to the TMR0 register. ister overflows from FFh to 00h in 8-bit mode or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
Counter mode is selected by setting the T0CS bit. In bit. The interrupt can be masked by clearing the
counter mode, Timer0 will increment either on every TMR0IE bit. The TMR0IE bit must be cleared in soft-
rising or falling edge of pin RA4/T0CKI. The increment- ware by the Timer0 module interrupt service routine
ing edge is determined by the Timer0 Source Edge before re-enabling this interrupt. The TMR0 interrupt
Select bit (T0SE). Clearing the T0SE bit selects the ris- cannot awaken the processor from SLEEP, since the
ing edge. Restrictions on the external clock input are timer is shut off during SLEEP.
discussed below.
9.4 16-Bit Mode Timer Reads and Writes
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure TMR0H is not the high byte of the timer/counter in 16-
the external clock can be synchronized with the internal bit mode, but is actually a buffered version of the high
phase clock (TOSC). Also, there is a delay in the actual byte of Timer0 (refer to Figure 9-1). The high byte of
incrementing of Timer0 after synchronization. the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
9.2 Prescaler high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
An 8-bit counter is available as a prescaler for the having to verify that the read of the high and low byte
Timer0 module. The prescaler is not readable or writ- were valid due to a rollover between successive reads
able. of the high and low byte.
The PSA and T0PS2:T0PS0 bits determine the pres- A write to the high byte of Timer0 must also take place
caler assignment and prescale ratio. through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
Clearing bit PSA will assign the prescaler to the Timer0 occurs to TMR0L. This allows all 16 bits of Timer0 to
module. When the prescaler is assigned to the Timer0 be updated at once.
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0, x....etc.) will clear the
prescaler count.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on Value on all
Bit 0 POR, BOR other resets
TMR0L Timer0 Module's Low Byte Register xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TMR0H Timer0 Module's High Byte Register 0000 000x 0000 000u
1111 1111 1111 1111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF --11 1111 --11 1111
T0PS0
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1
TRISA -- -- PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 95
PIC18CXX2
NOTES:
DS39026B-page 96 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
10.0 TIMER1 MODULE Figure 10-1 is a simplified block diagram of the Timer1
module.
The Timer1 module timer/counter has the following fea-
tures: Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
16-bit timer/counter module as well as contains the Timer1 oscillator enable
(Two 8-bit registers; TMR1H and TMR1L) bit (T1OSCEN). Timer1 can be enabled/disabled by
setting/clearing control bit TMR1ON (T1CON<0>).
Readable and writable (Both registers)
Internal or external clock select
Interrupt on overflow from FFFFh to 0000h
Reset from CCP module special event trigger
Register 10-1: T1CON: Timer1 Control Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16
bit 7 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
bit 6
bit 5:4 1 = Enables register Read/Write of TImer1 in one 16-bit operation
0 = Enables register Read/Write of Timer1 in two 8-bit operations
bit 3 Unimplemented: Read as '0'
bit 2 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 1 11 = 1:8 Prescale value
bit 0 10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 Oscillator is enabled
0 = Timer1 Oscillator is shut off.
The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 97
PIC18CXX2
10.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
Timer1 can operate in one of these modes: every rising edge of the external clock input or the
As a timer Timer1 oscillator, if enabled.
As a synchronous counter
As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is
The operating mode is determined by the clock select set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
bit, TMR1CS (T1CON<1>). become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal "reset input". This reset can
be generated by the CCP module (Section 13.0).
FIGURE 10-1: TIMER1 BLOCK DIAGRAM
TMR1IF CCP Special Event Trigger
Overflow
Interrupt TMR1 0 Synchronized
Flag Bit CLR
Clock Input
T1CKI/T1OSO TMR1H TMR1L
T1OSI TMR1ON 1
T1OSC on/off T1SYNC
T1OSCEN
Enable FOSC/4 1 Synchronize
Oscillator(1) Prescaler det
Internal 1, 2, 4, 8
SLEEP input
Clock 0
2
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This
eliminates power drain.
FIGURE 10-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
TMR1IF 8 TMR1 0 Synchronized
Overflow clock input
Interrupt Timer 1 TMR1L
flag bit high byte Synchronize
1 det
T13CKI/T1OSO TMR1ON T1SYNC
on/off SLEEP input
T1OSI
T1OSC 1 Prescaler
1, 2, 4, 8
T1OSCEN Fosc/4
Enable Internal 0 2
Oscillator(1) Clock
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
DS39026B-page 98 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
10.2 Timer1 Oscillator 10.3 Timer1 Interrupt
A crystal oscillator circuit is built-in between pins T1OSI The TMR1 Register pair (TMR1H:TMR1L) increments
(input) and T1OSO (amplifier output). It is enabled by from 0000h to FFFFh and rolls over to 0000h. The
setting control bit T1OSCEN (T1CON<3>). The oscilla- TMR1 Interrupt, if enabled, is generated on overflow,
tor is a low power oscillator rated up to 200 kHz. It will which is latched in interrupt flag bit TMR1IF (PIR1<0>).
continue to run during SLEEP. It is primarily intended This interrupt can be enabled/disabled by setting/clear-
for a 32 kHz crystal. Table 10-1 shows the capacitor ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
selection for the Timer1 oscillator.
10.4 Resetting Timer1 using a CCP Trigger
The user must provide a software time delay to ensure Output
proper start-up of the Timer1 oscillator.
TABLE 10-1: CAPACITOR SELECTION FOR If the CCP module is configured in compare mode to
THE ALTERNATE OSCILLATOR generate a "special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
Osc Type Freq C1 C2 conversion (if the A/D module is enabled).
LP 32 kHz TBD (1) TBD (1)
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
Crystal to be Tested: TMR1IF (PIR1<0>).
32.768 kHz Epson C-001R32.768K-A 20 Timer1 must be configured for either timer or synchro-
PPM nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
Note 1: Microchip suggests 33 pF as a starting reset operation may not work.
point in validating the oscillator circuit.
In the event that a write to Timer1 coincides with a spe-
2: Higher capacitance increases the stability cial event trigger from CCP1, the write will take prece-
of the oscillator, but also increases the dence.
start-up time.
In this mode of operation, the CCPR1H:CCPR1L regis-
3: Since each resonator/crystal has its own ters pair effectively becomes the period register for
characteristics, the user should consult the Timer1.
resonator/crystal manufacturer for appro-
priate values of external components. 10.5 Timer1 16-Bit Read/Write Mode
4: Capacitor values are for design guidance
only.
Timer1 can be configured for 16-bit reads and writes
(see Figure 10-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1 without having to determine whether a read of
the high byte followed by a read of the low byte is valid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The pres-
caler is only cleared on writes to TMR1L.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 99
PIC18CXX2
TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026B-page 100 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
NOTES:
7/99 Microchip Technology Inc. Preliminary DS39026B-page 101
PIC18CXX2 11.1 Timer2 Operation
11.0 TIMER2 MODULE Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
The Timer2 module timer has the following features: readable and writable, and is cleared on any device
8-bit timer (TMR2 register) reset. The input clock (FOSC/4) has a prescale option of
8-bit period register (PR2) 1:1, 1:4 or 1:16, selected by control bits
Readable and writable (both registers) T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
Software programmable prescaler (1:1, 1:4, 1:16) put of TMR2 goes through a 4-bit postscaler (which
Software programmable postscaler (1:1 to 1:16) gives a 1:1 to 1:16 scaling inclusive) to generate a
Interrupt on TMR2 match of PR2 TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
SSP module optional use of TMR2 output to gen-
The prescaler and postscaler counters are cleared
erate clock shift when any of the following occurs:
Timer2 has a control register shown in Register 11-1.
Timer2 can be shut off by clearing control bit TMR2ON a write to the TMR2 register
(T2CON<2>) to minimize power consumption. a write to the T2CON register
Figure 11-1 is a simplified block diagram of the Timer2 any device reset (Power-on Reset, MCLR reset,
module. Figure 11-1 shows the Timer2 control register.
The prescaler and postscaler selection of Timer2 are Watchdog Timer reset, or Brown-out Reset)
controlled by this register.
TMR2 is not cleared when T2CON is written.
Register 11-1: T2CON: Timer2 Control Register
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
-- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit bit 0
7
bit 7 Unimplemented: Read as '0'
bit 6:3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
bit 2
bit 1:0 0000 = 1:1 Postscale
0001 = 1:2 Postscale
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 102 Preliminary 7/99 Microchip Technology Inc.
11.2 Timer2 Interrupt PIC18CXX2
The Timer2 module has an 8-bit period register PR2. 11.3 Output of TMR2
Timer2 increments from 00h until it matches PR2 and The output of TMR2 (before the postscaler) is fed to the
then resets to 00h on the next increment cycle. PR2 is Synchronous Serial Port module, which optionally uses
a readable and writable register. The PR2 register is ini- it to generate the shift clock.
tialized to FFh upon reset.
FIGURE 11-1: TIMER2 BLOCK DIAGRAM
TMR2 Sets flag
output (1) bit TMR2IF
FOSC/4 Prescaler TMR2 Reset
1:1, 1:4, 1:16
Comparator Postscaler
2 PR2 EQ 1:1 to 1:16
T2CKPS1:T2CKPS0 4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR2 Timer2 module's register 0000 0000 0000 0000
T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 103
PIC18CXX2
NOTES:
DS39026B-page 104 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
12.0 TIMER3 MODULE Figure 12-1 is a simplified block diagram of the Timer3
module.
The Timer3 module timer/counter has the following fea-
tures: Register 12-1 shows the Timer3 control register. This
register controls the operating mode of the Timer3
16-bit timer/counter module and sets the CCP clock source.
(Two 8-bit registers; TMR3H and TMR3L)
Register 10-1 shows the Timer1 control register. This
Readable and writable (both registers) register controls the operating mode of the Timer1
Internal or external clock select module, as well as contains the Timer1 oscillator
Interrupt on overflow from FFFFh to 0000h enable bit (T1OSCEN), which can be a clock source for
Reset from CCP module trigger Timer3.
Register 12-1: T3CON: Timer3 Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 T3CCP2 T3CKPS1 T3CKPS0 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable
bit 6,3 1 = Enables register Read/Write of Timer3 in one 16-bit operation
bit 5:4 0 = Enables register Read/Write of Timer3 in two 8-bit operations
bit 2
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
bit 1 1x = Timer3 is the clock source for compare/capture CCP modules
bit 0 01 = Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP modules
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling
edge)
0 = Internal clock (Fosc/4)
TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 105
PIC18CXX2
12.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
Timer3 can operate in one of these modes: every rising edge of the Timer1 external clock input or
As a timer the Timer1 oscillator, if enabled.
As a synchronous counter
As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is
The operating mode is determined by the clock select set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
bit, TMR3CS (T3CON<1>). become inputs. That is, the TRISC<1:0> value is
ignored.
Timer3 also has an internal "reset input". This reset can
be generated by the CCP module (Section 12.0).
FIGURE 12-1: TIMER3 BLOCK DIAGRAM
TMR3IF 0 Synchronized
Overflow clock input
Interrupt TMR3H TMR3L
flag bit T1OSC Synchronize
TMR3ON 1 det
T1OSO/ on/off T3SYNC
T13CKI SLEEP input
(3) Prescaler
T1OSI 1, 2, 4, 8
1
2
T1OSCEN Fosc/4
Enable
Oscillator(1) Internal 0
Clock TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT MODE
Data bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
Set TMR3IF flag bit 8 TMR3 CCP Special Trigger Synchronized
on overflow T3CCPx clock input
0
Timer3 CLR
High Byte TMR3L
To Timer1 Clock Input TMR3ON 1
T1OSC on/off T3SYNC
T1OSO/ T1OSCEN FOSC/4 1 Synchronize
T13CKI Enable Internal Prescaler det
Oscillator(1) 1, 2, 4, 8
T1OSI Clock SLEEP input
0
2
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026B-page 106 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
12.2 Timer1 Oscillator 12.4 Resetting Timer3 Using a CCP Trigger
Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting If the CCP module is configured in compare mode to
the T1OSCEN (T1CON<3>) bit. The oscillator is a low generate a "special event trigger" (CCP1M3:CCP1M0
power oscillator rated up to 200 KHz. See Section 10.0 = 1011), this signal will reset Timer3.
for further details.
Note: The special event triggers from the CCP
12.3 Timer3 Interrupt module will not set interrupt flag bit
TMR3IF (PIR1<0>).
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The Timer3 must be configured for either timer or synchro-
TMR3 Interrupt, if enabled, is generated on overflow nized counter mode to take advantage of this feature. If
which is latched in interrupt flag bit TMR3IF (PIR2<1>). Timer3 is running in asynchronous counter mode, this
This interrupt can be enabled/disabled by setting/clear- reset operation may not work. In the event that a write
ing TMR3 interrupt enable bit TMR3IE (PIE2<1>). to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair effec-
tively becomes the period register for Timer3.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR2 -- -- -- -- BCLIF LVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIE2 -- -- -- -- BCLIE LVDIE TMR3IE CCP2IE 0000 0000 0000 0000
IPR2 -- -- -- -- BCLIP LVDIP TMR3IP CCP2IP 0000 0000 0000 0000
TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu
T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
T3CON -- T3CKPS2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 107
PIC18CXX2
NOTES:
DS39026B-page 108 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
13.0 CAPTURE/COMPARE/PWM The operation of CCP1 is identical to that of CCP2, with
(CCP) MODULES the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
Each CCP (Capture/Compare/PWM) module contains described with respect to CCP1.
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM Table 13-2 shows the interaction of the CCP modules.
master/slave Duty Cycle register. Table 13-1 shows the
timer resources of the CCP module modes.
Register 13-1: CCP1CON Register/CCP2CON Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
--
bit 7 -- DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7:6 Unimplemented: Read as '0'
bit 5:4
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
bit 3:0 Capture Mode:
Unused
Compare Mode:
Unused
PWM Mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match
(CCPIF bit is set, CCP pin is unaffected)
1011 = Compare mode,
Trigger special event (CCPIF bit is set)
11xx = PWM mode
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
7/99 Microchip Technology Inc. Preliminary DS39026B-page 109
PIC18CXX2
13.1 CCP1 Module 13.2 CCP2 Module
Capture/Compare/PWM Register1 (CCPR1) is com- Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR1L (low byte) and prised of two 8-bit registers: CCPR2L (low byte) and
CCPR1H (high byte). The CCP1CON register controls CCPR2H (high byte). The CCP2CON register controls
the operation of CCP1. All are readable and writable. the operation of CCP2. All are readable and writable.
TABLE 13-1: CCP MODE - TIMER RESOURCE
CCP Mode Timer Resource
Capture Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2
TABLE 13-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode Interaction
Capture Capture TMR1 or TMR3 time-base. Time base can be different for each CCP.
Capture Compare The compare could be configured for the special event trigger, which clears either TMR1
or TMR3 depending upon which time base is used.
Compare Compare
The compare(s) could be configured for the special event trigger, which clears TMR1 or
PWM PWM TMR3 depending upon which time base is used.
PWM Capture The PWMs will have the same frequency and update rate
PWM Compare (TMR2 interrupt).
None
None
DS39026B-page 110 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
13.3 Capture Mode 13.3.3 SOFTWARE INTERRUPT
In Capture mode, CCPR1H:CCPR1L captures the 16- When the Capture mode is changed, a false capture
bit value of the TMR1 or TMR3 registers when an event interrupt may be generated. The user should keep bit
occurs on pin RC2/CCP1. An event is defined as: CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
every falling edge change in operating mode.
every rising edge
every 4th rising edge 13.3.4 CCP PRESCALER
every 16th rising edge
There are four prescaler settings, specified by bits
An event is selected by control bits CCP1M3:CCP1M0 CCP1M3:CCP1M0. Whenever the CCP module is
(CCP1CON<3:0>). When a capture is made, the inter- turned off or the CCP module is not in capture mode,
rupt request flag bit CCP1IF (PIR1<2>) is set. It must the prescaler counter is cleared. This means that any
be cleared in software. If another capture occurs before reset will clear the prescaler counter.
the value in register CCPR1 is read, the old captured
value will be lost. Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
13.3.1 CCP PIN CONFIGURATION not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 13-1 shows the recom-
In Capture mode, the RC2/CCP1 pin should be config- mended method for switching between capture pres-
ured as an input by setting the TRISC<2> bit. calers. This example also clears the prescaler counter
and will not generate the "false" interrupt.
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition. EXAMPLE 13-1: CHANGING BETWEEN
CAPTURE PRESCALERS
13.3.2 TIMER1/TIMER3 MODE SELECTION CLRF CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
The timers that are to be used with the capture feature ; new prescaler mode
(either Timer1 and/or Timer3) must be running in timer MOVWF CCP1CON ; value and CCP ON
mode or synchronized counter mode. In asynchronous ; Load CCP1CON with
counter mode, the capture operation may not work. ; this value
The timer to be used with each CCP module is selected
in the T3CON register.
FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H TMR3L
Set flag bit CCP1IF
Prescaler T3CCP2 TMR3
1, 4, 16 Enable
CCP1 Pin CCPR1H CCPR1L
and T3CCP2 TMR1
edge detect Enable
TMR1H TMR1L
CCP1CON<3:0>
Q's
Set flag bit CCP2IF TMR3H TMR3L
T3CCP1
T3CCP2
Prescaler TMR3
1, 4, 16 Enable
CCP2 Pin CCPR2H CCPR2L
and T3CCP2 TMR1 TMR1L
edge detect T3CCP1 Enable
CCP2CON<3:0> TMR1H
Q's
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PIC18CXX2
13.4 Compare Mode 13.4.2 TIMER1/TIMER3 MODE SELECTION
In Compare mode, the 16-bit CCPR1 (CCPR2) register Timer1 and/or Timer3 must be running in Timer mode
value is constantly compared against either the TMR1 or Synchronized Counter mode if the CCP module is
register pair value or the TMR3 register pair value. using the compare feature. In Asynchronous Counter
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin mode, the compare operation may not work.
is:
13.4.3 SOFTWARE INTERRUPT MODE
driven High
driven Low When generate software interrupt is chosen, the CCP1
toggle output (High to Low or Low to High) pin is not affected. Only a CCP interrupt is generated (if
remains Unchanged enabled).
The action on the pin is based on the value of control 13.4.4 SPECIAL EVENT TRIGGER
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set. In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
13.4.1 CCP PIN CONFIGURATION The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
The user must configure the CCPx pin as an output by effectively be a 16-bit programmable period register for
clearing the appropriate TRISC bit. Timer1.
Note: Clearing the CCP1CON register will force The special trigger output of CCPx resets either the
the RC2/CCP1 compare output latch to the TMR1 or TMR3 register pair. Additionally, the CCP2
default low level. This is not the data latch. Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 interrupt flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set flag bit CCP1IF
RC2/CCP1 QS Output match CCPR1H CCPR1L
Pin R Logic Comparator
TRISC<2> CCP1CON<3:0> T3CCP2 01
Output Enable Mode Select
TMR1H TMR1L TMR3H TMR3L
Special Event Trigger
RC1/CCP2 QS Output Set flag bit CCP2IF T3CCP1 01
Pin R Logic T3CCP2 Comparator
CCPR2H CCPR2L
TRISC<1> match
Output Enable
CCP2CON<3:0>
Mode Select
DS39026B-page 112 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 13-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
0000 000u
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
GIEH GIEL 0000 0000
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 1111 1111
uuuu uuuu
TRISC PORTC Data Direction Register 1111 1111 uuuu uuuu
--uu uuuu
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx --00 0000
uuuu uuuu
T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 uuuu uuuu
--00 0000
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx 0000 0000
0000 0000
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx 0000 0000
uuuu uuuu
CCP1CON -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 uuuu uuuu
-uuu uuuu
CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx
CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx
CCP2CON -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
PIR2 -- -- -- -- BCLIF LVDIF TMR3IF CCP2IF 0000 0000
PIE2 -- -- -- -- BCLIE LVDIE TMR3IE CCP2IE 0000 0000
IPR2 -- -- -- -- BCLIP LVDIP TMR3IP CCP2IP 0000 0000
TMR3L Holding register for the Least Significant Byte of the 16-bit TMR3 register xxxx xxxx
TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register xxxx xxxx
T3CON -- T3CKPS2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by Capture and Timer1.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2x2 devices. Always maintain these bits clear.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 113
PIC18CXX2
13.5 PWM Mode A PWM output (Figure 13-4) has a time base (period)
and a time that the output stays high (duty cycle).
In Pulse Width Modulation (PWM) mode, the CCP1 pin The frequency of the PWM is the inverse of the
produces up to a 10-bit resolution PWM output. Since period (1/period).
the CCP1 pin is multiplexed with the PORTC data latch, FIGURE 13-4: PWM OUTPUT
the TRISC<2> bit must be cleared to make the CCP1
pin an output. Period
Note: Clearing the CCP1CON register will force Duty Cycle
the CCP1 PWM output latch to the default TMR2 = PR2
low level. This is not the PORTC I/O data
latch. TMR2 = Duty Cycle
TMR2 = PR2
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 13.5.3.
FIGURE 13-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Duty cycle registers CCP1CON<5:4>
CCPR1L
CCPR1H (Slave)
Comparator R Q
RC2/CCP1
TMR2 (Note 1)
S
Comparator TRISC<2>
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
DS39026B-page 114 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
13.5.1 PWM PERIOD 13.5.2 PWM DUTY CYCLE
The PWM period is specified by writing to the PR2 reg- The PWM duty cycle is specified by writing to the
ister. The PWM period can be calculated using the fol- CCPR1L register and to the CCP1CON<5:4> bits. Up
lowing formula: to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
PWM period = (PR2) + 1] 4 TOSC two LSbs. This 10-bit value is represented by
(TMR2 prescale value) CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM frequency is defined as 1 / [PWM period].
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)
When TMR2 is equal to PR2, the following three events TOSC (TMR2 prescale value)
occur on the next increment cycle:
CCPR1L and CCP1CON<5:4> can be written to at any
TMR2 is cleared time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
The CCP1 pin is set (exception: if PWM duty occurs (i.e., the period is complete). In PWM mode,
cycle = 0%, the CCP1 pin will not be set) CCPR1H is a read-only register.
The PWM duty cycle is latched from CCPR1L into The CCPR1H register and a 2-bit internal latch are
CCPR1H used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Note: The Timer2 postscaler (see Section 10.0)
is not used in the determination of the When the CCPR1H and 2-bit latch match TMR2 con-
PWM frequency. The postscaler could be catenated with an internal 2-bit Q clock or 2 bits of the
used to have a servo update rate at a dif- TMR2 prescaler, the CCP1 pin is cleared.
ferent frequency than the PWM output.
Maximum PWM resolution (bits) for a given PWM fre-
quency:
log F--F--P-O--W--S---MC---
= ----------------------------- bits
log ( 2 )
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 115
PIC18CXX2
13.5.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 13-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency 2.44 kHz 9.76 kHz 19.53 kHz 39.06 kHz 78.12 kHz 208.3 kHz
1
Timer Prescaler (1, 4, 16) 16 4 1 1 1
0x17
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 5.5
Maximum Resolution (bits) 10 10 10 8 7
TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
0000 000u
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
GIEH GIEL 0000 0000
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 1111 1111
0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
-000 0000
TMR2 Timer2 module's register 0000 0000 uuuu uuuu
uuuu uuuu
PR2 Timer2 module's period register 1111 1111 --00 0000
uuuu uuuu
T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu
--00 0000
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx
CCP1CON -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000
CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx
CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx
CCP2CON -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
Legend: x = unknown, u = unchanged, -- = unimplemented read as '0'.
Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026B-page 116 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
14.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
14.1 Master SSP (MSSP) Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
- Full Master Mode
- Slave mode (with general address call)
The I2C interface supports the following modes in hard-
ware:
Master mode
Multi-master mode
Slave mode
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14.2 Control Registers
The MSSP module has three associated registers.
These include a status register and two control regis-
ters.
Register 14-1: SSPSTAT: MSSP Status Register
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next start bit, stop bit, or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1 UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set
- n = Value at POR reset '0' = Bit is cleared x = Bit is unknown
DS39026B-page 118 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
Register 14-2: SSPCON1: MSSP Control Register1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSPM2 SSPM1 SSPM0
WCOL SSPOV SSPEN CKP SSPM3 bit 0
bit 7
bit 7 WCOL: Write Collision Detect bit
bit 6
Master Mode:
bit 5 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission
bit 4
bit 3 - 0 to be started
0 = No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode the user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not
set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be
cleared in software)
0 = No overflow
In I2C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care"
in transmit mode. (Must be cleared in software)
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1001 = Reserved
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set
- n = Value at POR reset '0' = Bit is cleared x = Bit is unknown
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Register 14-3: SSPCON2: MSSP Control Register2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (In I2C master mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (In I2C master mode only)
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (In I2C master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (In I2C master mode only)
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1 RSEN: Repeated Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0 SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit '1' = Bit is set '0' = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026B-page 120 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
14.2.1 SPI Mode FIGURE 14-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. All Internal
four modes of SPI are supported. To accomplish com- data bus
munication, typically three pins are used:
Read Write
Serial Data Out (SDO) - RC5/SDO
Serial Data In (SDI) - RC4/SDI/SDA SSPBUF reg
Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
SDI SSPSR reg shift
Additionally a fourth pin may be used when in a slave SDO bit0 clock
mode of operation:
SS Control
Slave Select (SS) - RA5/SS/AN4 Enable
14.2.1.1 OPERATION SS Edge
When initializing the SPI, several options need to be Select
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. 2
These control bits allow the following to be specified: Clock Select
Master Mode (SCK is the clock output) SSPM3:SSPM0
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK) SMP:CKE 4 ( ) TMR2 output
Data input sample phase (middle or end of data 2 2
output time) Edge
Clock edge (output data on rising/falling edge of
Select Prescaler TOSC
SCK)
Clock Rate (Master mode only) SCK 4, 16, 64
Slave Select Mode (Slave mode only)
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
Data to TX/RX in SSPSR
TRIS bit
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data (SSP-
BUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed suc-
cessfully.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 121
PIC18CXX2
When the application software is expecting to receive transmitter. Generally the MSSP Interrupt is used to
valid data, the SSPBUF should be read before the next determine when the transmission/reception has
byte of data to transfer is written to the SSPBUF. Buffer completed. The SSPBUF must be read and/or written.
full bit, BF (SSPSTAT<0>), indicates when SSPBUF If the interrupt method is not going to be used, then
has been loaded with the received data (transmission software polling can be done to ensure that a write
is complete). When the SSPBUF is read, the BF bit is collision does not occur. Example 14-1 shows the
cleared. This data may be irrelevant if the SPI is only a loading of the SSPBUF (SSPSR) for data transmission.
EXAMPLE 14-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
GOTO LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
The SSPSR is not directly readable or writable, and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT) indi-
cates the various status conditions.
14.2.1.2 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the SSP-
CON registers, and then set the SSPEN bit. This con-
figures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the TRIS
register) appropriately programmed. That is:
SDI is automatically controlled by the SPI module
SDO must have TRISC<5> bit cleared
SCK (Master mode) must have TRISC<3> bit
cleared
SCK (Slave mode) must have TRISC<3> bit set
SS must have TRISC<4> bit set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
14.2.1.3 TYPICAL CONNECTION
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
Master sends data -- Slave sends dummy data
Master sends data -- Slave sends data
Master sends dummy data -- Slave sends data
DS39026B-page 122 Preliminary 7/99 Microchip Technology Inc.
FIGURE 14-2: SPI MASTER/SLAVE CONNECTION PIC18CXX2
SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb
SDO SDI
Serial Input Buffer Serial Input Buffer
(SSPBUF) (SSPBUF)
Shift Register SDI SDO Shift Register
(SSPSR) Serial Clock (SSPSR)
MSb LSb SCK MSb LSb
SCK
PROCESSOR 1 PROCESSOR 2
7/99 Microchip Technology Inc. Preliminary DS39026B-page 123
PIC18CXX2
14.2.1.4 MASTER MODE Figure 14-3, Figure 14-5, and Figure 14-6 where the
MSB is transmitted first. In master mode, the SPI clock
The master can initiate the data transfer at any time rate (bit rate) is user programmable to be one of the fol-
because it controls the SCK. The master determines lowing:
when the slave (Processor 2, Figure 14-2) is to broad-
cast data by the software protocol. FOSC/4 (or TCY)
FOSC/16 (or 4 TCY)
In master mode the data is transmitted/received as FOSC/64 (or 16 TCY)
soon as the SSPBUF register is written to. If the SPI is Timer2 output/2
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register will This allows a maximum data rate (at 40 MHz) of 10.00
continue to shift in the signal present on the SDI pin at Mbps.
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal Figure 14-3 Shows the waveforms for master mode.
received byte (interrupts and status bits appropriately When the CKE bit is set, the SDO data is valid before
set). This could be useful in receiver applications as a there is a clock edge on SCK. The change of the input
"line activity monitor" mode. sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
The clock polarity is selected by appropriately program- data is shown.
ming the CKP bit (SSPCON1<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 14-3: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK 4 clock
(CKP = 1 modes
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKP = 1
CKE = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDO bit7 bit0
(CKE = 0)
bit7 bit0
SDO
(CKE = 1) Next Q4 cycle
after Q2
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39026B-page 124 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
14.2.1.5 SLAVE MODE the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
In slave mode, the data is transmitted and received as output. External pull-up/ pull-down resistors may be
the external clock pulses appear on SCK. When the desirable, depending on the application.
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave Mode with SS pin
While in slave mode the external clock is supplied by control enabled, (SSPCON<3:0> = 0100)
the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is
clock must meet the minimum high and low times as set to VDD.
specified in the electrical specifications.
Note 2: If the SPI is used in Slave Mode with CKE
While in sleep mode, the slave can transmit/receive set, then the SS pin control must be
data. When a byte is receive the device will wake-up enabled.
from sleep.
When the SPI module resets, the bit counter is forced
14.2.1.6 SLAVE SELECT SYNCHRONIZATION to 0. This can be done by either by forcing the SS pin to
a high level or clearing the SSPEN bit.
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control To emulate two-wire communication, the SDO pin can
enabled (SSPCON1<3:0> = 04h). The pin must not be connected to the SDI pin. When the SPI needs to
be driven low for the SS pin to function as an input. operate as a receiver the SDO pin can be configured as
The Data Latch must be high. When the SS pin is an input. This disables transmissions from the SDO.
low, transmission and reception are enabled and The SDI can always be left as an input (SDI function)
the SDO pin is driven. When the SS pin goes high, since it cannot create a bus conflict.
FIGURE 14-4: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO bit7 bit6 bit7 bit0
SDI bit7 bit0
(SMP = 0) bit7
Input Next Q4 cycle
Sample after Q2
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
7/99 Microchip Technology Inc. Preliminary DS39026B-page 125
PIC18CXX2
FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF Next Q4 cycle
Interrupt after Q2
Flag
SSPSR to
SSPBUF
FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit0
SDI bit7
(SMP = 0) Next Q4 cycle
after Q2
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39026B-page 126 Preliminary 7/99 Microchip Technology Inc.
PIC18CXX2
14.2.1.7 SLEEP OPERATION
In master mode all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
14.2.1.8 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
14.2.1.9 BUS MODE COMPATIBILITY
Table 14-1 shows the compatibility between the stan-
dard SPI modes and the states the the CKP and CKE
control bits.
TABLE 14-1: SPI BUS MODES
Standard SPI Mode Control Bits State
Terminology
CKP CKE
0, 0
0, 1 0 1
1, 0 0 0
1, 1 1 1
1 0
There is also a SMP bit which controls when the data is
sampled.
7/99 Microchip Technology Inc. Preliminary DS39026B-page 127
PIC18CXX2
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, all other
BOR resets
INTCON GIE/ PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
GIEH GIEL
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA -- PORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
14.3 MSSP I2C Operation FIGURE 14-7: MSSP BLOCK DIAGRAM
(I2C MODE)
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup- Read Internal
port) and provides interrupts on start and stop bits in Data Bus
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard Write
mode specifications, as well as 7-bit and 10-bit
addressing. RC3/SCK/SCL SSPBUF reg
Two pins are used for data transfer. These are the RC3/ Shift
SCK/SCL pin, which is the clock (SCL), and the RC4/ Clock
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the SSPSR reg
TRISC<4:3> bits.
RC4/ MSb LSb
The MSSP module functions are enabled by setting SDI/
MSSP Enable bit SSPEN (SSPCON<5>).
SDA
Match detect Addr Match
SSPADD reg
Start and Set, Reset
Stop bit detect S, P bits
(SSPSTAT reg)
The MSSP module has six registers for I2C operation.
These are the:
MSSP Control Register1 (SSPCON1)
MSSP Control Register2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) - Not directly
accessible
MSSP Address Register (SSPADD)
DS39026B-page 128 Preliminary 7/99 Microchip Technology Inc.
The SSPCON1 register allows control of the I2C oper- PIC18CXX2
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected: SSPBUF register.
I2C Master mode, clock = OSC/4 (SSPADD +1) b) The buffer full bit BF is set.
I2C Slave mode (7-bit address) c) An ACK pulse is generated.
I2C Slave mode (10-bit address) d) MSSP interrupt flag bit SSPIF (PIR1<3>) is set
I2C Slave mode (7-bit address), with start and
(interrupt is generated if enabled) on the falling
stop bit interrupts enabled edge of the ninth SCL pulse.
I2C Slave mode (10-bit address), with start and
In 10-bit address mode, two address bytes need to be
stop bit interrupts enabled received by the slave. The five Most Significant bits
I2C Firmware controlled master operation, slave (MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
is idle so the slave device will receive the second address
Selection of any I2C mode, with the SSPEN bit set, byte. For a 10-bit address, the first byte would equal
forces the SCL and SDA pins to be open drain, pro- `1111 0 A9 A8 0', where A9 and A8 are the two MSbs
vided these pins are programmed to inputs by setting of the address. The sequence of events for 10-bit
the appropriate TRISC bits. address is as follows with steps 7- 9 for slave-transmit-
ter:
14.3.1 SLAVE MODE
1. Receive first (high) byte of Address (bits SSPIF,
In slave mode, the SCL and SDA pins must be config- BF and bit UA (SSPSTAT<1>) are set).
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when 2. Update the SSPADD register with second (low)
required (slave-transmitter). byte of Address (clears bit UA and releases the
SCL line).
When an address is matched or the data transfer after
an address match is received, the hardware automati- 3. Read the SSPBUF register (clears bit BF) and
cally will generate the acknowledge (ACK) pulse and clear flag bit SSPIF.
load the SSPBUF register with the received value cur-
rently in the SSPSR register. 4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either 5. Update the SSPADD register with the first (high)
(or both): byte of Address. If match releases SCL line, this
will clear bit UA.
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received. 6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received. 7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The and BF are set).
BF bit is cleared by reading the SSPBUF register, while 9. Read the SSPBUF register (clears bit BF) and
bit SSPOV is cleared through software.
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, is shown in timing parameter #100 and
parameter #101.
14.3.1.1 ADDRESSING
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
7/99 Microchip Technology Inc. Preliminary DS39026B-page 129
PIC18CXX2
14.3.1.2 RECEPTION Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
When the R/W bit of the address byte is clear and an SCL pin prior to asserting another clock pulse. The
address match occurs, the R/W bit of the SSPSTAT slave devices may be holding off the master by stretch-
register is cleared. The received address is loaded into ing the clock. The eight data bits are shifted out on the
the SSPBUF register. falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 14-9).
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con- An MSSP interrupt is generated for each data transfer
dition is defined as either bit BF (SSPSTAT<0>) is set byte. The SSPIF bit must be cleared in software and
or bit SSPOV (SSPCON<6>) is set. the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
An MSSP interrupt is generated for each data transfer the ninth clock pulse.
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the As a slave-transmitter, the ACK pulse from the mas-
status of the byte. ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line is high (not ACK),
14.3.1.3 TRANSMISSION then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
When the R/W bit of the incoming address byte is set SSPSTAT register) and the slave monitors for
and an address match occurs, the R/W bit of the another occurrence of the START bit. If the SDA line
SSPSTAT register is set. The received address is was low (ACK), the transmit data must be loaded into
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