M PIC16F8X
18-pin Flash/EEPROM 8-Bit Microcontrollers
Devices Included in this Data Sheet: Pin Diagrams
PDIP, SOIC
PIC16F83
PIC16F84 RA2 1 18 RA1
PIC16CR83 RA0
PIC16CR84 RA3 2 17 OSC1/CLKIN
Extended voltage range devices available OSC2/CLKOUT
RA4/T0CKI 3 PIC16F8X 16 VDD
(PIC16LF8X, PIC16LCR8X) PIC16CR8X RB7
MCLR 4 15 RB6
RB5
High Performance RISC CPU Features: VSS 5 14 RB4
RB0/INT 6 13
Only 35 single word instructions to learn RB1 7 12
All instructions single cycle except for program RB2 8 11
branches which are two-cycle
RB3 9 10
Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Program Data Data Max. Special Microcontroller Features:
Memory
Device (words) RAM EEPROM Freq In-Circuit Serial Programming (ICSPTM) - via two
pins (ROM devices support only Data EEPROM
(bytes) (bytes) (MHz) programming)
PIC16F83 512 Flash 36 64 10 Power-on Reset (POR)
PIC16F84 1 K Flash Power-up Timer (PWRT)
PIC16CR83 512 ROM 68 64 10 Oscillator Start-up Timer (OST)
PIC16CR84 1 K ROM Watchdog Timer (WDT) with its own on-chip RC
36 64 10
oscillator for reliable operation
68 64 10 Code-protection
Power saving SLEEP mode
14-bit wide instructions Selectable oscillator options
8-bit wide data path
15 special function hardware registers CMOS Flash/EEPROM Technology:
Eight-level deep hardware stack
Direct, indirect and relative addressing modes Low-power, high-speed technology
Four interrupt sources: Fully static design
Wide operating voltage range:
- External RB0/INT pin
- TMR0 timer overflow - Commercial: 2.0V to 6.0V
- PORTB interrupt on change - Industrial: 2.0V to 6.0V
- Data EEPROM write complete Low power consumption:
1000 erase/write cycles Flash program memory - < 2 mA typical @ 5V, 4 MHz
10,000,000 erase/write cycles EEPROM data mem- - 15 A typical @ 2V, 32 kHz
ory - < 1 A typical standby current @ 2V
EEPROM Data Retention > 40 years
Peripheral Features:
13 I/O pins with individual direction control
High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
1998 Microchip Technology Inc. DS30430C-page 1
PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: What's New In This Data Sheet................................................................................................................................. 114
Appendix D: What's Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30430C-page 2 1998 Microchip Technology Inc.
1.0 GENERAL DESCRIPTION PIC16F8X
The PIC16F8X is a group in the PIC16CXX family of Table 1-1 lists the features of the PIC16F8X. A simpli-
low-cost, high-performance, CMOS, fully-static, 8-bit fied block diagram of the PIC16F8X is shown in
microcontrollers. This group contains the following Figure 3-1.
devices:
The PIC16F8X fits perfectly in applications ranging
PIC16F83 from high speed automotive and appliance motor
PIC16F84 control to low-power remote sensors, electronic locks,
security devices and smart cards. The Flash/EEPROM
PIC16CR83 technology makes customization of application
programs (transmitter codes, motor speeds, receiver
PIC16CR84 frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
All PICmicroTM microcontrollers employ an advanced microcontroller series perfect for all applications with
RISC architecture. PIC16F8X devices have enhanced space limitations. Low-cost, low-power, high
core features, eight-level deep stack, and multiple performance, ease-of-use and I/O flexibility make the
internal and external interrupt sources. The separate PIC16F8X very versatile even in areas where no
instruction and data buses of the Harvard architecture microcontroller use has been considered before
allow a 14-bit wide instruction word with a separate (e.g., timer functions; serial communication; capture,
8-bit wide data bus. The two stage instruction pipeline compare and PWM functions; and co-processor
allows all instructions to execute in a single cycle, applications).
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction The serial in-system programming feature (via two
set) are available. Additionally, a large register set is pins) offers flexibility of customizing the product after
used to achieve a very high performance level. complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
PIC16F8X microcontrollers typically achieve a 2:1 code program the device with the current firmware before
compression and up to a 4:1 speed improvement (at 20 shipping.
MHz) over other 8-bit microcontrollers in their class.
1.1 Family and Upward Compatibility
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of
Data EEPROM memory, and 13 I/O pins. A timer/ Those users familiar with the PIC16C5X family of
counter is also available. microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
The PIC16CXX family has special features to reduce Appendix A for a detailed list of enhancements. Code
external components, thus reducing cost, enhancing written for PIC16C5X devices can be easily ported to
system reliability and reducing power consumption. PIC16F8X devices (Appendix B).
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP 1.2 Development Support
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals. The PIC16CXX family is supported by a full-featured
The SLEEP (power-down) mode offers power saving. macro assembler, a software simulator, an in-circuit
The user can wake the chip from sleep through several emulator, a low-cost development programmer and a
external and internal interrupts and resets. full-featured programmer. A "C" compiler and fuzzy
logic support tools are also available.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
1998 Microchip Technology Inc. DS30430C-page 3
PIC16F8X
TABLE 1-1 PIC16F8X FAMILY OF DEVICES
Clock Maximum Frequency PIC16F83 PIC16CR83 PIC16F84 PIC16CR84
of Operation (MHz) 10 10 10 10
Flash Program Memory 512 -- 1K --
-- -- -- --
EEPROM Program Memory -- 512 -- 1K
36 36 68 68
Memory ROM Program Memory 64 64 64 64
TMR0 TMR0 TMR0 TMR0
Data Memory (bytes) 4 4 4 4
13 13 13 13
Data EEPROM (bytes) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP,
Peripherals Timer Module(s) SOIC SOIC SOIC SOIC
Interrupt Sources
Features I/O Pins
Voltage Range (Volts)
Packages
All PICmicroTM Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-
bility. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30430C-page 4 1998 Microchip Technology Inc.
2.0 PIC16F8X DEVICE VARIETIES PIC16F8X
A variety of frequency ranges and packaging options 2.3 Serialized Quick-Turnaround-
are available. Depending on application and production Production (SQTPSM ) Devices
requirements the proper device option can be selected
using the information in this section. When placing Microchip offers the unique programming service
orders, please use the "PIC16F8X Product where a few user-defined locations in each device are
Identification System" at the back of this data sheet to programmed with different serial numbers. The serial
specify the correct part number. numbers may be random, pseudo-random
or sequential.
There are four device "types" as indicated in the device Serial programming allows each device to have a
number. unique number which can serve as an entry-code,
password or ID number.
1. F, as in PIC16F84. These devices have Flash For information on submitting a SQTP code, please
program memory and operate over the standard contact your Microchip Regional Sales Office.
voltage range.
2.4 ROM Devices
2. LF, as in PIC16LF84. These devices have Flash
program memory and operate over an extended Some of Microchip's devices have a corresponding
voltage range. device where the program memory is a ROM. These
devices give a cost savings over Microchip's traditional
3. CR, as in PIC16CR83. These devices have user programmed devices (EPROM, EEPROM).
ROM program memory and operate over the ROM devices (PIC16CR8X) do not allow serialization
standard voltage range. information in the program memory space. The user
may program this information into the Data EEPROM.
4. LCR, as in PIC16LCR84. These devices have For information on submitting a ROM code, please
ROM program memory and operate over an contact your Microchip Regional Sales Office.
extended voltage range.
When discussing memory maps and other architectural
features, the use of F and CR also implies the LF and
LCR versions.
2.1 Flash Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed in-
circuit, or by device programmers, such as Microchip's
PICSTART Plus or PRO MATE II programmers.
2.2 Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices have all Flash
locations and configuration options already pro-
grammed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available.
For information on submitting a QTP code, please
contact your Microchip Regional Sales Office.
1998 Microchip Technology Inc. DS30430C-page 5
PIC16F8X
NOTES:
DS30430C-page 6 1998 Microchip Technology Inc.
3.0 ARCHITECTURAL OVERVIEW PIC16F8X
The high performance of the PIC16CXX family can be PIC16CXX devices contain an 8-bit ALU and working
attributed to a number of architectural features register. The ALU is a general purpose arithmetic unit.
commonly found in RISC microprocessors. To begin It performs arithmetic and Boolean functions between
with, the PIC16CXX uses a Harvard architecture. This data in the working register and any register file.
architecture has the program and data accessed from
separate memories. So the device has a program The ALU is 8-bits wide and capable of addition,
memory bus and a data memory bus. This improves subtraction, shift and logical operations. Unless
bandwidth over traditional von Neumann architecture otherwise mentioned, arithmetic operations are two's
where program and data are fetched from the same complement in nature. In two-operand instructions,
memory (accesses over the same bus). Separating typically one operand is the working register
program and data memory further allows instructions (W register), and the other operand is a file register or
to be sized differently than the 8-bit wide data word. an immediate constant. In single operand instructions,
PIC16CXX opcodes are 14-bits wide, enabling single the operand is either the W register or a file register.
word instructions. The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A two- The W register is an 8-bit working register used for ALU
stage pipeline overlaps fetch and execution of instruc- operations. It is not an addressable register.
tions (Example 3-1). Consequently, all instructions exe-
cute in a single cycle except for program branches. Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
The PIC16F83 and PIC16CR83 address 512 x 14 of Zero (Z) bits in the STATUS register. The C and DC bits
program memory, and the PIC16F84 and PIC16CR84 operate as a borrow and digit borrow out bit,
address 1K x 14 program memory. All program mem- respectively, in subtraction. See the SUBLW and SUBWF
ory is internal. instructions for examples.
The PIC16CXX can directly or indirectly address its A simplified block diagram for the PIC16F8X is shown
register files or data memory. All special function in Figure 3-1, its corresponding pin description is
registers including the program counter are mapped in shown in Table 3-1.
the data memory. An orthogonal (symmetrical)
instruction set makes it possible to carry out any oper-
ation on any register using any addressing mode. This
symmetrical nature and lack of `special optimal
situations' make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
1998 Microchip Technology Inc. DS30430C-page 7
PIC16F8X
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
Flash/ROM 13 Data Bus 8 EEPROM Data Memory
Program Program Counter
Memory RAM EEDATA EEPROM
8 Level Stack File Registers Data Memory
PIC16F83/CR83 (13-bit) PIC16F83/CR83
512 x 14 64 x 8
36 x 8
PIC16F84/CR84 PIC16F84/CR84 EEADR
1K x 14 RA4/T0CKI
68 x 8
Program 7 RAM Addr
Bus 14
Addr Mux
Instruction reg
7 Indirect
5 Direct Addr Addr TMR0
FSR reg
STATUS reg
8
Power-up MUX 8 I/O Ports
Timer ALU
Instruction W reg RA3:RA0
Decode & Oscillator RB7:RB1
Start-up Timer RB0/INT
Control
Power-on
Timing Reset
Generation
Watchdog
Timer
OSC2/CLKOUT MCLR VDD, VSS
OSC1/CLKIN
DS30430C-page 8 1998 Microchip Technology Inc.
PIC16F8X
TABLE 3-1 PIC16F8X PINOUT DESCRIPTION
Pin Name DIP SOIC I/O/P Buffer Description
No. No. Type Type
OSC1/CLKIN 16 16 I ST/CMOS (3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT
15 15 O -- Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an
RA0 active low reset to the device.
RA1
RA2 PORTA is a bi-directional I/O port.
RA3
17 17 I/O TTL
18 18 I/O TTL
1 1 I/O TTL
2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0
timer/counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT 6 6 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt pin.
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.
RB7 13 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.
VSS 5 5 P -- Ground reference for logic and I/O pins.
VDD 14 14 P -- Positive supply for logic and I/O pins.
Legend: I= input O = output I/O = Input/Output P = power
Note 1: -- = Not used TTL = TTL input ST = Schmitt Trigger input
2:
3: This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1998 Microchip Technology Inc. DS30430C-page 9
PIC16F8X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature An "Instruction Cycle" consists of four Q cycles (Q1,
clocks namely Q1, Q2, Q3 and Q4. Internally, the Q2, Q3 and Q4). The instruction fetch and execute are
program counter (PC) is incremented every Q1, the pipelined such that fetch takes one instruction cycle
instruction is fetched from the program memory and while decode and execute takes another instruction
latched into the instruction register in Q4. The cycle. However, due to the pipelining, each instruction
instruction is decoded and executed during the effectively executes in one cycle. If an instruction
following Q1 through Q4. The clocks and instruction causes the program counter to change (e.g., GOTO)
execution flow is shown in Figure 3-2. then two cycles are required to complete the instruction
(Example 3-1).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the "Instruction Register" in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 PC+1 PC+2
Q1 Fetch INST (PC+1) Fetch INST (PC+2)
Execute INST (PC) Execute INST (PC+1)
Q2 Internal
phase
Q3 clock
Q4
PC PC
OSC2/CLKOUT Fetch INST (PC)
(RC mode) Execute INST (PC-1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2
3. CALL SUB_1 Execute 2
4. BSF PORTA, BIT3 Fetch 3 Execute 3
Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
DS30430C-page 10 1998 Microchip Technology Inc.
PIC16F8X
4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK -
There are two memory blocks in the PIC16F8X. These PIC16F83/CR83
are the program memory and the data memory. Each
block has its own bus, so that access to each block can PC
occur during the same oscillator cycle.
CALL, RETURN 13
The data memory can further be broken down into the
general purpose RAM and the Special Function RETFIE, RETLW
Registers (SFRs). The operation of the SFRs that
control the "core" are described here. The SFRs used Stack Level 1
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data Stack Level 8
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is, Reset Vector 0000h
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of User Memory Peripheral Interrupt Vector 0004h
data EEPROM memory have the address range Space
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0. 1FFh
4.1 Program Memory Organization 1FFFh
The PIC16FXX has a 13-bit program counter capable FIGURE 4-2: PROGRAM MEMORY MAP
of addressing an 8K x 14 program memory space. For AND STACK -
the PIC16F83 and PIC16CR83, the first 512 x 14 PIC16F84/CR84
(0000h-01FFh) are physically implemented
(Figure 4-1). For the PIC16F84 and PIC16CR84, the PC
first 1K x 14 (0000h-03FFh) are physically imple-
mented (Figure 4-2). Accessing a location above the CALL, RETURN 13
physically implemented address will cause a wrap-
around. For example, for the PIC16F84 locations 20h, RETFIE, RETLW
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction. Stack Level 1
The reset vector is at 0000h and the interrupt vector is
at 0004h.
Stack Level 8
Reset Vector 0000h
Peripheral Interrupt Vector 0004h
User Memory
Space
1998 Microchip Technology Inc. 3FFh
1FFFh
DS30430C-page 11
PIC16F8X 4.2.1 GENERAL PURPOSE REGISTER FILE
4.2 Data Memory Organization All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
The data memory is partitioned into two areas. The first accessed either directly or indirectly through the FSR
is the Special Function Registers (SFR) area, while the (Section 4.5).
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device. The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing loca-
Portions of data memory are banked. This is for both tion 0Ch or 8Ch will access the same GPR.
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general 4.2.2 SPECIAL FUNCTION REGISTERS
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking The Special Function Registers (Figure 4-1, Figure 4-2
requires the use of control bits for bank selection. and Table 4-1) are used by the CPU and Peripheral
These control bits are located in the STATUS Register. functions to control the device operation. These
Figure 4-1 and Figure 4-2 show the data memory map registers are static RAM.
organization.
The special function registers can be classified into two
Instructions MOVWF and MOVF can move values from the sets, core and peripheral. Those associated with the
W register to any location in the register file ("F"), and core functions are described in this section. Those
vice-versa. related to the operation of the peripheral features are
described in the section for that specific feature.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
DS30430C-page 12 1998 Microchip Technology Inc.
PIC16F8X
FIGURE 4-1: REGISTER FILE MAP - FIGURE 4-2: REGISTER FILE MAP -
PIC16F83/CR83 PIC16F84/CR84
File Address File Address File Address File Address
00h Indirect addr.(1) Indirect addr.(1) 80h 00h Indirect addr.(1) Indirect addr.(1) 80h
01h TMR0 OPTION 81h 01h TMR0 OPTION 81h
02h PCL PCL 82h 02h PCL PCL 82h
03h STATUS STATUS 83h 03h STATUS STATUS 83h
04h FSR FSR 84h 04h FSR FSR 84h
05h PORTA TRISA 85h 05h PORTA TRISA 85h
06h PORTB TRISB 86h 06h PORTB TRISB 86h
07h 87h 07h 87h
08h EEDATA EECON1 88h 08h EEDATA EECON1 88h
09h EEADR EECON2(1) 89h 09h EEADR EECON2(1) 89h
0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh
0Ch 8Ch 0Ch 8Ch
36 Mapped 68
General (accesses) General
Purpose in Bank 0 Purpose
registers registers
(SRAM) (SRAM) Mapped
(accesses)
2Fh AFh in Bank 0
30h B0h
4Fh CFh
50h D0h
7Fh FFh 7Fh FFh
Bank 0 Bank 1 Bank 0 Bank 1
Unimplemented data memory location; read as '0'. Unimplemented data memory location; read as '0'.
Note 1: Not a physical register. Note 1: Not a physical register.
1998 Microchip Technology Inc. DS30430C-page 13
PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset (Note3)
Bank 0 INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
00h TMR0 xxxx xxxx uuuu uuuu
01h PCL 8-bit real-time clock/counter 0000 0000 0000 0000
02h STATUS (2) 0001 1xxx 000q quuu
FSR Low order 8 bits of the Program Counter (PC) xxxx xxxx uuuu uuuu
03h PORTA ---x xxxx ---u uuuu
04h PORTB IRP RP1 RP0 TO PD Z DC C xxxx xxxx uuuu uuuu
05h RA0 ---- ---- ---- ----
06h EEDATA Indirect data memory address pointer 0 RB0/INT xxxx xxxx uuuu uuuu
07h EEADR xxxx xxxx uuuu uuuu
08h -- -- -- RA4/T0CKI RA3 RA2 RA1 RBIF ---0 0000 ---0 0000
09h 0000 000x 0000 000u
RB7 RB6 RB5 RB4 RB3 RB2 RB1
Unimplemented location, read as '0'
EEPROM data register
EEPROM address register
0Ah PCLATH -- -- -- Write buffer for upper 5 bits of the PC (1)
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF
Bank 1
80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000
83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
85h TRISA -- -- -- PORTA data direction register ---1 1111 ---1 1111
86h TRISB PORTB data direction register 1111 1111 1111 1111
87h Unimplemented location, read as '0' ---- ---- ---- ----
88h EECON1 -- -- -- EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0Ah PCLATH -- -- -- Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never trans-
2: ferred to PCLATH.
3: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14 1998 Microchip Technology Inc.
PIC16F8X
4.2.2.1 STATUS REGISTER Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
The STATUS register contains the arithmetic status of because these instructions do not affect any status bit.
the ALU, the RESET status and the bank select bit for
data memory. Note 1: The IRP and RP1 bits (STATUS) are
not used by the PIC16F8X and should be
As with any register, the STATUS register can be the programmed as cleared. Use of these bits
destination for any instruction. If the STATUS register is as general purpose R/W bits is NOT
the destination for an instruction that affects the Z, DC recommended, since this may affect
or C bits, then the write to these three bits is disabled. upward compatibility with future products.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable. Note 2: The C and DC bits operate as a borrow
Therefore, the result of an instruction with the STATUS and digit borrow out bit, respectively, in
register as destination may be different than intended. subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register Note 3: When the STATUS register is the
as 000u u1uu (where u = unchanged). destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP
RP1 RP0 TO PD Z DC C R = Readable bit
bit7
bit0 W = Writable bit
bit 7: U = Unimplemented bit,
read as `0'
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.
1998 Microchip Technology Inc. DS30430C-page 15
PIC16F8X
4.2.2.2 OPTION_REG REGISTER Note: When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
The OPTION_REG register is a readable and writable prescaler assignment.
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R = Readable bit
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit
bit7 U = Unimplemented bit,
bit0
bit 7: read as `0'
- n = Value at POR reset
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
DS30430C-page 16 1998 Microchip Technology Inc.
PIC16F8X
4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
The INTCON register is a readable and writable its corresponding enable bit or the global
register which contains the various enable bits for all enable bit, GIE (INTCON).
interrupt sources.
FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R = Readable bit
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF W = Writable bit
U = Unimplemented bit,
bit7 bit0
read as `0'
- n = Value at POR reset
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1: INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1998 Microchip Technology Inc. DS30430C-page 17
PIC16F8X
4.3 Program Counter: PCL and PCLATH manipulation of the PCLATH is not required for
the return instructions (which "pops" the PC from the
The Program Counter (PC) is 13-bits wide. The low stack).
byte is the PCL register, which is a readable and
writable register. The high byte of the PC (PC) is Note: The PIC16F8X ignores the PCLATH
not directly readable nor writable and comes from the bits, which are used for program memory
PCLATH register. The PCLATH (PC latch high) register pages 1, 2 and 3 (0800h - 1FFFh). The
is a holding register for PC. The contents of use of PCLATH as general purpose
PCLATH are transferred to the upper byte of the R/W bits is not recommended since this
program counter when the PC is loaded with a new may affect upward compatibility with
value. This occurs during a CALL, GOTO or a write to future products.
PCL. The high bits of PC are loaded from PCLATH as
shown in Figure 4-1. 4.4 Stack
FIGURE 4-1: LOADING OF PC IN The PIC16FXX has an 8 deep x 13-bit wide hardware
DIFFERENT SITUATIONS stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
PCH PCL readable or writable.
12 87 0 The entire 13-bit PC is "pushed" onto the stack when a
INST with PCL CALL instruction is executed or an interrupt is acknowl-
PC as dest edged. The stack is "popped" in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
PCLATH 8 not affected by a push or a pop operation.
5 ALU result
PCLATH
Note: There are no instruction mnemonics
called push or pop. These are actions that
PCH PCL occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
12 11 10 8 7 0 tions, or the vectoring to an interrupt
address.
PC PCLATH GOTO, CALL
2
11
Opcode
PCLATH The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push over-
4.3.1 COMPUTED GOTO writes the value that was stored from the first push. The
tenth push overwrites the second push (and so on).
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a table If the stack is effectively popped nine times, the PC
read using a computed GOTO method, care should be value is the same as the value from the first pop.
exercised if the table location crosses a PCL memory
boundary (each 256 word block). Refer to the application Note: There are no status bits to indicate stack
note "Implementing a Table Read" (AN556). overflow or stack underflow conditions.
4.3.2 PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of pro-
gram memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instruc-
tions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLATH bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH) are programmed to
the desired program memory page. If a CALL instruc-
tion (or interrupt) is executed, the entire 13-bit PC is
"pushed" onto the stack (see next section). Therefore,
DS30430C-page 18 1998 Microchip Technology Inc.
PIC16F8X
4.5 Indirect Addressing; INDF and FSR A simple program to clear RAM locations 20h-2Fh
Registers using indirect addressing is shown in Example 4-2.
The INDF register is not a physical register. Address- EXAMPLE 4-2: HOW TO CLEAR RAM
ing INDF actually addresses the register whose USING INDIRECT
address is contained in the FSR register (FSR is a movlw ADDRESSING
pointer). This is indirect addressing. movwf
clrf 0x20 ;initialize pointer
EXAMPLE 4-1: INDIRECT ADDRESSING NEXT incf FSR ; to RAM
Register file 05 contains the value 10h CONTINUE btfss INDF ;clear INDF register
Register file 06 contains the value 0Ah goto FSR ;inc pointer
Load the value 05 into the FSR register FSR,4 ;all done?
A read of the INDF register will return the value of : NEXT ;NO, clear next
10h ;YES, continue
Increment the value of the FSR register by one
An effective 9-bit address is obtained by concatenating
(FSR = 06) the 8-bit FSR register and the IRP bit (STATUS), as
A read of the INDF register now will return the shown in Figure 4-1. However, IRP is not used in the
PIC16F8X.
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
RP1 RP0 6 from opcode 0 IRP 7 (FSR) 0
bank select location select bank select location select
00 01 10 11
00h 00h
not used not used
0Bh
0Ch
Data 2Fh (1) Addresses
Memory (3) 30h (1) map back
to Bank 0
4Fh (2)
50h (2)
7Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: PIC16F83 and PIC16CR83 devices.
2: PIC16F84 and PIC16CR84 devices
3: For memory map detail see Figure 4-1.
1998 Microchip Technology Inc. DS30430C-page 19
PIC16F8X
NOTES:
DS30430C-page 20 1998 Microchip Technology Inc.
PIC16F8X
5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA
The PIC16F8X has two ports, PORTA and PORTB. CLRF PORTA ; Initialize PORTA by
Some port pins are multiplexed with an alternate func-
tion for other features on the device. ; setting output
5.1 PORTA and TRISA Registers ; data latches
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger BSF STATUS, RP0 ; Select Bank 1
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All MOVLW 0x0F ; Value used to
pins have data direction bits (TRIS registers) which can
configure these pins as output or input. ; initialize data
Setting a TRISA bit (=1) will make the corresponding ; direction
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit MOVWF TRISA ; Set RA as inputs
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected ; RA4 as outputs
pin.
; TRISA are always
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write ; read as '0'.
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
value is modified and written to the port data latch.
Data DQ
The RA4 pin is multiplexed with the TMR0 clock input. bus CK Q
Data Latch
WR
PORT
N RA4 pin
VSS
WR DQ
TRIS CK Q
TRIS Latch
Schmitt
FIGURE 5-1: BLOCK DIAGRAM OF PINS Trigger
RA3:RA0 input
Data buffer
bus Q
VDD RD TRIS
D
Q Q D
WR P
Port EENN
CK
RD PORT
Data Latch
N I/O pin TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
D Q
WR VSS
TRIS CK Q
TRIS Latch TTL
input
buffer
RD TRIS
Q D
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc. DS30430C-page 21
PIC16F8X
TABLE 5-1 PORTA FUNCTIONS
Name Bit0 Buffer Type Function
RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
05h PORTA -- -- -- RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA -- -- -- TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30430C-page 22 1998 Microchip Technology Inc.
PIC16F8X
5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
PORTB is an 8-bit wide bi-directional port. The interrupt in the following manner:
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding a) Read (or write) PORTB. This will end the mis-
output driver in a hi-impedance mode. A '0' on any bit match condition.
in the TRISB register puts the contents of the output
latch on the selected pin(s). b) Clear flag bit RBIF.
Each of the PORTB pins have a weak internal pull-up. A mismatch condition will continue to set the RBIF bit.
A single control bit can turn on all the pull-ups. This is Reading PORTB will end the mismatch condition, and
done by clearing the RBPU (OPTION_REG) bit. allow the RBIF bit to be cleared.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are This interrupt on mismatch feature, together with
disabled on a Power-on Reset. software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
Four of PORTB's pins, RB7:RB4, have an interrupt on wake-up on key-depression (see AN552 in the
change feature. Only pins configured as inputs can Embedded Control Handbook).
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt Note 1: For a change on the I/O pin to be
on change comparison). The pins value in input mode recognized, the pulse width must be at
are compared with the old value latched on the last least TCY (4/fOSC) wide.
read of PORTB. The "mismatch" outputs of the pins are
OR'ed together to generate the RB port The interrupt on change feature is recommended for
change interrupt. wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
FIGURE 5-3: BLOCK DIAGRAM OF PINS feature. Polling of PORTB is not recommended while
RB7:RB4 using the interrupt on change feature.
FIGURE 5-4: BLOCK DIAGRAM OF PINS
RB3:RB0
RBPU(1)
Data bus VDD
WR Port
VDD P weak
WR TRIS pull-up
RBPU(1) weak
Data bus P pull-up Data Latch
WR Port DQ
Data Latch I/O I/O
WR TRIS DQ pin(2) CK pin(2)
CK TRIS Latch TTL
TRIS Latch DQ Input
Buffer
DQ CK
CK TTL
Input
Buffer
RD TRIS Latch RD TRIS QD
RD Port QD RD Port EN
EN
Set RBIF RB0/INT
From other Schmitt Trigger RD Port
RB7:RB4 pins Buffer
QD
EN Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1998 Microchip Technology Inc. DS30430C-page 23
PIC16F8X
EXAMPLE 5-1: INITIALIZING PORTB
CLRF PORTB ; Initialize PORTB by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB as inputs
; RB as outputs
; RB as inputs
TABLE 5-3 PORTB FUNCTIONS
Name Bit Buffer Type I/O Consistency Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT
TRISB4 TRISB1 TRISB0 Reset uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB3 TRISB2 1111 1111
xxxx xxxx 1111 1111
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
REG
1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30430C-page 24 1998 Microchip Technology Inc.
PIC16F8X
5.3 I/O Programming Considerations 5.3.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
5.3.1 BI-DIRECTIONAL I/O PORTS
The actual write to an I/O port happens at the end of an
Any instruction which writes, operates internally as a instruction cycle, whereas for reading, the data must be
read followed by a write operation. The BCF and BSF valid at the beginning of the instruction cycle
instructions, for example, read the register into the (Figure 5-5). Therefore, care must be exercised if a
CPU, execute the bit operation and write the result back write followed by a read operation is carried out on the
to the register. Caution must be used when these same I/O port. The sequence of instructions should be
instructions are applied to a port with both inputs and such that the pin voltage stabilizes (load dependent)
outputs defined. For example, a BSF operation on bit5 before the next instruction which causes that file to be
of PORTB will cause all eight bits of PORTB to be read read into the CPU is executed. Otherwise, the previous
into the CPU. Then the BSF operation takes place on state of that pin may be read into the CPU rather than
bit5 and PORTB is written to the output latches. If the new state. When in doubt, it is better to separate
another bit of PORTB is used as a bi-directional I/O pin these instructions with a NOP or another instruction not
(i.e., bit0) and it is defined as an input at this time, the accessing this I/O port.
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular Example 5-1 shows the effect of two sequential
pin, overwriting the previous content. As long as the pin read-modify-write instructions (e.g., BCF, BSF, etc.) on
stays in the input mode, no problem occurs. However, an I/O port.
if bit0 is switched into output mode later on, the content
of the data latch is unknown. EXAMPLE 5-1: READ-MODIFY-WRITE
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the INSTRUCTIONS ON AN
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port pins I/O PORT
is read, the desired operation is done to this value, and
this value is then written to the port latch. ;Initial PORT settings: PORTB Inputs
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order ; PORTB Outputs
to change the level on this pin ("wired-or", "wired-and").
The resulting high output current may damage the chip. ;PORTB have external pull-ups and are
FIGURE 5-5: SUCCESSIVE I/O OPERATION ;not connected to other circuitry
;
; PORT latch PORT pins
; ---------- ---------
BCF PORTB, 7 ; 01pp ppp 11pp ppp
BCF PORTB, 6 ; 10pp ppp 11pp ppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp ppp 11pp ppp
BCF TRISB, 6 ; 10pp ppp 10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction NOP NOP followed by a read from PORTB.
MOVWF PORTB MOVF PORTB,W
fetched write to Note that:
PORTB
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
Instruction Port pin NOP TPD = propagation delay
executed sampled here
TPD Therefore, at higher clock frequencies,
a write followed by a read may be
MOVWF PORTB MOVF PORTB,W problematic.
write to
PORTB
1998 Microchip Technology Inc. DS30430C-page 25
PIC16F8X
NOTES:
DS30430C-page 26 1998 Microchip Technology Inc.
PIC16F8X
6.0 TIMER0 MODULE AND TMR0 edge select bit, T0SE (OPTION_REG). Clearing bit
REGISTER T0SE selects the rising edge. Restrictions on the exter-
nal clock input are discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following
features: The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
8-bit timer/counter controlled, in software, by control bit PSA
Readable and writable (OPTION_REG). Clearing bit PSA will assign the
8-bit software programmable prescaler prescaler to the Timer0 Module. The prescaler is not
Internal or external clock select readable or writable. When the prescaler (Section 6.3)
Interrupt on overflow from FFh to 00h is assigned to the Timer0 Module, the prescale value
Edge select for external clock (1:2, 1:4, ..., 1:256) is software selectable.
Timer mode is selected by clearing the T0CS bit 6.1 TMR0 Interrupt
(OPTION_REG). In timer mode, the Timer0 mod-
ule (Figure 6-1) will increment every instruction cycle The TMR0 interrupt is generated when the TMR0
(without prescaler). If the TMR0 register is written, the register overflows from FFh to 00h. This overflow sets
increment is inhibited for the following two cycles the T0IF bit (INTCON). The interrupt can be
(Figure 6-2 and Figure 6-3). The user can work around masked by clearing enable bit T0IE (INTCON). The
this by writing an adjusted value to the TMR0 register. T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
Counter mode is selected by setting the T0CS bit interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
(OPTION_REG). In this mode TMR0 will increment the processor from SLEEP since the timer is shut off
either on every rising or falling edge of pin RA4/T0CKI. during SLEEP.
The incrementing edge is determined by the T0 source
FIGURE 6-1: TMR0 BLOCK DIAGRAM
Data bus
FOSC/4 0 Programmable PSout Sync with 8
1 Prescaler 1 Internal
RA4/T0CKI clocks TMR0 register
pin T0CS 3 0 PSout
T0SE PS2, PS1, PS0
(2 cycle delay)
PSA Set bit T0IF
on Overflow
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0
TMR0
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
Instruction executed reads NT0 reads NT0 reads NT0
Executed reads NT0 + 1 reads NT0 + 2
1998 Microchip Technology Inc. DS30430C-page 27
PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction
Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
TMR0 T0 T0+1 NT0 NT0+1
Instruction Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
Execute executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 6-4: TMR0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
TMR0 timer FEh FFh 00h 01h 02h
T0IF bit 4 1 1
(INTCON)
GIE bit
(INTCON)
INSTRUCTION FLOW Interrupt Latency(2)
PC +1
PC PC PC +1 0004h 0005h
Inst (PC+1) Dummy cycle Inst (0004h) Inst (0005h)
Instruction Inst (PC) Inst (PC) Dummy cycle Inst (0004h)
fetched
Instruction Inst (PC-1)
executed
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30430C-page 28 1998 Microchip Technology Inc.
6.2 Using TMR0 with External Clock PIC16F8X
When an external clock input is used for TMR0, it must 6.2.2 TMR0 INCREMENT DELAY
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC) Since the prescaler output is synchronized with the
synchronization. Also, there is a delay in the actual internal clocks, there is a small delay from the time the
incrementing of the TMR0 register after external clock edge occurs to the time the Timer0
synchronization. Module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION incrementing.
When no prescaler is used, the external clock input is 6.3 Prescaler
the same as the prescaler output. The synchronization
of pin RA4/T0CKI with the internal phase clocks is An 8-bit counter is available as a prescaler for the
accomplished by sampling the prescaler output on the Timer0 Module, or as a postscaler for the Watchdog
Q2 and Q4 cycles of the internal phase clocks Timer (Figure 6-6). For simplicity, this counter is being
(Figure 6-5). Therefore, it is necessary for T0CKI to be referred to as "prescaler" throughout this data sheet.
high for at least 2Tosc (plus a small RC delay) and low Note that there is only one prescaler available which is
for at least 2Tosc (plus a small RC delay). Refer to the mutually exclusive between the Timer0 Module and the
electrical specification of the desired device. Watchdog Timer. Thus, a prescaler assignment for the
Timer0 Module means that there is no prescaler for the
When a prescaler is used, the external clock input is Watchdog Timer, and vice-versa.
divided by an asynchronous ripple counter type
prescaler so that the prescaler output is symmetrical. The PSA and PS2:PS0 bits (OPTION_REG)
For the external clock to meet the sampling determine the prescaler assignment and prescale ratio.
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a When assigned to the Timer0 Module, all instructions
period of at least 4Tosc (plus a small RC delay) divided writing to the Timer0 Module (e.g., CLRF 1, MOVWF 1,
by the prescaler value. The only requirement on T0CKI BSF 1,x ....etc.) will clear the prescaler. When
high and low time is that they do not violate the assigned to WDT, a CLRWDT instruction will clear the
minimum pulse width requirement of 10 ns. Refer to prescaler along with the Watchdog Timer. The
parameters 40, 41 and 42 in the AC Electrical prescaler is not readable or writable.
Specifications of the desired device.
1998 Microchip Technology Inc. DS30430C-page 29
PIC16F8X
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Ext. Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler Out (Note 2) (Note 3)
Ext. Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4) T0 T0 + 1 T0 + 2
TMR0
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER Data Bus
8
CLKOUT (= Fosc/4)
TMR0 register
RA4/T0CKI 0M 1 SYNC
pin U M 2 Set bit T0IF
X on overflow
0 U Cycles
1 X
T0SE T0CS
PSA
Watchdog 0 8-bit Prescaler PS2:PS0
Timer M 8
U
WDT Enable bit 8 - to - 1MUX
1X
PSA
0 1
MUX PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.
DS30430C-page 30 1998 Microchip Technology Inc.
PIC16F8X
6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: CHANGING PRESCALER
The prescaler assignment is fully under software (TIMER0WDT)
control (i.e., it can be changed "on the fly" during
program execution). BCF STATUS, RP0 ;Bank 0
CLRF TMR0 ;Clear TMR0
; and Prescaler
Note: To avoid an unintended device RESET, the BSF STATUS, RP0 ;Bank 1
following instruction sequence CLRWDT ;Clears WDT
(Example 6-1) must be executed when MOVLW b'xxxx1xxx' ;Select new
changing the prescaler assignment from MOVWF OPTION_REG ; prescale value
BCF STATUS, RP0 ;Bank 0
Timer0 to the WDT. This sequence must
be taken even if the WDT is disabled. To EXAMPLE 6-2: CHANGING PRESCALER
change prescaler from the WDT to the (WDTTIMER0)
Timer0 module use the sequence shown in CLRWDT ;Clear WDT and
Example 6-2. ; prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW b'xxxx0xxx' ;Select TMR0, new
; prescale value
' and clock source
MOVWF OPTION_REG ;
BCF STATUS, RP0 ;Bank 0
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 0000
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
85h TRISA -- -- -- TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
1998 Microchip Technology Inc. DS30430C-page 31
PIC16F8X
NOTES:
DS30430C-page 32 1998 Microchip Technology Inc.
PIC16F8X
7.0 DATA EEPROM MEMORY data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
The EEPROM data memory is readable and writable time will vary with voltage and temperature as well as
during normal operation (full VDD range). This memory from chip to chip. Please refer to AC specifications for
is not directly mapped in the register file space. Instead exact limits.
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write When the device is code protected, the CPU may
this memory. These registers are: continue to read and write the data EEPROM memory.
The device programmer can no longer access
EECON1 this memory.
EECON2
EEDATA 7.1 EEADR
EEADR
The EEADR register can address up to a maximum of
EEDATA holds the 8-bit data for read/write, and EEADR 256 bytes of data EEPROM. Only the first 64 bytes of
holds the address of the EEPROM location being data EEPROM are implemented.
accessed. PIC16F8X devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh. The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
The EEPROM data memory allows byte read and write. address is in the 64 byte memory space.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)
U U U R/W-0 R/W-x R/W-0 R/S-0 R/S-x
--
bit7 -- -- EEIF WRERR WREN WR RD R = Readable bit
bit 7:5 bit0 W = Writable bit
bit 4 S = Settable bit
bit 3
U = Unimplemented bit,
bit 2
bit 1 read as `0'
bit 0 - n = Value at POR reset
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
1998 Microchip Technology Inc. DS30430C-page 33
PIC16F8X
7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits To write an EEPROM data location, the user must first
physically implemented. The upper-three bits are non- write the address to the EEADR register and the data
existent and read as '0's. to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in EXAMPLE 7-1: DATA EEPROM WRITE
software. They are cleared in hardware at completion of
the read or write operation. The inability to clear the WR BSF STATUS, RP0 ; Bank 1
bit in software prevents the accidental, premature ter- BCF
mination of a write operation. BSF INTCON, GIE ; Disable INTs.
MOVLW
The WREN bit, when set, will allow a write operation. MOVWF EECON1, WREN ; Enable Write
On power-up, the WREN bit is clear. The WRERR bit is MOVLW
set when a write operation is interrupted by a MCLR MOVWF 55h ;
reset or a WDT time-out reset during normal operation. BSF
In these situations, following reset, the user can check EECON2 ; Write 55h
the WRERR bit and rewrite the location. The data and BSF
address will be unchanged in the EEDATA and Required AAh ;
EEADR registers. Sequence
EECON2 ; Write AAh
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software. EECON1,WR ; Set WR bit
EECON2 is not a physical register. Reading EECON2 ; begin write
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence. INTCON, GIE ; Enable INTs.
7.3 Reading the EEPROM Data Memory The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
To read a data memory location, the user must write EECON2, then set WR bit) for each byte. We strongly
the address to the EEADR register and then set control recommend that interrupts be disabled during this
bit RD (EECON1). The data is available, in the very code segment.
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value Additionally, the WREN bit in EECON1 must be set to
until another read or until it is written to by the user enable write. This mechanism prevents accidental
(during a write operation). writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
EXAMPLE 7-1: DATA EEPROM READ At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
BCF STATUS, RP0 ; Bank 0 Interrupt Flag bit (EEIF) is set. The user can either
MOVLW CONFIG_ADDR ; enable this interrupt or poll this bit. EEIF must be
MOVWF EEADR ; Address to read cleared by software.
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
MOVF EEDATA, W ; W = EEDATA
DS30430C-page 34 1998 Microchip Technology Inc.
PIC16F8X
7.5 Write Verify GOTO WRITE_ERR ; NO, Write error
: ; YES, Good write
Depending on the application, good programming : ; Continue program
practice may dictate that the value written to the Data
EEPROM should be verified (Example 7-1) to the 7.6 Protection Against Spurious Writes
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed There are conditions when the device may not want to
near the specification limit. The Total Endurance disk write to the data EEPROM memory. To protect against
will help determine your comfort level. spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Generally the EEPROM write failure will be a bit which Power-up Timer (72 ms duration) prevents
was written as a '1', but reads back as a '0' (due to EEPROM write.
leakage off the bit).
The write initiate sequence and the WREN bit together
EXAMPLE 7-1: WRITE VERIFY help prevent an accidental write during brown-out,
power glitch, or software malfunction.
BCF STATUS, RP0 ; Bank 0 7.7 Data EEPROM Operation during Code
Protect
: ; Any code can go here
When the device is code protected, the CPU is able to
: ; read and write unscrambled data to the Data
EEPROM.
MOVF EEDATA, W ; Must be in Bank 0
For ROM devices, there are two code protection bits
BSF STATUS, RP0 ; Bank 1 (Section 8.1). One for the ROM program memory and
one for the Data EEPROM memory.
READ
BSF EECON1, RD ; YES, Read the
; value written
BCF STATUS, RP0 ; Bank 0
;
; Is the value written (in W reg) and
; read (in EEDATA) the same?
;
SUBWF EEDATA, W ;
BTFSS STATUS, Z ; Is difference 0?
TABLE 7-1 REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
88h EECON1 -- -- -- EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
1998 Microchip Technology Inc. DS30430C-page 35
PIC16F8X
NOTES:
DS30430C-page 36 1998 Microchip Technology Inc.
8.0 SPECIAL FEATURES OF THE PIC16F8X
CPU
8.1 Configuration Bits
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of The configuration bits can be programmed (read as '0')
real time applications. The PIC16F8X has a host of or left unprogrammed (read as '1') to select various
such features intended to maximize system reliability, device configurations. These bits are mapped in
minimize cost through elimination of external program memory location 2007h.
components, provide power saving operating modes Address 2007h is beyond the user program memory
and offer code protection. These features are: space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
OSC Selection be accessed during programming.
To find out how to program the PIC16C84, refer to
Reset PIC16C84 EEPROM Memory Programming Specifica-
tion (DS30189).
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-circuit serial programming
The PIC16F8X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
1998 Microchip Technology Inc. DS30430C-page 37
PIC16F8X
FIGURE 8-1: CONFIGURATION WORD - PIC16CR83 AND PIC16CR84
R-u R-u R-u R-u R-u R-u R/P-u R-u R-u R-u R-u R-u R-u R-u
CP CP CP CP CP CP DP CP CP
bit13 CP PWRTE WDTE FOSC1 FOSC0
bit0
R = Readable bit
P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 13:8 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 7 DP: Data Memory Code Protection bit
1 = Code protection off
0 = Data memory is code protected
bit 6:4 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
FIGURE 8-2: CONFIGURATION WORD - PIC16F83 AND PIC16F84
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP CP CP CP CP CP CP CP CP CP PWRTE
WDTE FOSC1 FOSC0
bit13
bit0
bit 13:4 CP: Code Protection bit
1 = Code protection off R = Readable bit
0 = All memory is code protected P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
DS30430C-page 38 1998 Microchip Technology Inc.
PIC16F8X
8.2 Oscillator Configurations TABLE 8-1 CAPACITOR SELECTION
FOR CERAMIC RESONATORS
8.2.1 OSCILLATOR TYPES
The PIC16F8X can be operated in four different Ranges Tested:
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of Mode Freq OSC1/C1 OSC2/C2
these four modes:
XT 455 kHz 47 - 100 pF 47 - 100 pF
2.0 MHz 15 - 33 pF 15 - 33 pF
LP Low Power Crystal 4.0 MHz 15 - 33 pF 15 - 33 pF
XT Crystal/Resonator
HS High Speed Crystal/Resonator HS 8.0 MHz 15 - 33 pF 15 - 33 pF
RC Resistor/Capacitor
10.0 MHz 15 - 33 pF 15 - 33 pF
Note : Recommended values of C1 and C2 are identical to
the ranges tested table.
8.2.2 CRYSTAL OSCILLATOR / CERAMIC Higher capacitance increases the stability of the
RESONATORS oscillator but also increases the start-up time.
These values are for design guidance only. Since
In XT, LP or HS modes a crystal or ceramic resonator each resonator has its own characteristics, the user
is connected to the OSC1/CLKIN and OSC2/CLKOUT should consult the resonator manufacturer for the
pins to establish oscillation (Figure 8-3). appropriate values of external components.
Resonators Tested:
FIGURE 8-3: CRYSTAL/CERAMIC 455 kHz Panasonic EFO-A455K04B 0.3%
RESONATOR OPERATION 2.0 MHz Murata Erie CSA2.00MG 0.5%
(HS, XT OR LP OSC 4.0 MHz Murata Erie CSA4.00MG 0.5%
CONFIGURATION) 8.0 MHz Murata Erie CSA8.00MT 0.5%
10.0 MHz Murata Erie CSA10.00MTZ 0.5%
C1(1) OSC1
None of the resonators had built-in capacitors.
To
XTAL RF(3) internal TABLE 8-2 CAPACITOR SELECTION
logic FOR CRYSTAL OSCILLATOR
OSC2 SLEEP
RS(2) PIC16FXX Mode Freq OSC1/C1 OSC2/C2
C2(1)
LP 32 kHz 68 - 100 pF 68 - 100 pF
Note1: See Table 8-1 for recommended values of 200 kHz 15 - 33 pF 15 - 33 pF
2: C1 and C2.
3: A series resistor (RS) may be required for XT 100 kHz 100 - 150 pF 100 - 150 pF
AT strip cut crystals.
RF varies with the crystal chosen. 2 MHz 15 - 33 pF 15 - 33 pF
4 MHz 15 - 33 pF 15 - 33 pF
HS 4 MHz 15 - 33 pF 15 - 33 pF
10 MHz 15 - 33 pF 15 - 33 pF
The PIC16F8X oscillator design requires the use of a Note : Higher capacitance increases the stability of
parallel cut crystal. Use of a series cut crystal may give oscillator but also increases the start-up time.
a frequency out of the crystal manufacturers These values are for design guidance only. Rs may
specifications. When in XT, LP or HS modes, the device be required in HS mode as well as XT mode to
can have an external clock source to drive the avoid overdriving crystals with low drive level spec-
OSC1/CLKIN pin (Figure 8-4). ification. Since each crystal has its own characteris-
tics, the user should consult the crystal
FIGURE 8-4: EXTERNAL CLOCK INPUT manufacturer for appropriate values of external
OPERATION (HS, XT OR LP components.
OSC CONFIGURATION)
For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz
Clock from OSC1 200 kHz Epson C-2 100.00 KC-P 20 PPM
ext. system PIC16FXX 1.0 MHz
2.0 MHz STD XTL 200.000 KHz 20 PPM
Open OSC2 4.0 MHz
10.0 MHz ECS ECS-10-13-2 50 PPM
ECS ECS-20-S-2 50 PPM
ECS ECS-40-S-4 50 PPM
ECS ECS-100-S-4 50 PPM
1998 Microchip Technology Inc. DS30430C-page 39
PIC16F8X
8.2.3 EXTERNAL CRYSTAL OSCILLATOR 8.2.4 RC OSCILLATOR
CIRCUIT
For timing insensitive applications the RC device option
Either a prepackaged oscillator can be used or a simple offers additional cost savings. The RC oscillator
oscillator circuit with TTL gates can be built. frequency is a function of the supply voltage, the
Prepackaged oscillators provide a wide operating resistor (Rext) values, capacitor (Cext) values, and the
range and better stability. A well-designed crystal operating temperature. In addition to this, the oscillator
oscillator will provide good performance with TTL frequency will vary from unit to unit due to normal
gates. Two types of crystal oscillator circuits are process parameter variation. Furthermore, the
available; one with series resonance, and one with difference in lead frame capacitance between package
parallel resonance. types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into
Figure 8-5 shows a parallel resonant oscillator circuit. account variation due to tolerance of the external
The circuit is designed to use the fundamental R and C components. Figure 8-7 shows how an R/C
frequency of the crystal. The 74AS04 inverter performs combination is connected to the PIC16F8X. For Rext
the 180-degree phase shift that a parallel oscillator values below 4 k, the oscillator operation may
requires. The 4.7 k resistor provides negative become unstable, or stop completely. For very high
feedback for stability. The 10 k potentiometer biases Rext values (e.g., 1 M), the oscillator becomes
the 74AS04 in the linear region. This could be used for sensitive to noise, humidity and leakage. Thus, we
external oscillator designs. recommend keeping Rext between 5 k and 100 k.
FIGURE 8-5: EXTERNAL PARALLEL Although the oscillator will operate with no external
RESONANT CRYSTAL capacitor (Cext = 0 pF), we recommend using values
OSCILLATOR CIRCUIT above 20 pF for noise and stability reasons. With little
or no external capacitance, the oscillation frequency
+5V To Other PIC16FXX can vary dramatically due to changes in external
Devices capacitances, such as PCB trace capacitance or
10k package lead frame capacitance.
4.7k 74AS04
See the electrical specification section for RC
74AS04 CLKIN frequency variation from part to part due to normal
process variation. The variation is larger for larger R
10k (since leakage current variation will affect RC
XTAL frequency more for large R) and for smaller C (since
10k variation of input capacitance has a greater affect on
RC frequency).
20 pF 20 pF
See the electrical specification section for variation of
Figure 8-6 shows a series resonant oscillator circuit. oscillator frequency due to VDD for given Rext/Cext
This circuit is also designed to use the fundamental values as well as frequency variation due to
frequency of the crystal. The inverter performs a operating temperature.
180-degree phase shift. The 330 k resistors provide
the negative feedback to bias the inverters in their The oscillator frequency, divided by 4, is available on
linear region. the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).
FIGURE 8-7: RC OSCILLATOR MODE
VDD
FIGURE 8-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT Rext
OSC1 Internal
clock
To Other Cext PIC16FXX
Devices
330 k 330 k VSS
74AS04 74AS04 PIC16FXX OSC2/CLKOUT
74AS04
Fosc/4
CLKIN
Recommended values: 5 k Rext 100 k
0.1 F Cext > 20pF
XTAL
Note: When the device oscillator is in RC mode,
do not drive the OSC1 pin with an external
clock or you may damage the device.
DS30430C-page 40 1998 Microchip Technology Inc.
PIC16F8X
8.3 Reset Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
The PIC16F8X differentiates between various kinds in any other reset. Most other registers are reset to a
of reset: "reset state" on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
Power-on Reset (POR) They are not affected by a WDT reset during SLEEP,
MCLR reset during normal operation since this reset is viewed as the resumption of normal
MCLR reset during SLEEP operation.
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP) Table 8-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Figure 8-8 shows a simplified block diagram of the Table 8-4 gives a full description of reset states for all
on-chip reset circuit. The MCLR reset path has a noise registers.
filter to ignore small pulses. The electrical specifica-
tions state the pulse width requirements for the MCLR The TO and PD bits are set or cleared differently in dif-
pin. ferent reset situations (Section 8.7). These bits are
used in software to determine the nature of the reset.
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR SLEEP S
VDD WDT WDT
Module Time_Out
Chip_Reset
Reset
VDD rise
detect Power_on_Reset
OST/PWRT
OST
10-bit Ripple counter R Q
OSC1/
CLKIN
PWRT
On-chip 10-bit Ripple counter
RC OSC(1)
Note 1: This is a separate oscillator from the Enable PWRT See Table 8-5
RC oscillator of the CLKIN pin. Enable OST
1998 Microchip Technology Inc. DS30430C-page 41
PIC16F8X
TABLE 8-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter STATUS Register
Power-on Reset 000h 0001 1xxx
MCLR Reset during normal operation 000h 000u uuuu
MCLR Reset during SLEEP 000h 0001 0uuu
WDT Reset (during normal operation) 000h 0000 1uuu
WDT Wake-up PC + 1 uuu0 0uuu
Interrupt wake-up from SLEEP PC + 1 (1) uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4 RESET CONDITIONS FOR ALL REGISTERS
Register Address Power-on Reset MCLR Reset during: Wake-up from SLEEP:
normal operation through interrupt
SLEEP through WDT Time-out
WDT Reset during nor-
mal operation
W -- xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h ---- ---- ---- ---- ---- ----
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h PC + 1(2)
STATUS 02h 0000h 000q quuu(3)
uuuq quuu(3)
03h 0001 1xxx
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---x xxxx ---u uuuu ---u uuuu
PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu
EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000u uuuu uuuu(1)
0Bh 0000 000x
INDF 80h ---- ---- ---- ---- ---- ----
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
PCL 82h 0000h 0000h PC + 1
STATUS 000q quuu(3) uuuq quuu(3)
83h 0001 1xxx
FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
EECON1 88h ---0 x000 ---0 q000 ---0 uuuu
EECON2 89h ---- ---- ---- ---- ---- ----
PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000u uuuu uuuu(1)
8Bh 0000 000x
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0',
q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.
DS30430C-page 42 1998 Microchip Technology Inc.
PIC16F8X
8.4 Power-on Reset (POR) FIGURE 8-9: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
A Power-on Reset pulse is generated on-chip when VDD POWER-UP)
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin VDD VDD
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create D R
Power-on Reset. A minimum rise time for VDD must be
met for this to operate properly. See Electrical Specifi- C R1
cations for details. MCLR
When the device starts normal operation (exits the PIC16FXX
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure Note 1: External Power-on Reset circuit is required
operation. If these conditions are not met, the device only if VDD power-up rate is too slow. The
must be held in reset until the operating conditions diode D helps discharge the capacitor
are met. quickly when VDD powers down.
For additional information, refer to Application Note 2: R < 40 k is recommended to make sure
AN607, "Power-up Trouble Shooting." that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
The POR circuit does not produce an internal reset pin is 5 A). A larger voltage drop will
when VDD declines. degrade VIH level on the MCLR pin.
8.5 Power-up Timer (PWRT) 3: R1 = 100 to 1 k will limit any current
flowing into MCLR from external
The Power-up Timer (PWRT) provides a fixed 72 ms capacitor C in the event of an MCLR pin
nominal time-out (TPWRT) from POR (Figure 8-10, breakdown due to ESD or EOS.
Figure 8-11, Figure 8-12 and Figure 8-13). The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT delay allows the VDD to rise to an accept-
able level (Possible exception shown in Figure 8-13).
A configuration bit, PWRTE, can enable/disable the
PWRT. See either Figure 8-1 or Figure 8-2 for the oper-
ation of the PWRTE bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-10, Figure 8-11,
Figure 8-12 and Figure 8-13). This ensures the crystal
oscillator or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 8-13), an external power-on reset circuit may
be necessary (Figure 8-9).
1998 Microchip Technology Inc. DS30430C-page 43
PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR TPWRT
INTERNAL POR
TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
DS30430C-page 44 1998 Microchip Technology Inc.
PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
1998 Microchip Technology Inc. DS30430C-page 45
PIC16F8X
8.7 Time-out Sequence and Power-down 8.8 Reset on Brown-Out
Status Bits (TO/PD)
A brown-out is a condition where device power (VDD)
On power-up (Figure 8-10, Figure 8-11, Figure 8-12 dips below its minimum value, but not to zero, and then
and Figure 8-13) the time-out sequence is as follows: recovers. The device should be reset in the event of a
First PWRT time-out is invoked after a POR has brown-out.
expired. Then the OST is activated. The total time-out
will vary based on oscillator configuration and PWRTE To reset a PIC16F8X device when a brown-out occurs,
configuration bit status. For example, in RC mode with external brown-out protection circuits may be built, as
the PWRT disabled, there will be no time-out at all. shown in Figure 8-14 and Figure 8-15.
TABLE 8-5 TIME-OUT IN VARIOUS FIGURE 8-14: BROWN-OUT PROTECTION
SITUATIONS CIRCUIT 1
Oscillator Power-up Wake-up VDD
Configuration from 33k
PWRT PWRT VDD
XT, HS, LP Enabled Disabled SLEEP
1024TOSC
RC 72 ms + 1024TOSC 10k MCLR
1024TOSC --
72 ms --
Since the time-outs occur from the POR reset pulse, if 40k PIC16F8X
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin This circuit will activate reset when VDD goes below
immediately (Figure 8-10). This is useful for testing (Vz + 0.7V) where Vz = Zener voltage.
purposes or to synchronize more than one PIC16F8X
device when operating in parallel. FIGURE 8-15: BROWN-OUT PROTECTION
CIRCUIT 2
Table 8-6 shows the significance of the TO and PD bits.
Table 8-3 lists the reset conditions for some special VDD
registers, while Table 8-4 lists the reset conditions for
all the registers. VDD
R1
TABLE 8-6 STATUS BITS AND THEIR
SIGNIFICANCE
TO PD Condition
1 1 Power-on Reset Q1
MCLR
0 x Illegal, TO is set on POR
R2
40k PIC16F8X
x 0 Illegal, PD is set on POR
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up
1 1 MCLR Reset during normal operation This brown-out circuit is less expensive, although less
accurate. Transistor Q1 turns off when VDD is below a
1 0 MCLR Reset during SLEEP or interrupt certain level such that:
wake-up from SLEEP
VDD R1 = 0.7V
R1 + R2
DS30430C-page 46 1998 Microchip Technology Inc.
8.9 Interrupts PIC16F8X
The PIC16F8X has 4 sources of interrupt: The RB0/INT pin interrupt, the RB port change inter-
External interrupt RB0/INT pin rupt and the TMR0 overflow interrupt flags are con-
TMR0 overflow interrupt tained in the INTCON register.
PORTB change interrupts (pins RB7:RB4) When an interrupt is responded to; the GIE bit is
Data EEPROM write complete interrupt cleared to disable any further interrupt, the return
The interrupt control register (INTCON) records address is pushed onto the stack and the PC is loaded
individual interrupt requests in flag bits. It also contains with 0004h. For external interrupt events, such as the
the individual and global interrupt enable bits. RB0/INT pin or PORTB change interrupt, the interrupt
The global interrupt enable bit, GIE (INTCON) latency will be three to four instruction cycles. The exact
enables (if set) all un-masked interrupts or disables (if latency depends when the interrupt event occurs
cleared) all interrupts. Individual interrupts can be (Figure 8-17). The latency is the same for both one and
disabled through their corresponding enable bits in two cycle instructions. Once in the interrupt service
INTCON register. Bit GIE is cleared on reset. routine the source(s) of the interrupt can be determined
The "return from interrupt" instruction, RETFIE, exits by polling the interrupt flag bits. The interrupt flag bit(s)
interrupt routine as well as sets the GIE bit, which must be cleared in software before re-enabling
re-enable interrupts. interrupts to avoid infinite interrupt requests.
FIGURE 8-16: INTERRUPT LOGIC Note 1: Individual interrupt flag bits are set
regardless of the status of their
T0IF corresponding mask bit or the GIE bit.
T0IE
INTF Wake-up
INTE (If in SLEEP mode)
RBIF Interrupt to CPU
RBIE
EEIF
EEIE
GIE
1998 Microchip Technology Inc. DS30430C-page 47
PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT 3
4
INT pin 1
Interrupt Latency 2
INTF flag 1 5
(INTCON)
GIE bit
(INTCON)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Inst (PC+1) -- Inst (0004h) Inst (0005h)
Instruction Inst (PC) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h)
fetched
Instruction Inst (PC-1)
executed
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
8.9.1 INT INTERRUPT 8.9.3 PORT RB INTERRUPT
External interrupt on RB0/INT pin is edge triggered: An input change on PORTB sets flag bit RBIF
either rising if INTEDG bit (OPTION_REG) is set, (INTCON). The interrupt can be enabled/disabled
or falling, if INTEDG bit is clear. When a valid edge by setting/clearing enable bit RBIE (INTCON)
appears on the RB0/INT pin, the INTF bit (Section 5.2).
(INTCON) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON). Flag bit INTF Note 1: For a change on the I/O pin to be
must be cleared in software via the interrupt service recognized, the pulse width must be at
routine before re-enabling this interrupt. The INT least TCY wide.
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2 TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON)
(Section 6.0).
DS30430C-page 48 1998 Microchip Technology Inc.
PIC16F8X
8.10 Context Saving During Interrupts Example 8-1 does the following:
During an interrupt, only the return PC value is saved a) Stores the W register.
on the stack. Typically, users wish to save key register b) Stores the STATUS register in STATUS_TEMP.
values during an interrupt (e.g., W register and STATUS c) Executes the Interrupt Service Routine code.
register). This is implemented in software. d) Restores the STATUS (and bank select bit)
Example 8-1 stores and restores the STATUS and W register.
register's values. The User defined registers, W_TEMP e) Restores the W register.
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
ISR SWAPF STATUS, W ; Swap status to be saved into W
POP MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
: :
: STATUS_TEMP, W ; Interrupt Service Routine
: STATUS ; should configure Bank as required
: W_TEMP, F ;
SWAPF W_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF ; Move W into STATUS register
; (sets bank to original state)
SWAPF ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF ; Swap nibbles in W_TEMP and place result into W
1998 Microchip Technology Inc. DS30430C-page 49
PIC16F8X
8.11 Watchdog Timer (WDT) part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
The Watchdog Timer is a free running on-chip RC can be assigned to the WDT under software control by
oscillator which does not require any external writing to the OPTION_REG register. Thus, time-out
components. This RC oscillator is separate from the periods up to 2.3 seconds can be realized.
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN The CLRWDT and SLEEP instructions clear the WDT and
and OSC2/CLKOUT pins of the device has been the postscaler (if assigned to the WDT) and prevent it
stopped, for example, by execution of a SLEEP from timing out and generating a device
instruction. During normal operation a WDT time-out RESET condition.
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up The TO bit in the STATUS register will be cleared upon
and continue with normal operation. The WDT can be a WDT time-out.
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1). 8.11.2 WDT PROGRAMMING CONSIDERATIONS
8.11.1 WDT PERIOD It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
The WDT has a nominal time-out period of 18 ms, (with WDT prescaler) it may take several seconds before a
no prescaler). The time-out periods vary with WDT time-out occurs.
temperature, VDD and process variations from part to
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M Postscaler
1U 8
WDT Timer X
8 - to -1 MUX
PS2:PS0
WDT PSA
Enable Bit
To TMR0 (Figure 6-6)
PSA
0 1
MUX
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset 1111 1111
2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
REG
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.
2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.
DS30430C-page 50 1998 Microchip Technology Inc.
PIC16F8X
8.12 Power-down Mode (SLEEP) 8.12.2 WAKE-UP FROM SLEEP
A device may be powered down (SLEEP) and later The device can wake-up from SLEEP through one of
powered up (Wake-up from SLEEP). the following events:
8.12.1 SLEEP 1. External reset input on MCLR pin.
The Power-down mode is entered by executing the 2. WDT Wake-up (if WDT was enabled).
SLEEP instruction.
3. Interrupt from RB0/INT pin, RB port change, or
If enabled, the Watchdog Timer is cleared (but keeps data EEPROM write complete.
running), the PD bit (STATUS) is cleared, the TO bit
(STATUS) is set, and the oscillator driver is turned Peripherals cannot generate interrupts during SLEEP,
off. The I/O ports maintain the status they had before since no on-chip Q clocks are present.
the SLEEP instruction was executed (driving high, low,
or hi-impedance). The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
For the lowest current consumption in SLEEP mode, program execution. The TO and PD bits can be used to
place all I/O pins at either at VDD or VSS, with no determine the cause of a device reset. The PD bit,
external circuitry drawing current from the I/O pins, and which is set on power-up, is cleared when SLEEP is
disable external clocks. I/O pins that are hi-impedance invoked. The TO bit is cleared if a WDT time-out
inputs should be pulled high or low externally to avoid occurred (and caused wake-up).
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS. The While the SLEEP instruction is being executed, the next
contribution from on-chip pull-ups on PORTB should be instruction (PC + 1) is pre-fetched. For the device to
considered. wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
The MCLR pin must be at a logic high level (VIHMC). occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
It should be noted that a RESET generated by a WDT the instruction after the SLEEP instruction. If the GIE bit
time-out does not drive the MCLR pin low. is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 TOST(2)
CLKOUT(4)
INT pin Interrupt Latency
(Note 2)
INTF flag
(INTCON) Processor in
SLEEP
GIE bit
(INTCON)
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Inst(PC + 1) Inst(PC + 2) Dummy cycle Inst(0004h) Inst(0005h)
Instruction Inst(PC) = SLEEP SLEEP Inst(PC + 1) Dummy cycle Inst(0004h)
fetched Inst(PC - 1)
Instruction
executed
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1998 Microchip Technology Inc. DS30430C-page 51
PIC16F8X 8.15 In-Circuit Serial Programming
8.12.3 WAKE-UP USING INTERRUPTS PIC16F8X microcontrollers can be serially
programmed while in the end application circuit. This is
When global interrupts are disabled (GIE cleared) and simply done with two lines for clock and data, and three
any interrupt source has both its interrupt enable bit other lines for power, ground, and the programming
and interrupt flag bit set, one of the following will occur: voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
If the interrupt occurs before the execution of a microcontroller just before shipping the product,
SLEEP instruction, the SLEEP instruction will com- allowing the most recent firmware or custom firmware
plete as a NOP. Therefore, the WDT and WDT to be programmed.
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared. The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
If the interrupt occurs during or after the execu- MCLR pin from VIL to VIHH (see programming
tion of a SLEEP instruction, the device will immedi- specification). RB6 becomes the programming clock
ately wake up from sleep. The SLEEP instruction and RB7 becomes the programming data. Both RB6
will be completely executed before the wake-up. and RB7 are Schmitt Trigger inputs in this mode.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will After reset, to place the device into programming/verify
be cleared. mode, the program counter (PC) points to location 00h.
A 6-bit command is then supplied to the device, 14-bits
Even if the flag bits were checked before executing a of program data is then supplied to or from the device,
SLEEP instruction, it may be possible for flag bits to using load or read-type instructions. For complete
become set before the SLEEP instruction completes. To details of serial programming, please refer to the
determine whether a SLEEP instruction executed, test PIC16CXX Programming Specifications (Literature
the PD bit. If the PD bit is set, the SLEEP instruction was #DS30189).
executed as a NOP.
FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL
To ensure that the WDT is cleared, a CLRWDT instruc- PROGRAMMING
tion should be executed before a SLEEP instruction. CONNECTION
8.13 Program Verification/Code Protection External To Normal
Connector Connections
If the code protection bit(s) have not been Signals
programmed, the on-chip program memory can be PIC16FXX
read out for verification purposes. +5V
0V VDD
Note: Microchip does not recommend code pro- VSS
tecting widowed devices. VPP MCLR/VPP
8.14 ID Locations CLK RB6
Four memory locations (2000h - 2003h) are designated Data I/O RB7
as ID locations to store checksum or other code
identification numbers. These locations are not VDD
accessible during normal execution but are readable To Normal
and writable only during program/verify. Only the Connections
4 least significant bits of ID location are usable.
For ROM devices, both the program memory and Data
For ROM devices, these values are submitted along EEPROM memory may be read, but only the Data
with the ROM code. EEPROM memory may be programmed.
DS30430C-page 52 1998 Microchip Technology Inc.
PIC16F8X
9.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
into three basic categories:
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type Byte-oriented operations
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction Bit-oriented operations
set summary in Table 9-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 9-1 Literal and control operations
shows the opcode field descriptions.
All instructions are executed within one single instruc-
For byte-oriented instructions, 'f' represents a file reg- tion cycle, unless a conditional test is true or the pro-
ister designator and 'd' represents a destination desig- gram counter is changed as a result of an instruction.
nator. The file register designator specifies which file In this case, the execution takes two instruction cycles
register is to be used by the instruction. with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
The destination designator specifies where the result of an oscillator frequency of 4 MHz, the normal instruction
the operation is to be placed. If 'd' is zero, the result is execution time is 1 s. If a conditional test is true or the
placed in the W register. If 'd' is one, the result is placed program counter is changed as a result of an instruc-
in the file register specified in the instruction. tion, the instruction execution time is 2 s.
For bit-oriented instructions, 'b' represents a bit field Table 9-2 lists the instructions recognized by the
designator which selects the number of the bit affected MPASM assembler.
by the operation, while 'f' represents the number of the
file in which the bit is located. Figure 9-1 shows the general formats that the instruc-
tions can have.
For literal and control operations, 'k' represents an Note: To maintain upward compatibility with
eight or eleven bit constant or literal value. future PIC16CXX products, do not use the
OPTION and TRIS instructions.
TABLE 9-1 OPCODE FIELD All examples use the following format to represent a
DESCRIPTIONS hexadecimal number:
Field Description 0xhh
where h signifies a hexadecimal digit.
f Register file address (0x00 to 0x7F)
W Working register (accumulator) FIGURE 9-1: GENERAL FORMAT FOR
INSTRUCTIONS
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don't care location (= 0 or 1) Byte-oriented file register operations
The assembler will generate code with x = 0. It is the 13 8 76 0
recommended form of use for compatibility with all OPCODE d f (FILE #)
Microchip software tools. d = 0 for destination W
d = 1 for destination f
d Destination select; d = 0: store result in W, f = 7-bit file register address
d = 1: store result in file register f.
Default is d = 1
label Label name Bit-oriented file register operations
TOS Top of Stack 13 10 9 7 6 0
PC Program Counter OPCODE b (BIT #) f (FILE #)
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit b = 3-bit bit address
f = 7-bit file register address
WDT Watchdog Timer/Counter
TO Time-out bit Literal and control operations
PD Power-down bit
dest Destination either the W register or the specified General 87 0
register file location 13 k (literal)
OPCODE
[] Options
() Contents
Assigned to k = 8-bit immediate value
Register bit field
In the set of CALL and GOTO instructions only
italics User defined term (font is courier) 13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
1998 Microchip Technology Inc. DS30430C-page 53
PIC16F8X
TABLE 9-2 PIC16FXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands
MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
AND W with f 1 00 0101 dfff ffff Z 1,2
ANDWF f, d 1 00 0001 lfff ffff Z 2
Clear f 1 00 0001 0xxx xxxx Z
CLRF f Clear W 1 00 1001 dfff ffff Z 1,2
Complement f 1 00 0011 dfff ffff Z 1,2
CLRW - Decrement f 1(2) 00 1011 dfff ffff 1,2,3
Decrement f, Skip if 0 1 00 1010 dfff ffff Z 1,2
COMF f, d Increment f 1(2) 00 1111 dfff ffff 1,2,3
Increment f, Skip if 0 1 00 0100 dfff ffff Z 1,2
DECF f, d Inclusive OR W with f 1 00 1000 dfff ffff Z 1,2
Move f 1 00 0000 lfff ffff
DECFSZ f, d Move W to f 1 00 0000 0xx0 0000 C 1,2
No Operation 1 00 1101 dfff ffff C 1,2
INCF f, d Rotate Left f through Carry 1 00 1100 dfff ffff C,DC,Z 1,2
Rotate Right f through Carry 1 00 0010 dfff ffff 1,2
INCFSZ f, d Subtract W from f 1 00 1110 dfff ffff Z 1,2
Swap nibbles in f 1 00 0110 dfff ffff
IORWF f, d Exclusive OR W with f
MOVF f, d
MOVWF f
NOP -
RLF f, d
RRF f, d
SUBWF f, d
SWAPF f, d
XORWF f, d
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
Bit Set f
BSF f, b Bit Test f, Skip if Clear 1 01 01bb bfff ffff 1,2
Bit Test f, Skip if Set
BTFSC f, b 1 (2) 01 10bb bfff ffff 3
BTFSS f, b 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
AND literal with W
ANDLW k 1 11 1001 kkkk kkkk Z
Call subroutine
CALL k Clear Watchdog Timer 2 10 0kkk kkkk kkkk
CLRWDT - Go to address 1 00 0000 0110 0100 TO,PD
Inclusive OR literal with W
GOTO k 2 10 1kkk kkkk kkkk
Move literal to W
IORLW k Return from interrupt 1 11 1000 kkkk kkkk Z
Return with literal in W
MOVLW k Return from Subroutine 1 11 00xx kkkk kkkk
Go into standby mode
RETFIE - Subtract W from literal 2 00 0000 0000 1001
Exclusive OR literal with W
RETLW k 2 11 01xx kkkk kkkk
RETURN - 2 00 0000 0000 1000
SLEEP - 1 00 0000 0110 0011 TO,PD
SUBLW k 1 11 110x kkkk kkkk C,DC,Z
XORLW k 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30430C-page 54 1998 Microchip Technology Inc.
PIC16F8X
9.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW AND Literal with W
Syntax: Syntax:
Operands: [label] ADDLW k Operands: [label] ANDLW k
Operation: Operation:
Status Affected: 0 k 255 Status Affected: 0 k 255
Encoding: Encoding: (W) .AND. (k) (W)
Description: (W) + k (W) Description:
Words: C, DC, Z Words: Z
Cycles: Cycles:
Q Cycle Activity: 11 111x kkkk kkkk Q Cycle Activity: 11 1001 kkkk kkkk
The contents of the W register are The contents of W register are
added to the eight bit literal 'k' and the AND'ed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
1 1
1 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
literal 'k' data W literal "k" data W
Example: ADDLW 0x15 Example ANDLW 0x5F
Before Instruction Before Instruction
W = 0x10 W = 0xA3
After Instruction After Instruction
W = 0x25 W = 0x03
ADDWF Add W and f ANDWF AND W with f
Syntax: Syntax:
Operands: [label] ADDWF f,d Operands: [label] ANDWF f,d
Operation: 0 f 127 Operation: 0 f 127
Status Affected: d [0,1] Status Affected: d [0,1]
Encoding: Encoding:
Description: (W) + (f) (destination) Description: (W) .AND. (f) (destination)
Words: C, DC, Z Words: Z
Cycles: Cycles:
Q Cycle Activity: 00 0111 dfff ffff Q Cycle Activity: 00 0101 dfff ffff
Add the contents of the W register with AND the W register with register 'f'. If 'd'
register 'f'. If 'd' is 0 the result is stored is 0 the result is stored in the W regis-
in the W register. If 'd' is 1 the result is ter. If 'd' is 1 the result is stored back in
stored back in register 'f'. register 'f'.
1 1
1 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register data destination register data destination
'f' 'f'
Example ADDWF FSR, 0 Example ANDWF FSR, 1
Before Instruction Before Instruction
W = 0x17 W = 0x17
FSR = 0xC2 FSR = 0xC2
After Instruction After Instruction
W = 0xD9 W = 0x17
FSR = 0xC2 FSR = 0x02
1998 Microchip Technology Inc. DS30430C-page 55
PIC16F8X
BCF Bit Clear f BTFSC Bit Test, Skip if Clear
Syntax: Syntax:
Operands: [label] BCF f,b Operands: [label] BTFSC f,b
Operation: 0 f 127 Operation: 0 f 127
Status Affected: 0b7 Status Affected: 0b7
Encoding: Encoding:
Description: 0 (f) Description: skip if (f) = 0
Words:
Cycles: None Words: None
Q Cycle Activity: Cycles:
01 00bb bfff ffff Q Cycle Activity: 01 10bb bfff ffff
Bit 'b' in register 'f' is cleared. If bit 'b' in register 'f' is '1' then the next
instruction is executed.
1 If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
1 executed instead, making this a 2TCY
instruction.
Q1 Q2 Q3 Q4
Decode Read Process Write 1
register data register 'f'
'f' 1(2)
Example BCF FLAG_REG, 7 Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No-Operat
FLAG_REG = 0xC7
register 'f' data ion
After Instruction
FLAG_REG = 0x47 If Skip: (2nd Cycle)
Q1 Q2 Q3 Q4
No-Operati No-Opera No-Operat
No-Operat on tion ion
ion
Example HERE BTFSC FLAG,1
FALSE PROCESS_CODE
TRUE GOTO
BSF Bit Set f Before Instruction
Syntax: PC = address HERE
Operands: [label] BSF f,b
After Instruction
Operation: 0 f 127 if FLAG = 0,
Status Affected: 0b7 PC = address TRUE
Encoding: if FLAG=1,
Description: PC = address FALSE
Words:
Cycles: 1 (f)
Q Cycle Activity:
None
01 01bb bfff ffff
Bit 'b' in register 'f' is set.
1
1
Q1 Q2 Q3 Q4
Decode Read Process Write
register data register 'f'
'f'
Example BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430C-page 56 1998 Microchip Technology Inc.
PIC16F8X
BTFSS Bit Test f, Skip if Set CALL Call Subroutine
Syntax:
Operands: [label] BTFSS f,b Syntax: [ label ] CALL k
Operation: 0 f 127 Operands: 0 k 2047
Status Affected: 0b
京公网安备 11010802033920号
Copyright © 2005-2021 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
