M PIC16F84A
18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
Devices Included in this Data Sheet: Pin Diagrams
PDIP, SOIC
PIC16F84A
Extended voltage range device available RA2 1 18 RA1
RA0
(PIC16LF84A) RA3 2 17 OSC1/CLKIN
OSC2/CLKOUT
High Performance RISC CPU Features: RA4/T0CKI 3 PIC16F84A 16 VDD
RB7
Only 35 single word instructions to learn MCLR 4 15 RB6
All instructions single cycle except for program RB5
VSS 5 14 RB4
branches which are two-cycle
Operating speed: DC - 20 MHz clock input RB0/INT 6 13
DC - 200 ns instruction cycle RB1 7 12
1024 words of program memory
68 bytes of data RAM RB2 8 11
64 bytes of data EEPROM
14-bit wide instruction words RB3 9 10
8-bit wide data bytes
15 special function hardware registers SSOP
Eight-level deep hardware stack
Direct, indirect and relative addressing modes RA2 1 20 RA1
Four interrupt sources: RA3 RA0
RA4/T0CKI 2 19 OSC1/CLKIN
- External RB0/INT pin MCLR OSC2/CLKOUT
- TMR0 timer overflow VSS 3 PIC16F84A 18 VDD
- PORTB interrupt on change VSS VDD
- Data EEPROM write complete RB0/INT 4 17 RB7
RB1 RB6
Peripheral Features: RB2 5 16 RB5
RB3 RB4
13 I/O pins with individual direction control 6 15
High current sink/source for direct LED drive
7 14
- 25 mA sink max. per pin
- 25 mA source max. per pin 8 13
TMR0: 8-bit timer/counter with 8-bit
programmable prescaler 9 12
Special Microcontroller Features: 10 11
1000 erase/write cycles Enhanced Flash program CMOS Enhanced Flash/EERPOM Technology:
memory
Low-power, high-speed technology
1,000,000 typical erase/write cycles EEPROM data Fully static design
memory Wide operating voltage range:
EEPROM Data Retention > 40 years - Commercial: 2.0V to 5.5V
In-Circuit Serial Programming (ICSPTM) - via two - Industrial: 2.0V to 5.5V
Low power consumption:
pins - < 2 mA typical @ 5V, 4 MHz
Power-on Reset (POR), Power-up Timer (PWRT), - 15 A typical @ 2V, 32 kHz
- < 0.5 A typical standby current @ 2V
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Code-protection
Power saving SLEEP mode
Selectable oscillator options
1998 Microchip Technology Inc. Preliminary DS35007A-page 1
PIC16F84A
Table of Contents
1.0 Device Overview ............................................................................................................................................................................ 3
2.0 Memory Organization..................................................................................................................................................................... 5
3.0 I/O Ports....................................................................................................................................................................................... 13
4.0 Timer0 Module ............................................................................................................................................................................. 17
5.0 Data EEPROM Memory............................................................................................................................................................... 19
6.0 Special Features of the CPU ....................................................................................................................................................... 21
7.0 Instruction Set Summary.............................................................................................................................................................. 33
8.0 Development Support .................................................................................................................................................................. 35
9.0 Electrical Characteristics for PIC16F84A..................................................................................................................................... 41
10.0 DC & AC Characteristics Graphs/Tables ..................................................................................................................................... 53
11.0 Packaging Information ................................................................................................................................................................. 55
Appendix A: Revision History ........................................................................................................................................................... 59
Appendix B: Conversion Considerations.......................................................................................................................................... 59
Appendix C: Migration from Baseline to Midrange Devices ............................................................................................................. 62
Index ................................................................................................................................................................................................... 63
On-Line Support................................................................................................................................................................................... 65
Reader Response ................................................................................................................................................................................ 66
PIC16F84A Product Identification System ........................................................................................................................................... 67
To Our Valued Customers
Most Current Data Sheet
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DS35007A-page 2 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
1.0 DEVICE OVERVIEW The program memory contains 1K words, which trans-
lates to 1024 instructions, since each 14-bit program
This document contains device-specific information for memory word is the same width as each device instruc-
the operation of the PIC16F84A device. Additional tion. The data memory (RAM) contains 68 bytes. Data
information may be found in the PICmicroTM Mid-Range EEPROM is 64 bytes.
Reference Manual, (DS33023), which may be down-
loaded from the Microchip website. The Reference There are also 13 I/O pins that are user-configured on
Manual should be considered a complementary docu- a pin-to-pin basis. Some pins are multiplexed with other
ment to this data sheet, and is highly recommended device functions. These functions include:
reading for a better understanding of the device archi-
tecture and operation of the peripheral modules. External interrupt
Change on PORTB interrupt
The PIC16F84A belongs to the mid-range family of the Timer0 clock input
PICmicroTM microcontroller devices. A block diagram of
the device is shown in Figure 1-1. Table 1-1 details the pinout of the device with descrip-
tions and details for each pin.
FIGURE 1-1: PIC16F84A BLOCK DIAGRAM
Flash 13 Data Bus 8 EEPROM Data Memory
Program Program Counter
Memory RAM EEDATA EEPROM
PIC16F84A 8 Level Stack File Registers Data Memory
1K x 14 (13-bit)
PIC16F84A 64 x 8
Program 68 x 8
Bus 14 EEADR
7 RAM Addr RA4/T0CKI
Instruction reg Addr Mux
5 Direct Addr 7 Indirect TMR0
Addr
FSR reg
STATUS reg
8
Power-up MUX 8 I/O Ports
Timer ALU
Instruction W reg RA3:RA0
Decode & Oscillator RB7:RB1
Start-up Timer RB0/INT
Control
Power-on
Timing Reset
Generation
Watchdog
Timer
OSC2/CLKOUT MCLR VDD, VSS
OSC1/CLKIN
1998 Microchip Technology Inc. Preliminary DS35007A-page 3
PIC16F84A
TABLE 1-1 PIC16F84A PINOUT DESCRIPTION
Pin Name DIP SOIC SSOP I/O/P Buffer Description
Type
No. No. No. Type
OSC1/CLKIN 16 16 18 I ST/CMOS (3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 15 15 19 O -- Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR 4 4 4 I/P ST Master clear (reset) input/programming voltage input. This
RA0 pin is an active low reset to the device.
RA1
RA2 PORTA is a bi-directional I/O port.
RA3
17 17 19 I/O TTL
18 18 20 I/O TTL
1 1 1 I/O TTL
2 2 2 I/O TTL
RA4/T0CKI 3 3 3 I/O ST Can also be selected to be the clock input to the TMR0
timer/counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 6 6 7 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt
pin.
RB1 7 7 8 I/O TTL
RB2 8 8 9 I/O TTL
RB3 9 9 10 I/O TTL
RB4 10 10 11 I/O TTL Interrupt on change pin.
RB5 11 11 12 I/O TTL Interrupt on change pin.
RB6 12 12 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.
RB7 13 13 14 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.
VSS 5 5 5,6 P -- Ground reference for logic and I/O pins.
VDD 14 14 15,16 P -- Positive supply for logic and I/O pins.
Legend: I= input O = output I/O = Input/Output P = power
Note 1: -- = Not used TTL = TTL input ST = Schmitt Trigger input
2:
3: This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS35007A-page 4 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
2.0 MEMORY ORGANIZATION FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK - PIC16F84A
There are two memory blocks in the PIC16F84A.
These are the program memory and the data memory. PC
Each block has its own bus, so that access to each
block can occur during the same oscillator cycle. CALL, RETURN 13
The data memory can further be broken down into the RETFIE, RETLW
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that Stack Level 1
control the "core" are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
Stack Level 8
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped Reset Vector 0000h
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the Peripheral Interrupt Vector 0004h
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range User Memory
0h-3Fh. More details on the EEPROM memory can be Space
found in Section 5.0.
3FFh
Additional information on device memory may be found 1FFFh
in the PICmicroTM Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space.
For the PIC16F84A, the first 1K x 14 (0000h-03FFh)
are physically implemented (Figure 2-1). Accessing a
location above the physically implemented address will
cause a wraparound. For example, for locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
1998 Microchip Technology Inc. Preliminary DS35007A-page 5
PIC16F84A 2.2.1 GENERAL PURPOSE REGISTER FILE
2.2 Data Memory Organization Each General Purpose Register (GPR) is 8 bits wide
and is accessed either directly or indirectly through the
The data memory is partitioned into two areas. The first FSR (Section 2.4).
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area. The GPR addresses in bank 1 are mapped to
The SFRs control the operation of the device. addresses in bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is FIGURE 2-1: REGISTER FILE MAP -
banked to allow greater than 116 bytes of general PIC16F84A
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking File Address File Address
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register. 00h Indirect addr.(1) Indirect addr.(1) 80h
Figure 2-1 shows the data memory map organization.
01h TMR0 OPTION_REG 81h
Instructions MOVWF and MOVF can move values from
the W register to any location in the register file ("F"), 02h PCL PCL 82h
and vice-versa.
03h STATUS STATUS 83h
The entire data memory can be accessed either
directly using the absolute address of each register file 04h FSR FSR 84h
or indirectly through the File Select Register (FSR)
(Section 2.4). Indirect addressing uses the present 05h PORTA TRISA 85h
value of the RP0 bit for access into the banked areas of
data memory. 06h PORTB TRISB 86h
Data memory is partitioned into two banks which 07h 87h
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the 08h EEDATA EECON1 88h
RP0 bit (STATUS). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first 09h EEADR EECON2(1) 89h
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen- 0Ah PCLATH PCLATH 8Ah
eral Purpose Registers implemented as static RAM.
0Bh INTCON INTCON 8Bh
0Ch 8Ch
68 Mapped
General (accesses)
Purpose in Bank 0
Registers
(SRAM)
4Fh CFh
50h D0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
DS35007A-page 6 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
2.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two
sets, core and peripheral. Those associated with the
The Special Function Registers (Figure 2-1 and core functions are described in this section. Those
Table 2-1) are used by the CPU and Peripheral related to the operation of the peripheral features are
functions to control the device operation. These described in the section for that specific feature.
registers are static RAM.
TABLE 2-1 REGISTER FILE SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset (Note3)
Bank 0
00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
xxxx xxxx uuuu uuuu
01h TMR0 8-bit real-time clock/counter 0000 0000 0000 0000
000q quuu
02h PCL Low order 8 bits of the Program Counter (PC) uuuu uuuu
---u uuuu
03h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx
uuuu uuuu
04h FSR Indirect data memory address pointer 0 xxxx xxxx
---- ----
05h PORTA (4) -- -- -- RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx uuuu uuuu
uuuu uuuu
06h PORTB (5) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx ---0 0000
0000 000u
07h Unimplemented location, read as '0' ---- ----
xxxx xxxx
08h EEDATA EEPROM data register xxxx xxxx
09h EEADR EEPROM address register
0Ah PCLATH -- -- -- Write buffer for upper 5 bits of the PC (1) ---0 0000
0Bh INTCON 0000 000x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
Bank 1 Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
80h INDF
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
0000 0000 0000 0000
82h PCL Low order 8 bits of Program Counter (PC)
83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
85h TRISA -- -- -- PORTA data direction register ---1 1111 ---1 1111
86h TRISB PORTB data direction register 1111 1111 1111 1111
87h Unimplemented location, read as '0' ---- ---- ---- ----
88h EECON1 -- -- -- EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0Ah PCLATH -- -- -- Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never transferred
2: to PCLATH.
3: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: On any device reset, these pins are configured as inputs.
This is the value that will be in the port output latch.
1998 Microchip Technology Inc. Preliminary DS35007A-page 7
PIC16F84A
2.2.2.1 STATUS REGISTER Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 7-2)
The STATUS register contains the arithmetic status of because these instructions do not affect any status bit.
the ALU, the RESET status and the bank select bit for
data memory. Note 1: The IRP and RP1 bits (STATUS) are
not used by the PIC16F84A and should be
As with any register, the STATUS register can be the programmed as cleared. Use of these bits
destination for any instruction. If the STATUS register is as general purpose R/W bits is NOT
the destination for an instruction that affects the Z, DC recommended, since this may affect
or C bits, then the write to these three bits is disabled. upward compatibility with future products.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable. Note 2: The C and DC bits operate as a borrow
Therefore, the result of an instruction with the STATUS and digit borrow out bit, respectively, in
register as destination may be different than intended. subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register Note 3: When the STATUS register is the
as 000u u1uu (where u = unchanged). destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP
RP1 RP0 TO PD Z DC C R = Readable bit
bit7
bit0 W = Writable bit
bit 7: U = Unimplemented bit,
read as `0'
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
The IRP bit is not used by the PIC16F84A. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F84A. RP1 should be maintained clear.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.
DS35007A-page 8 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
2.2.2.2 OPTION_REG REGISTER Note: When the prescaler is assigned to
the WDT (PSA = '1'), TMR0 has a 1:1
The OPTION_REG register is a readable and writable prescaler assignment.
register which contains various control bits to configure
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 2-1: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R = Readable bit
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit
bit7 U = Unimplemented bit,
bit0
read as `0'
- n = Value at POR reset
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
1998 Microchip Technology Inc. Preliminary DS35007A-page 9
PIC16F84A
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
The INTCON register is a readable and writable its corresponding enable bit or the global
register which contains the various enable bits for all enable bit, GIE (INTCON).
interrupt sources.
FIGURE 2-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R = Readable bit
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF W = Writable bit
U = Unimplemented bit,
bit7 bit0
read as `0'
- n = Value at POR reset
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section .
bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1: INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
DS35007A-page 10 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
2.3 PCL and PCLATH 2.4 Indirect Addressing; INDF and FSR
Registers
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits The INDF register is not a physical register. Address-
wide. The low byte is called the PCL register. This reg- ing INDF actually addresses the register whose
ister is readable and writable. The high byte is called address is contained in the FSR register (FSR is a
the PCH register. This register contains the PC pointer). This is indirect addressing.
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register. EXAMPLE 2-1: INDIRECT ADDRESSING
Register file 05 contains the value 10h
2.3.1 STACK Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
The stack allows a combination of up to 8 program calls A read of the INDF register will return the value of
and interrupts to occur. The stack contains the return
address from this branch in program execution. 10h
Increment the value of the FSR register by one
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either (FSR = 06)
program or data space and the stack pointer is not A read of the INDF register now will return the
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt value of 0Ah.
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution. Reading INDF itself indirectly (FSR = 0) will produce
PCLATH is not modified when the stack is PUSHed or 00h. Writing to the INDF register indirectly results in a
POPed. no-operation (although STATUS bits may be affected).
After the stack has been PUSHed eight times, the ninth A simple program to clear RAM locations 20h-2Fh
push overwrites the value that was stored from the first using indirect addressing is shown in Example 2-2.
push. The tenth push overwrites the second push (and
so on). EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
NEXT movlw ADDRESSING
CONTINUE movwf
clrf 0x20 ;initialize pointer
incf FSR ; to RAM
btfss INDF ;clear INDF register
goto FSR ;inc pointer
FSR,4 ;all done?
: NEXT ;NO, clear next
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 2-1. However, IRP is not used in the
PIC16F84A.
1998 Microchip Technology Inc. Preliminary DS35007A-page 11
PIC16F84A
FIGURE 2-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
RP1 RP0 6 from opcode 0 IRP 7 (FSR) 0
(2)
(2)
bank select location select bank select location select
00 01
00h 80h
Data 0Bh Addresses
Memory (1) 0Ch map back
to Bank 0
4Fh
50h (3)
FFh
(3)
7Fh Bank 1
Bank 0
Note 1: For memory map detail see Figure 2-1.
2: Maintain as clear for upward compatiblity with future products.
3: Not implemented.
DS35007A-page 12 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
3.0 I/O PORTS FIGURE 3-1: BLOCK DIAGRAM OF PINS
RA3:RA0
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the Data
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin. bus
Additional information on I/O ports may be found in the D Q
PICmicroTM Mid-Range Reference Manual,
(DS33023). WR VDD
3.1 PORTA and TRISA Registers Port CK Q
PORTA is a 5-bit wide bi-directional port. The corre- P
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin Data Latch
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will N I/O pin
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin. D Q
Note: On a Power-on Reset, these pins are con- WR VSS
figured as inputs and read as '0'.
TRIS CK Q
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All TRIS Latch TTL
write operations are read-modify-write operations. input
Therefore a write to a port implies that the port pins are buffer
read, this value is modified, and then written to the port
data latch. RD TRIS
Pin RA4 is multiplexed with the Timer0 module clock Q D
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output. EN
All other RA port pins have TTL input levels and full RD PORT
CMOS output drivers.
Note: I/O pins have protection diodes to VDD and VSS.
EXAMPLE 3-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA as inputs
; RA4 as output
; TRISA are always
; read as '0'.
1998 Microchip Technology Inc. Preliminary DS35007A-page 13
PIC16F84A
FIGURE 3-2: BLOCK DIAGRAM OF PIN RA4
Data DQ
bus CK Q
Data Latch
WR
PORT
N RA4 pin
VSS
WR DQ
TRIS CK Q
TRIS Latch
Schmitt
Trigger
input
buffer
RD TRIS
Q D
EENN
RD PORT
TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
TABLE 3-1 PORTA FUNCTIONS
Name Bit0 Buffer Type Function
RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
05h PORTA -- -- -- RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA -- -- -- TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS35007A-page 14 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
3.2 PORTB and TRISB Registers Four of PORTB's pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
PORTB is an 8-bit wide bi-directional port. The corre- cause this interrupt to occur (i.e. any RB7:RB4 pin con-
sponding data direction register is TRISB. Setting a figured as an output is excluded from the interrupt on
TRISB bit (=1) will make the corresponding PORTB pin change comparison). The input pins (of RB7:RB4) are
an input, i.e., put the corresponding output driver in a compared with the old value latched on the last read of
hi-impedance mode. Clearing a TRISB bit (=0) will PORTB. The "mismatch" outputs of RB7:RB4 are
make the corresponding PORTB pin an output, i.e., put OR'ed together to generate the RB Port Change Inter-
the contents of the output latch on the selected pin. rupt with flag bit RBIF (INTCON).
EXAMPLE 3-1: INITIALIZING PORTB This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
BCF STATUS, RP0 ; rupt in the following manner:
CLRF PORTB ; Initialize PORTB by a) Any read or write of PORTB. This will end the
mismatch condition.
; clearing output
b) Clear flag bit RBIF.
; data latches
A mismatch condition will continue to set flag bit RBIF.
BSF STATUS, RP0 ; Select Bank 1 Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
MOVLW 0xCF ; Value used to
The interrupt on change feature is recommended for
; initialize data wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
; direction feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
MOVWF TRISB ; Set RB as inputs
; RB as outputs
; RB as inputs
Each of the PORTB pins has a weak internal pull-up. A FIGURE 3-4: BLOCK DIAGRAM OF PINS
single control bit can turn on all the pull-ups. This is per- RB3:RB0
formed by clearing bit RBPU (OPTION). The weak RBPU(1)
pull-up is automatically turned off when the port pin is Data bus VDD
configured as an output. The pull-ups are disabled on a WR Port
Power-on Reset.
WR TRIS
FIGURE 3-3: BLOCK DIAGRAM OF PINS P weak
RB7:RB4 pull-up
VDD Data Latch I/O
DQ pin(2)
RBPU(1) weak
Data bus P pull-up CK
WR Port
Data Latch I/O TRIS Latch TTL
WR TRIS DQ pin(2) DQ Input
Buffer
CK CK
TRIS Latch
TTL RD TRIS QD
DQ Input RD Port EN
Buffer
CK
RD TRIS Latch RB0/INT
RD Port QD
Schmitt Trigger RD Port
EN Buffer
Set RBIF Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
From other QD
RB7:RB4 pins EN
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1998 Microchip Technology Inc. Preliminary DS35007A-page 15
PIC16F84A
TABLE 3-3 PORTB FUNCTIONS
Name Bit Buffer Type I/O Consistency Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT
86h TRISB TRISB4 TRISB1 TRISB0 Reset uuuu uuuu
TRISB7 TRISB6 TRISB5 TRISB3 TRISB2 1111 1111
xxxx xxxx 1111 1111
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS35007A-page 16 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
4.0 TIMER0 MODULE Additional information on external clock requirements
is available in the PICmicroTM Mid-Range Reference
The Timer0 module timer/counter has the following fea- Manual, (DS33023).
tures:
4.2 Prescaler
8-bit timer/counter
Readable and writable An 8-bit counter is available as a prescaler for the
Internal or external clock select Timer0 module, or as a postscaler for the Watchdog
Edge select for external clock Timer, respectively (Figure 4-2). For simplicity, this
8-bit software programmable prescaler counter is being referred to as "prescaler" throughout
Interrupt on overflow from FFh to 00h this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
Figure 4-1 is a simplified block diagram of the Timer0 the Timer0 module and the Watchdog Timer. Thus, a
module. prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
Additional information on timer modules is available in vice-versa.
the PICmicroTM Mid-Range Reference Manual,
(DS33023). The prescaler is not readable or writable.
4.1 Timer0 Operation The PSA and PS2:PS0 bits (OPTION_REG)
determine the prescaler assignment and prescale ratio.
Timer0 can operate as a timer or as a counter.
Clearing bit PSA will assign the prescaler to the Timer0
Timer mode is selected by clearing bit T0CS module. When the prescaler is assigned to the Timer0
(OPTION_REG). In timer mode, the Timer0 mod- module, prescale values of 1:2, 1:4, ..., 1:256 are
ule will increment every instruction cycle (without pres- selectable.
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The Setting bit PSA will assign the prescaler to the Watch-
user can work around this by writing an adjusted value dog Timer (WDT). When the prescaler is assigned to
to the TMR0 register. the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG). In counter mode, Timer0 will When assigned to the Timer0 module, all instructions
increment either on every rising or falling edge of pin writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
RA4/T0CKI. The incrementing edge is determined by BSF 1,x....etc.) will clear the prescaler. When
the Timer0 Source Edge Select bit T0SE assigned to WDT, a CLRWDT instruction will clear the
(OPTION_REG). Clearing bit T0SE selects the ris- prescaler along with the WDT.
ing edge. Restrictions on the external clock input are
discussed below. Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
When an external clock input is used for Timer0, it must count, but will not change the prescaler
meet certain requirements. The requirements ensure assignment.
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
FOSC/4 0 Programmable PSout Sync with PSout Data bus
1 Prescaler 1 Internal 8
RA4/T0CKI clocks
pin T0CS 3 0 TMR0
PS2, PS1, PS0
T0SE (2 cycle delay) Set interrupt
flag bit T0IF
PSA on overflow
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
1998 Microchip Technology Inc. Preliminary DS35007A-page 17
PIC16F84A
4.2.1 SWITCHING PRESCALER ASSIGNMENT 4.3 Timer0 Interrupt
The prescaler assignment is fully under software con- The TMR0 interrupt is generated when the TMR0 reg-
trol, i.e., it can be changed "on the fly" during program ister overflows from FFh to 00h. This overflow sets bit
execution. T0IF (INTCON). The interrupt can be masked by
clearing bit T0IE (INTCON). Bit T0IF must be
Note: To avoid an unintended device RESET, a cleared in software by the Timer0 module interrupt ser-
specific instruction sequence (shown in the vice routine before re-enabling this interrupt. The
PICmicroTM Mid-Range Reference Man- TMR0 interrupt cannot awaken the processor from
ual, DS3023) must be executed when SLEEP since the timer is shut off during SLEEP.
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus
CLKOUT (=Fosc/4)
RA4/T0CKI 0M 1 SYNC 8
pin U M 2 TMR0 reg
X
0 U Cycles Set flag bit T0IF
1 X on Overflow
T0SE T0CS
PSA
Watchdog 0 8-bit Prescaler PS2:PS0
Timer M 8
U
WDT Enable bit 8 - to - 1MUX
1X
PSA
0 1
MUX PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
POR, other resets
BOR
01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA -- -- PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS35007A-page 18 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
5.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
The EEPROM data memory is readable and writable writes the new data (erase before write). The EEPROM
during normal operation (full VDD range). This memory data memory is rated for high erase/write cycles. The
is not directly mapped in the register file space. Instead write time is controlled by an on-chip timer. The write-
it is indirectly addressed through the Special Function time will vary with voltage and temperature as well as
Registers. There are four SFRs used to read and write from chip to chip. Please refer to AC specifications for
this memory. These registers are: exact limits.
EECON1 When the device is code protected, the CPU may
EECON2 (Not a physically implemented register) continue to read and write the data EEPROM memory.
EEDATA The device programmer can no longer access
EEADR this memory.
EEDATA holds the 8-bit data for read/write, and EEADR Additional information on the Data EEPROM is avail-
holds the address of the EEPROM location being able in the PICmicroTM Mid-Range Reference Manual,
accessed. PIC16F84A devices have 64 bytes of data (DS33023).
EEPROM with an address range from 0h to 3Fh.
FIGURE 5-1: EECON1 REGISTER (ADDRESS 88h)
U U U R/W-0 R/W-x R/W-0 R/S-0 R/S-x
--
bit7 -- -- EEIF WRERR WREN WR RD R = Readable bit
bit 7:5 bit0 W = Writable bit
bit 4 S = Settable bit
bit 3
U = Unimplemented bit,
bit 2
bit 1 read as `0'
bit 0 - n = Value at POR reset
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
1998 Microchip Technology Inc. Preliminary DS35007A-page 19
PIC16F84A
5.1 Reading the EEPROM Data Memory code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
To read a data memory location, the user must write the updating EEPROM. The WREN bit is not cleared
address to the EEADR register and then set control bit by hardware
RD (EECON1). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be After a write sequence has been initiated, clearing the
read in the next instruction. EEDATA will hold this value WREN bit will not affect this write cycle. The WR bit will
until another read or until it is written to by the user be inhibited from being set unless the WREN bit is set.
(during a write operation).
At the completion of the write cycle, the WR bit is
EXAMPLE 5-1: DATA EEPROM READ cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
BCF STATUS, RP0 ; Bank 0 enable this interrupt or poll this bit. EEIF must be
MOVLW CONFIG_ADDR ; cleared by software.
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1 5.3 Write Verify
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0 Depending on the application, good programming prac-
MOVF EEDATA, W ; W = EEDATA tice may dictate that the value written to the Data
EEPROM should be verified (Example 5-1) to the
5.2 Writing to the EEPROM Data Memory desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
To write an EEPROM data location, the user must first near the specification limit. The Total Endurance disk
write the address to the EEADR register and the data will help determine your comfort level.
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte. Generally the EEPROM write failure will be a bit which
was written as a '0', but reads back as a '1' (due to
leakage off the bit).
EXAMPLE 5-1: DATA EEPROM WRITE
BSF STATUS, RP0 ; Bank 1 EXAMPLE 5-1: WRITE VERIFY
BCF
BSF INTCON, GIE ; Disable INTs. BCF STATUS, RP0 ; Bank 0
MOVLW
MOVWF EECON1, WREN ; Enable Write : ; Any code can go here
MOVLW
MOVWF 55h ; : ;
BSF
EECON2 ; Write 55h MOVF EEDATA, W ; Must be in Bank 0
BSF AAh ;
Required EECON2 ; Write AAh BSF STATUS, RP0 ; Bank 1
Sequence EECON1,WR ; Set WR bit
; begin write READ
INTCON, GIE ; Enable INTs.
BSF EECON1, RD ; YES, Read the
; value written
BCF STATUS, RP0 ; Bank 0
;
The write will not initiate if the above sequence is not ; Is the value written (in W reg) and
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly ; read (in EEDATA) the same?
recommend that interrupts be disabled during this
code segment. ;
Additionally, the WREN bit in EECON1 must be set to SUBWF EEDATA, W ;
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected) BTFSS STATUS, Z ; Is difference 0?
GOTO WRITE_ERR ; NO, Write error
: ; YES, Good write
: ; Continue program
TABLE 5-1 REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
88h EECON1 -- -- -- EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by data EEPROM.
DS35007A-page 20 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
6.0 SPECIAL FEATURES OF THE the chip in reset until the crystal oscillator is stable. The
CPU other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
What sets a microcontroller apart from other design keeps the device in reset while the power supply
processors are special circuits to deal with the needs of stabilizes. With these two timers on-chip, most
real time applications. The PIC16F84A has a host of applications need no external reset circuitry.
such features intended to maximize system reliability,
minimize cost through elimination of external SLEEP mode offers a very low current power-down
components, provide power saving operating modes mode. The user can wake-up from SLEEP through
and offer code protection. These features are: external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
OSC Selection allow the part to fit the application. The RC oscillator
Reset option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
- Power-on Reset (POR) select the various options.
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST) Additional information on special features is available in
Interrupts the PICmicroTM Mid-Range Reference Manual,
Watchdog Timer (WDT) (DS33023).
SLEEP
Code protection 6.1 Configuration Bits
ID locations
In-circuit serial programming The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
The PIC16F84A has a Watchdog Timer which can be device configurations. These bits are mapped in
shut off only through configuration bits. It runs off its program memory location 2007h.
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is Address 2007h is beyond the user program memory
the Oscillator Start-up Timer (OST), intended to keep space and it belongs to the special test/configuration
memory space (2000h - 3FFFh). This space can only
be accessed during programming.
FIGURE 6-1: CONFIGURATION WORD - PIC16F84A
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP CP CP CP CP CP CP CP CP CP PWRTE
WDTE FOSC1 FOSC0
bit13
bit0
bit 13:4 CP: Code Protection bit
1 = Code protection off R = Readable bit
0 = All memory is code protected P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
1998 Microchip Technology Inc. Preliminary DS35007A-page 21
PIC16F84A
6.2 Oscillator Configurations TABLE 6-1 CAPACITOR SELECTION
FOR CERAMIC RESONATORS
6.2.1 OSCILLATOR TYPES
The PIC16F84A can be operated in four different Ranges Tested:
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of Mode Freq OSC1/C1 OSC2/C2
these four modes:
XT 455 kHz 47 - 100 pF 47 - 100 pF
2.0 MHz 15 - 33 pF 15 - 33 pF
LP Low Power Crystal 4.0 MHz 15 - 33 pF 15 - 33 pF
XT Crystal/Resonator
HS High Speed Crystal/Resonator HS 8.0 MHz 15 - 33 pF 15 - 33 pF
RC Resistor/Capacitor
10.0 MHz 15 - 33 pF 15 - 33 pF
Note : Recommended values of C1 and C2 are identical to
the ranges tested table.
6.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
In XT, LP or HS modes a crystal or ceramic resonator These values are for design guidance only. Since
is connected to the OSC1/CLKIN and OSC2/CLKOUT each resonator has its own characteristics, the user
pins to establish oscillation (Figure 6-2). should consult the resonator manufacturer for the
appropriate values of external components.
Resonators Tested:
FIGURE 6-2: CRYSTAL/CERAMIC 455 kHz Panasonic EFO-A455K04B 0.3%
RESONATOR OPERATION 2.0 MHz Murata Erie CSA2.00MG 0.5%
(HS, XT OR LP OSC 4.0 MHz Murata Erie CSA4.00MG 0.5%
CONFIGURATION) 8.0 MHz Murata Erie CSA8.00MT 0.5%
10.0 MHz Murata Erie CSA10.00MTZ 0.5%
C1(1) OSC1
None of the resonators had built-in capacitors.
To
XTAL RF(3) internal TABLE 6-2 CAPACITOR SELECTION
logic FOR CRYSTAL OSCILLATOR
OSC2 SLEEP
RS(2) PIC16FXX Mode Freq OSC1/C1 OSC2/C2
C2(1)
LP 32 kHz 68 - 100 pF 68 - 100 pF
Note1: See Table 6-1 for recommended values of 200 kHz 15 - 33 pF 15 - 33 pF
2: C1 and C2.
3: A series resistor (RS) may be required for XT 100 kHz 100 - 150 pF 100 - 150 pF
AT strip cut crystals.
RF varies with the crystal chosen. 2 MHz 15 - 33 pF 15 - 33 pF
4 MHz 15 - 33 pF 15 - 33 pF
HS 4 MHz 15 - 33 pF 15 - 33 pF
10 MHz 15 - 33 pF 15 - 33 pF
The PIC16F84A oscillator design requires the use of a Note : Higher capacitance increases the stability of
parallel cut crystal. Use of a series cut crystal may give oscillator but also increases the start-up time.
a frequency out of the crystal manufacturers These values are for design guidance only. Rs may
specifications. When in XT, LP or HS modes, the device be required in HS mode as well as XT mode to
can have an external clock source to drive the avoid overdriving crystals with low drive level spec-
OSC1/CLKIN pin (Figure 6-3). ification. Since each crystal has its own characteris-
tics, the user should consult the crystal
FIGURE 6-3: EXTERNAL CLOCK INPUT manufacturer for appropriate values of external
OPERATION (HS, XT OR LP components.
OSC CONFIGURATION)
For VDD > 4.5V, C1 = C2 30 pF is recommended.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz
Clock from OSC1 200 kHz Epson C-2 100.00 KC-P 20 PPM
ext. system PIC16FXX 1.0 MHz
2.0 MHz STD XTL 200.000 KHz 20 PPM
Open OSC2 4.0 MHz
10.0 MHz ECS ECS-10-13-2 50 PPM
ECS ECS-20-S-2 50 PPM
ECS ECS-40-S-4 50 PPM
ECS ECS-100-S-4 50 PPM
DS35007A-page 22 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
6.2.3 RC OSCILLATOR 6.3 Reset
For timing insensitive applications the RC device option The PIC16F84A differentiates between various kinds
offers additional cost savings. The RC oscillator of reset:
frequency is a function of the supply voltage, the
resistor (Rext) values, capacitor (Cext) values, and the Power-on Reset (POR)
operating temperature. In addition to this, the oscillator MCLR reset during normal operation
frequency will vary from unit to unit due to normal MCLR reset during SLEEP
process parameter variation. Furthermore, the WDT Reset (during normal operation)
difference in lead frame capacitance between package WDT Wake-up (during SLEEP)
types also affects the oscillation frequency, especially
for low Cext values. The user needs to take into Figure 6-5 shows a simplified block diagram of the
account variation due to tolerance of the external on-chip reset circuit. The MCLR reset path has a noise
R and C components. Figure 6-4 shows how an R/C filter to ignore small pulses. The electrical specifica-
combination is connected to the PIC16F84A. tions state the pulse width requirements for the MCLR
pin.
FIGURE 6-4: RC OSCILLATOR MODE
Some registers are not affected in any reset condition;
VDD their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
Rext "reset state" on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
OSC1 Internal They are not affected by a WDT reset during SLEEP,
clock since this reset is viewed as the resumption of normal
operation.
Cext PIC16FXX
Table 6-3 gives a description of reset conditions for the
VSS program counter (PC) and the STATUS register.
OSC2/CLKOUT Table 6-4 gives a full description of reset states for all
registers.
Fosc/4
The TO and PD bits are set or cleared differently in dif-
Recommended values: 5 k Rext 100 k ferent reset situations (Section 6.7). These bits are
Cext > 20pF used in software to determine the nature of the reset.
FIGURE 6-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR SLEEP S
VDD WDT WDT
Module Time_Out
Chip_Reset
Reset
VDD rise
detect Power_on_Reset
OST/PWRT
OST
10-bit Ripple counter R Q
OSC1/
CLKIN
PWRT
On-chip 10-bit Ripple counter
RC OSC(1)
Note 1: This is a separate oscillator from the Enable PWRT See Table 6-5
RC oscillator of the CLKIN pin. Enable OST
1998 Microchip Technology Inc. Preliminary DS35007A-page 23
PIC16F84A
TABLE 6-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter STATUS Register
Power-on Reset 000h 0001 1xxx
MCLR Reset during normal operation 000h 000u uuuu
MCLR Reset during SLEEP 000h 0001 0uuu
WDT Reset (during normal operation) 000h 0000 1uuu
WDT Wake-up PC + 1 uuu0 0uuu
Interrupt wake-up from SLEEP PC + 1 (1) uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 6-4 RESET CONDITIONS FOR ALL REGISTERS
Register Address Power-on Reset MCLR Reset during: Wake-up from SLEEP:
normal operation through interrupt
SLEEP through WDT Time-out
WDT Reset during nor-
mal operation
W -- xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h ---- ---- ---- ---- ---- ----
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h PC + 1(2)
STATUS 02h 0000h 000q quuu(3)
uuuq quuu(3)
03h 0001 1xxx
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
---u uuuu ---u uuuu
PORTA(4) 05h ---x xxxx uuuu uuuu uuuu uuuu
PORTB(5) 06h xxxx xxxx
EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000u uuuu uuuu(1)
0Bh 0000 000x
INDF 80h ---- ---- ---- ---- ---- ----
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
PCL 82h 0000h 0000h PC + 1
STATUS 000q quuu(3) uuuq quuu(3)
83h 0001 1xxx
FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
EECON1 88h ---0 x000 ---0 q000 ---0 uuuu
EECON2 89h ---- ---- ---- ---- ---- ----
PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000u uuuu uuuu(1)
8Bh 0000 000x
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
2: Table 6-3 lists the reset value for each specific condition.
3: On any device reset, these pins are configured as inputs.
4: This is the value that will be in the port output latch.
5:
DS35007A-page 24 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
6.4 Power-on Reset (POR) FIGURE 6-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
A Power-on Reset pulse is generated on-chip when VDD POWER-UP)
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, just tie the MCLR pin VDD VDD
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to D R
create Power-on Reset. A minimum rise time for VDD
must be met for this to operate properly. See Electrical C R1
Specifications for details. MCLR
When the device starts normal operation (exits the PIC16FXX
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure Note 1: External Power-on Reset circuit is required
operation. If these conditions are not met, the device only if VDD power-up rate is too slow. The
must be held in reset until the operating conditions diode D helps discharge the capacitor
are met. quickly when VDD powers down.
For additional information, refer to Application Note 2: R < 40 k is recommended to make sure
AN607, "Power-up Trouble Shooting." that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
The POR circuit does not produce an internal reset pin is 5 A). A larger voltage drop will
when VDD declines. degrade VIH level on the MCLR pin.
6.5 Power-up Timer (PWRT) 3: R1 = 100 to 1 k will limit any current
flowing into MCLR from external
The Power-up Timer (PWRT) provides a fixed 72 ms capacitor C in the event of an MCLR pin
nominal time-out (TPWRT) from POR (Figure 6-7, breakdown due to ESD or EOS.
Figure 6-8, Figure 6-9 and Figure 6-10). The Power-up
Timer operates on an internal RC oscillator. The chip is
kept in reset as long as the PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level (Pos-
sible exception shown in Figure 6-10).
A configuration bit, PWRTE, can enable/disable the
PWRT. See Figure 6-1 for the operation of the PWRTE
bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
6.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-7, Figure 6-8, Figure 6-9
and Figure 6-10). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 6-10), an external power-on reset circuit may
be necessary (Figure 6-6).
1998 Microchip Technology Inc. Preliminary DS35007A-page 25
PIC16F84A
FIGURE 6-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 6-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
DS35007A-page 26 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
FIGURE 6-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
FIGURE 6-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD TPWRT
MCLR
INTERNAL POR TOST
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
1998 Microchip Technology Inc. Preliminary DS35007A-page 27
PIC16F84A
6.7 Time-out Sequence and Power-down 6.8 Interrupts
Status Bits (TO/PD)
The PIC16F84A has 4 sources of interrupt:
On power-up (Figure 6-7, Figure 6-8, Figure 6-9 and
Figure 6-10) the time-out sequence is as follows: First External interrupt RB0/INT pin
PWRT time-out is invoked after a POR has expired. TMR0 overflow interrupt
Then the OST is activated. The total time-out will vary PORTB change interrupts (pins RB7:RB4)
based on oscillator configuration and PWRTE Data EEPROM write complete interrupt
configuration bit status. For example, in RC mode with
the PWRT disabled, there will be no time-out at all. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
TABLE 6-5 TIME-OUT IN VARIOUS the individual and global interrupt enable bits.
SITUATIONS
The global interrupt enable bit, GIE (INTCON)
Oscillator Power-up Wake-up enables (if set) all un-masked interrupts or disables (if
Configuration from cleared) all interrupts. Individual interrupts can be
PWRT PWRT disabled through their corresponding enable bits in
XT, HS, LP Enabled Disabled SLEEP INTCON register. Bit GIE is cleared on reset.
1024TOSC
RC 72 ms + 1024TOSC The "return from interrupt" instruction, RETFIE, exits
1024TOSC -- interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
72 ms --
The RB0/INT pin interrupt, the RB port change inter-
Since the time-outs occur from the POR reset pulse, if rupt and the TMR0 overflow interrupt flags are con-
MCLR is kept low long enough, the time-outs will tained in the INTCON register.
expire. Then bringing MCLR high, execution will begin
immediately (Figure 6-7). This is useful for testing When an interrupt is responded to; the GIE bit is
purposes or to synchronize more than one PIC16F84A cleared to disable any further interrupt, the return
device when operating in parallel. address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
Table 6-6 shows the significance of the TO and PD bits. RB0/INT pin or PORTB change interrupt, the interrupt
Table 6-3 lists the reset conditions for some special latency will be three to four instruction cycles. The
registers, while Table 6-4 lists the reset conditions for exact latency depends when the interrupt event occurs.
all the registers. The latency is the same for both one and two cycle
instructions. Once in the interrupt service routine the
TABLE 6-6 STATUS BITS AND THEIR source(s) of the interrupt can be determined by polling
SIGNIFICANCE the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
TO PD Condition avoid infinite interrupt requests.
1 1 Power-on Reset Note 1: Individual interrupt flag bits are set
0 x Illegal, TO is set on POR regardless of the status of their
x 0 Illegal, PD is set on POR corresponding mask bit or the GIE bit.
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up FIGURE 6-11: INTERRUPT LOGIC
1 1 MCLR Reset during normal operation
1 0 MCLR Reset during SLEEP or interrupt
wake-up from SLEEP
T0IF Wake-up
T0IE (If in SLEEP mode)
INTF Interrupt to CPU
INTE
RBIF
RBIE
EEIF
EEIE
GIE
DS35007A-page 28 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
6.8.1 INT INTERRUPT 6.8.4 DATA EEPROM INTERRUPT
External interrupt on RB0/INT pin is edge triggered: At the completion of a data EEPROM write cycle, flag
either rising if INTEDG bit (OPTION_REG) is set, bit EEIF (EECON1) will be set. The interrupt can be
or falling, if INTEDG bit is clear. When a valid edge enabled/disabled by setting/clearing enable bit EEIE
appears on the RB0/INT pin, the INTF bit (INTCON) (Section 5.0).
(INTCON) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON). Flag bit INTF 6.9 Context Saving During Interrupts
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT During an interrupt, only the return PC value is saved
interrupt can wake the processor from SLEEP on the stack. Typically, users wish to save key register
(Section 6.11) only if the INTE bit was set prior to going values during an interrupt (e.g., W register and STATUS
into SLEEP. The status of the GIE bit decides whether register). This is implemented in software.
the processor branches to the interrupt vector
following wake-up. Example 6-1 stores and restores the STATUS and W
register's values. The User defined registers, W_TEMP
6.8.2 TMR0 INTERRUPT and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON). The interrupt can be enabled/disabled Example 6-1 does the following:
by setting/clearing enable bit T0IE (INTCON)
(Section 4.0). a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
6.8.3 PORB INTERRUPT c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit)
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled register.
by setting/clearing enable bit RBIE (INTCON) e) Restores the W register.
(Section 3.2).
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
EXAMPLE 6-1: SAVING STATUS AND W REGISTERS IN RAM
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
ISR SWAPF STATUS, W ; Swap status to be saved into W
POP MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
: :
: STATUS_TEMP, W ; Interrupt Service Routine
: STATUS ; should configure Bank as required
: W_TEMP, F ;
SWAPF W_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF ; Move W into STATUS register
; (sets bank to original state)
SWAPF ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF ; Swap nibbles in W_TEMP and place result into W
1998 Microchip Technology Inc. Preliminary DS35007A-page 29
PIC16F84A
6.10 Watchdog Timer (WDT) part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
The Watchdog Timer is a free running on-chip RC can be assigned to the WDT under software control by
oscillator which does not require any external writing to the OPTION_REG register. Thus, time-out
components. This RC oscillator is separate from the periods up to 2.3 seconds can be realized.
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN The CLRWDT and SLEEP instructions clear the WDT
and OSC2/CLKOUT pins of the device has been and the postscaler (if assigned to the WDT) and pre-
stopped, for example, by execution of a SLEEP vent it from timing out and generating a device
instruction. During normal operation a WDT time-out RESET condition.
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up The TO bit in the STATUS register will be cleared upon
and continue with normal operation. The WDT can be a WDT time-out.
permanently disabled by programming configuration bit
WDTE as a '0' (Section 6.1). 6.10.2 WDT PROGRAMMING CONSIDERATIONS
6.10.1 WDT PERIOD It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
The WDT has a nominal time-out period of 18 ms, (with WDT prescaler) it may take several seconds before a
no prescaler). The time-out periods vary with WDT time-out occurs.
temperature, VDD and process variations from part to
FIGURE 6-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 4-2)
0
M Postscaler
1U 8
WDT Timer X
8 - to -1 MUX
PS2:PS0
WDT PSA
Enable Bit
To TMR0 (Figure 4-2)
PSA
0 1
MUX
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 6-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on all
Power-on other resets
Reset
2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: See Figure 6-1 for operation of the PWRTE bit.
2: See Figure 6-1 and Section 6.12 for operation of the Code and Data protection bits.
DS35007A-page 30 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
6.11 Power-down Mode (SLEEP) 6.11.2 WAKE-UP FROM SLEEP
A device may be powered down (SLEEP) and later The device can wake-up from SLEEP through one of
powered up (Wake-up from SLEEP). the following events:
6.11.1 SLEEP 1. External reset input on MCLR pin.
The Power-down mode is entered by executing the 2. WDT Wake-up (if WDT was enabled).
SLEEP instruction.
3. Interrupt from RB0/INT pin, RB port change, or
If enabled, the Watchdog Timer is cleared (but keeps data EEPROM write complete.
running), the PD bit (STATUS) is cleared, the TO bit
(STATUS) is set, and the oscillator driver is turned Peripherals cannot generate interrupts during SLEEP,
off. The I/O ports maintain the status they had before since no on-chip Q clocks are present.
the SLEEP instruction was executed (driving high, low,
or hi-impedance). The first event (MCLR reset) will cause a device reset.
The two latter events are considered a continuation of
For the lowest current consumption in SLEEP mode, program execution. The TO and PD bits can be used to
place all I/O pins at either at VDD or VSS, with no determine the cause of a device reset. The PD bit,
external circuitry drawing current from the I/O pins, and which is set on power-up, is cleared when SLEEP is
disable external clocks. I/O pins that are hi-impedance invoked. The TO bit is cleared if a WDT time-out
inputs should be pulled high or low externally to avoid occurred (and caused wake-up).
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS. The While the SLEEP instruction is being executed, the next
contribution from on-chip pull-ups on PORTB should be instruction (PC + 1) is pre-fetched. For the device to
considered. wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
The MCLR pin must be at a logic high level (VIHMC). occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
It should be noted that a RESET generated by a WDT the instruction after the SLEEP instruction. If the GIE bit
time-out does not drive the MCLR pin low. is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 6-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 TOST(2)
CLKOUT(4)
INT pin Interrupt Latency
(Note 2)
INTF flag
(INTCON) Processor in
SLEEP
GIE bit
(INTCON)
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Inst(PC + 1) Inst(PC + 2) Dummy cycle Inst(0004h) Inst(0005h)
Instruction Inst(PC) = SLEEP SLEEP Inst(PC + 1) Dummy cycle Inst(0004h)
fetched Inst(PC - 1)
Instruction
executed
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1998 Microchip Technology Inc. Preliminary DS35007A-page 31
PIC16F84A 6.14 In-Circuit Serial Programming
6.11.3 WAKE-UP USING INTERRUPTS PIC16F84A microcontrollers can be serially
programmed while in the end application circuit. This is
When global interrupts are disabled (GIE cleared) and simply done with two lines for clock and data, and three
any interrupt source has both its interrupt enable bit other lines for power, ground, and the programming
and interrupt flag bit set, one of the following will occur: voltage. Customers can manufacture boards with
unprogrammed devices, and then program the
If the interrupt occurs before the execution of a microcontroller just before shipping the product,
SLEEP instruction, the SLEEP instruction will com- allowing the most recent firmware or custom firmware
plete as a NOP. Therefore, the WDT and WDT to be programmed.
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared. For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSPTM)
If the interrupt occurs during or after the execu- Guide, (DS30277).
tion of a SLEEP instruction, the device will imme-
diately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
6.12 Program Verification/Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note: Microchip does not recommend code pro-
tecting windowed devices.
6.13 ID Locations
Four memory locations (2000h - 2004h) are designated
as ID locations to store checksum or other code
identification numbers. These locations are not
accessible during normal execution but are readable
and writable only during program/verify. Only the
four least significant bits of ID location are usable.
DS35007A-page 32 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
7.0 INSTRUCTION SET SUMMARY Table 7-2 lists the instructions recognized by the
MPASM assembler.
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type Figure 7-1 shows the general formats that the instruc-
and one or more operands which further specify the tions can have.
operation of the instruction. The PIC16CXX instruction
set summary in Table 7-2 lists byte-oriented, bit-ori- Note: To maintain upward compatibility with
ented, and literal and control operations. Table 7-1 future PIC16CXXX products, do not use
shows the opcode field descriptions. the OPTION and TRIS instructions.
For byte-oriented instructions, 'f' represents a file reg- All examples use the following format to represent a
ister designator and 'd' represents a destination desig- hexadecimal number:
nator. The file register designator specifies which file
register is to be used by the instruction. 0xhh
where h signifies a hexadecimal digit.
The destination designator specifies where the result of FIGURE 7-1: GENERAL FORMAT FOR
the operation is to be placed. If 'd' is zero, the result is INSTRUCTIONS
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction. Byte-oriented file register operations
For bit-oriented instructions, 'b' represents a bit field 13 8 76 0
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the OPCODE d f (FILE #)
file in which the bit is located.
d = 0 for destination W
For literal and control operations, 'k' represents an d = 1 for destination f
eight or eleven bit constant or literal value. f = 7-bit file register address
Bit-oriented file register operations
TABLE 7-1 OPCODE FIELD 13 10 9 7 6 0
DESCRIPTIONS
OPCODE b (BIT #) f (FILE #)
Field Description b = 3-bit bit address
f = 7-bit file register address
Register file address (0x00 to 0x7F)
f
W Working register (accumulator) Literal and control operations
b Bit address within an 8-bit file register
k Literal field, constant data or label General
13
x Don't care location (= 0 or 1) OPCODE 87 0
k (literal)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools. k = 8-bit immediate value
d Destination select; d = 0: store result in W,
d = 1: store result in file register f. CALL and GOTO instructions only
Default is d = 1
PC Program Counter 13 11 10 0
TO Time-out bit OPCODE k (literal)
PD Power-down bit k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped A description of each instruction is available in the
into three basic categories: PICmicroTM Mid-Range Reference Manual,
(DS33023).
Byte-oriented operations
Bit-oriented operations
Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 s.
1998 Microchip Technology Inc. Preliminary DS35007A-page 33
PIC16F84A
TABLE 7-2 PIC16CXXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands
MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF 1 00 0101 dfff ffff Z 1,2
CLRF f, d AND W with f 1 00 0001 lfff ffff Z 2
CLRW 1 00 0001 0xxx xxxx Z
COMF f Clear f 1 00 1001 dfff ffff Z 1,2
DECF 1 00 0011 dfff ffff Z 1,2
DECFSZ - Clear W 1(2) 00 1011 dfff ffff 1,2,3
INCF 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Complement f 1(2) 00 1111 dfff ffff 1,2,3
IORWF 1 00 0100 dfff ffff Z 1,2
MOVF f, d Decrement f 1 00 1000 dfff ffff Z 1,2
MOVWF 1 00 0000 lfff ffff
NOP f, d Decrement f, Skip if 0 1 00 0000 0xx0 0000 C 1,2
RLF 1 00 1101 dfff ffff C 1,2
RRF f, d Increment f 1 00 1100 dfff ffff C,DC,Z 1,2
SUBWF 1 00 0010 dfff ffff 1,2
SWAPF f, d Increment f, Skip if 0 1 00 1110 dfff ffff Z 1,2
XORWF 1 00 0110 dfff ffff
f, d Inclusive OR W with f
f, d Move f
f Move W to f
- No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f
BTFSC f, b Bit Test f, Skip if Clear 1 01 01bb bfff ffff 1,2
BTFSS f, b Bit Test f, Skip if Set
1 (2) 01 10bb bfff ffff 3
1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
AND literal with W
ANDLW k Call subroutine 1 11 1001 kkkk kkkk Z
Clear Watchdog Timer
CALL k Go to address 2 10 0kkk kkkk kkkk
Inclusive OR literal with W
CLRWDT - Move literal to W 1 00 0000 0110 0100 TO,PD
Return from interrupt
GOTO k Return with literal in W 2 10 1kkk kkkk kkkk
Return from Subroutine
IORLW k Go into standby mode 1 11 1000 kkkk kkkk Z
Subtract W from literal
MOVLW k Exclusive OR literal with W 1 11 00xx kkkk kkkk
RETFIE - 2 00 0000 0000 1001
RETLW k 2 11 01xx kkkk kkkk
RETURN - 2 00 0000 0000 1000
SLEEP - 1 00 0000 0110 0011 TO,PD
SUBLW k 1 11 110x kkkk kkkk C,DC,Z
XORLW k 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS35007A-page 34 Preliminary 1998 Microchip Technology Inc.
8.0 DEVELOPMENT SUPPORT PIC16F84A
8.1 Development Tools 8.3 ICEPIC: Low-Cost PICmicroTM
In-Circuit Emulator
The PICmicrTM microcontrollers are supported with a
full range of hardware and software development tools: ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
MPLABTM-ICE Real-Time In-Circuit Emulator families of 8-bit OTP microcontrollers.
ICEPICTM Low-Cost PIC16C5X and PIC16CXXX
ICEPIC is designed to operate on PC-compatible
In-Circuit Emulator machines ranging from 386 through PentiumTM based
PRO MATE II Universal Programmer machines under Windows 3.x, Windows 95, or Win-
PICSTART Plus Entry-Level Prototype dows NT environment. ICEPIC features real time, non-
intrusive emulation.
Programmer
SIMICE 8.4 PRO MATE II: Universal Programmer
PICDEM-1 Low-Cost Demonstration Board
PICDEM-2 Low-Cost Demonstration Board The PRO MATE II Universal Programmer is a full-fea-
PICDEM-3 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone
MPASM Assembler mode as well as PC-hosted mode. PRO MATE II is CE
MPLABTM SIM Software Simulator compliant.
MPLAB-C17 (C Compiler)
Fuzzy Logic Development System The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
(fuzzyTECH-MP) at VDD min and VDD max for maximum reliability. It has
KEELOQ Evaluation Kits and Programmer an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
8.2 MPLAB-ICE: High Performance assembly to support various package types. In stand-
Universal In-Circuit Emulator with alone mode the PRO MATE II can read, verify or pro-
MPLAB IDE gram PIC12CXXX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
The MPLAB-ICE Universal In-Circuit Emulator is configuration and code-protect bits in this mode.
intended to provide the product development engineer
with a complete microcontroller design tool set for 8.5 PICSTART Plus Entry Level
PICmicro microcontrollers (MCUs). MPLAB-ICE is sup- Development System
plied with the MPLAB Integrated Development Environ-
ment (IDE), which allows editing, "make" and The PICSTART programmer is an easy-to-use, low-
download, and source debugging from a single envi- cost prototype programmer. It connects to the PC via
ronment. one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
Interchangeable processor modules allow the system programmer simple and efficient. PICSTART Plus is not
to be easily reconfigured for emulation of different pro- recommended for production programming.
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip micro- PICSTART Plus supports all PIC12CXXX, PIC14C000,
controllers. PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
The MPLAB-ICE Emulator System has been designed PIC16C923, PIC16C924 and PIC17C756 may be sup-
as a real-time emulation system with advanced fea- ported with an adapter socket. PICSTART Plus is CE
tures that are generally found on more expensive devel- compliant.
opment tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x or
Windows 95 environment were chosen to best make
these features available to you, the end user.
MPLAB-ICE is available in two versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor mod-
ules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed reange of the PICmicro
MCU.
1998 Microchip Technology Inc. Preliminary DS35007A-page 35
PIC16F84A 8.8 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
8.6 SIMICE Entry-Level Hardware
Simulator The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
SIMICE is an entry-level hardware development sys- PIC16C73 and PIC16C74 microcontrollers. All the
tem designed to operate in a PC-based environment necessary hardware and software is included to
with Microchip's simulator MPLABTM-SIM. Both SIM- run the basic demonstration programs. The user
ICE and MPLAB-SIM run under Microchip Technol- can program the sample microcontrollers provided
ogy's MPLAB Integrated Development Environment with the PICDEM-2 board, on a PRO MATE II pro-
(IDE) software. Specifically, SIMICE provides hardware grammer or PICSTART-Plus, and easily test firmware.
simulation for Microchip's PIC12C5XX, PIC12CE5XX, The MPLAB-ICE emulator may also be used with the
and PIC16C5X families of PICmicroTM 8-bit microcon- PICDEM-2 board to test firmware. Additional prototype
trollers. SIMICE works in conjunction with MPLAB-SIM area has been provided to the user for adding addi-
to provide non-real-time I/O port emulation. SIMICE tional hardware and connecting it to the microcontroller
enables a developer to run simulator code for driving socket(s). Some of the features include a RS-232 inter-
the target system. In addition, the target system can face, push-button switches, a potentiometer for simu-
provide input to the simulator code. This capability lated analog input, a Serial EEPROM to demonstrate
allows for simple and interactive debugging without usage of the I2C bus and separate headers for connec-
having to manually generate MPLAB-SIM stimulus tion to an LCD module and a keypad.
files. SIMICE is a valuable debugging tool for entry-
level system development. 8.9 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
8.7 PICDEM-1 Low-Cost PICmicro
Demonstration Board The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
The PICDEM-1 is a simple board which demonstrates package. It will also support future 44-pin PLCC
the capabilities of several of Microchip's microcontrol- microcontrollers with a LCD Module. All the neces-
lers. The microcontrollers supported are: PIC16C5X sary hardware and software is included to run the
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, basic demonstration programs. The user can pro-
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and gram the sample microcontrollers provided with
PIC17C44. All necessary hardware and software is the PICDEM-3 board, on a PRO MATE II program-
included to run basic demo programs. The users can mer or PICSTART Plus with an adapter socket, and
program the sample microcontrollers provided with easily test firmware. The MPLAB-ICE emulator may
the PICDEM-1 board, on a PRO MATE II or also be used with the PICDEM-3 board to test firm-
PICSTART-Plus programmer, and easily test firm- ware. Additional prototype area has been provided to
ware. The user can also connect the PICDEM-1 the user for adding hardware and connecting it to the
board to the MPLAB-ICE emulator and download the microcontroller socket(s). Some of the features include
firmware to the emulator for testing. Additional proto- an RS-232 interface, push-button switches, a potenti-
type area is available for the user to build some addi- ometer for simulated analog input, a thermistor and
tional hardware and connect it to the microcontroller separate headers for connection to an external LCD
socket(s). Some of the features include an RS-232 module and a keypad. Also provided on the PICDEM-3
interface, a potentiometer for simulated analog input, board is an LCD panel, with 4 commons and 12 seg-
push-button switches and eight LEDs connected to ments, that is capable of displaying time, temperature
PORTB. and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
DS35007A-page 36 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
8.10 MPLAB Integrated Development 8.12 Software Simulator (MPLAB-SIM)
Environment Software
The MPLAB-SIM Software Simulator allows code
The MPLAB IDE Software brings an ease of software development in a PC host environment. It allows the
development previously unseen in the 8-bit microcon- user to simulate the PICmicro series microcontrollers
troller market. MPLAB is a windows based application on an instruction level. On any given instruction, the
which contains: user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
A full featured editor output radix can be set by the user and the execution
Three operating modes can be performed in; single step, execute until break, or
in a trace mode.
- editor
- emulator MPLAB-SIM fully supports symbolic debugging using
- simulator MPLAB-C17 and MPASM. The Software Simulator
A project manager offers the low cost flexibility to develop and debug code
Customizable tool bar and key mapping outside of the laboratory environment making it an
A status bar with project information excellent multi-project software development tool.
Extensive on-line help
8.13 MPLAB-C17 Compiler
MPLAB allows you to:
The MPLAB-C17 Code Development System is a
Edit your source files (either assembly or `C') complete ANSI `C' compiler and integrated develop-
One touch assemble (or compile) and download ment environment for Microchip's PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
to PICmicro tools (automatically updates all gration capabilities and ease of use not found with
project information) other compilers.
Debug using:
- source files For easier source level debugging, the compiler pro-
- absolute listing file vides symbol information that is compatible with the
MPLAB IDE memory display.
The ability to use MPLAB with Microchip's simulator
allows a consistent platform and the ability to easily 8.14 Fuzzy Logic Development System
switch from the low cost simulator to the full featured (fuzzyTECH-MP)
emulator with minimal retraining due to development
tools. fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
8.11 Assembler (MPASM) MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
The MPASM Universal Macro Assembler is a PC- full-featured version, fuzzyTECH-MP, Edition for imple-
hosted symbolic assembler. It supports all microcon- menting more complex systems.
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families. Both versions include Microchip's fuzzyLABTM demon-
stration board for hands-on experience with fuzzy logic
MPASM offers full featured Macro capabilities, condi- systems implementation.
tional assembly, and several source and listing formats.
It generates various object code formats to support 8.15 SEEVAL Evaluation and
Microchip's development tools as well as third party Programming System
programmers.
The SEEVAL SEEPROM Designer's Kit supports all
MPASM allows full symbolic debugging from MPLAB- Microchip 2-wire and 3-wire Serial EEPROMs. The kit
ICE, Microchip's Universal Emulator System. includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
MPASM has the following features to assist in develop- product including Smart SerialsTM and secure serials.
ing software for specific use applications. The Total EnduranceTM Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
Provides translation of Assembler source code to significantly reduce time-to-market and result in an
object code for all Microchip microcontrollers. optimized system.
Macro assembly capability.
Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchip's emulator systems.
Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
1998 Microchip Technology Inc. Preliminary DS35007A-page 37
PIC16F84A
8.16 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS35007A-page 38 Preliminary 1998 Microchip Technology Inc.
1998 Microchip Technology Inc. PIC12C5XX PIC14000 24CXX HCS200 TABLE 8-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 25CXX HCS300
HCS301
93CXX
Emulator Products MPLABTM-ICE
ICEPICTM Low-Cost
In-Circuit Emulator
MPLABTM
Integrated
Software Tools Development
Environment
MPLABTM C17*
Compiler
fuzzyTECH-MP
Explorer/Edition
Preliminary Fuzzy Logic
Dev. Tool
Total EnduranceTM
Software Model
PICSTARTPlus
Programmers Low-Cost
Universal Dev. Kit
PRO MATE II
Universal
Programmer
KEELOQ
Programmer
SEEVAL
Designers Kit PIC16F84A
SIMICE
Demo Boards PICDEM-14A
PICDEM-1
DS35007A-page 39 PICDEM-2
PICDEM-3
KEELOQ
Evaluation Kit
KEELOQ
Transponder Kit
PIC16F84A
NOTES:
DS35007A-page 40 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
9.0 ELECTRICAL CHARACTERISTICS FOR PIC16F84A
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-55C to +125C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V
Voltage on MCLR with respect to VSS(1) ...................................................................................................... -0.3 to +14V
Voltage on RA4 with respect to VSS .......................................................................................................... -0.3 to +8.5V
Total power dissipation(2) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA .....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling
this pin directly to VSS.
Note 2: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1998 Microchip Technology Inc. Preliminary DS35007A-page 41
PIC16F84A
TABLE 9-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC PIC16F84A-04 PIC16F84A-20 PIC16LF84A-04
RC VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 2.0V to 5.5V
IDD: 4.5 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 4.5 mA max. at 5.5V
IPD: 14 A max. at 4V, WDT dis IPD: 1.0 A typ. at 5.5V, WDT dis IPD: 7.0 A max. at 2V WDT dis
Freq: 4.0 MHz max. at 4V Freq: 4..0 MHz max. at 4V Freq: 2.0 MHz max. at 2V
XT VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 2.0V to 5.5V
IDD: 4.5 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 4.5 mA max. at 5.5V
IPD: 14 A max. at 4V, WDT dis IPD: 1.0 A typ. at 5.5V, WDT dis IPD: 7.0 A max. at 2V WDT dis
Freq: 4.0 MHz max. at 4V Freq: 4.0 MHz max. at 4.5V Freq: 2.0 MHz max. at 2V
HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 4.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V typ. Do not use in HS mode
IPD: 1.0 A typ. at 4.5V, WDT dis IPD: 1.0 A typ. at 4.5V, WDT dis
Freq: 4.0 MHz max. at 4.5V Freq: 20 MHz max. at 4.5V
LP VDD: 4.0V to 5.5V VDD: 2.0V to 5.5V
IDD: 45 A max. at 32 kHz, 2.0V
IDD: 48 A typ. at 32 kHz, 2.0V Do not use in LP mode IPD: 7 A max. at 2.0V WDT dis
IPD: 0.6 A typ. at 3.0V, WDT dis Freq: 200 kHz max. at 2V
Freq: 200 kHz max. at 4V
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifica-
tions. It is recommended that the user select the device type that ensures the specifications required.
DS35007A-page 42 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
9.1 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial)
PIC16F84A-20 (Commercial, Industrial)
DC Characteristics Standard Operating Conditions (unless otherwise stated)
Power Supply Pins Operating temperature 0C TA +70C (commercial)
-40C TA +85C (industrial)
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage 4.0 -- 5.5 V XT, RC and LP osc configuration
D001A 4.5 -- 5.5 V HS osc configuration
D002* VDR RAM Data Retention 1.5* -- -- V Device in SLEEP mode
Voltage (Note 1)
D003 VPOR VDD Start Voltage to -- VSS -- V See section on Power-on Reset for details
ensure internal
Power-on Reset signal
D004* SVDD VDD Rise Rate to 0.05* -- -- V/ms PWRT enabled (PWRTE bit clear)
D004A*
ensure internal TBD -- -- PWRT disabled (PWRTE bit set)
Power-on Reset signal See section on Power-on Reset for details
IDD Supply Current RC and XT osc configuration (Note 4)
D010 (Note 2) -- 1.8 4.5 mA FOSC = 4.0 MHz, VDD = 5.5V
D010A -- 3 10 mA FOSC = 4.0 MHz, VDD = 5.5V
(During Flash programming)
HS osc configuration (PIC16F84A-20)
D013 -- 10 20 mA FOSC = 20 MHz, VDD = 5.5V
D020 IPD Power-down Current -- 7.0 28 A VDD = 4.0V, WDT enabled, industrial
D021 (Note 3) -- 1.0 14 A VDD = 4.0V, WDT disabled, commercial
D021A -- 1.0 16 A VDD = 4.0V, WDT disabled, industrial
D022* Module Differential -- 6.0 20* A WDTE bit set, VDD = 4.0V, commercial
Current (Note 5) -- -- 25* A WDTE bit set, VDD = 4.0V, extended
IWDT Watchdog Timer
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
1998 Microchip Technology Inc. Preliminary DS35007A-page 43
PIC16F84A
9.2 DC CHARACTERISTICS: PIC16LF84A-04 (Commercial, Industrial)
DC Characteristics Standard Operating Conditions (unless otherwise stated)
Power Supply Pins Operating temperature 0C TA +70C (commercial)
Parameter Sym -40C TA +85C (industrial)
No.
Characteristic Min Typ Max Units Conditions
D001 VDD Supply Voltage 2.0 -- 5.5 V XT, RC, and LP osc configuration
D002* 1.5* -- -- V Device in SLEEP mode
VDR RAM Data Retention
Voltage (Note 1)
D003 VPOR VDD Start Voltage to -- VSS -- V See section on Power-on Reset for details
ensure internal
Power-on Reset signal
D004* SVDD VDD Rise Rate to 0.05* -- -- V/ms PWRT enabled (PWRTE bit clear)
D004A*
ensure internal TBD -- -- PWRT disabled (PWRTE bit set)
Power-on Reset signal See section on Power-on Reset for details
IDD Supply Current RC and XT osc configuration (Note 4)
(Note 2)
D010 -- 1 4 mA FOSC = 2.0 MHz, VDD = 5.5V
D010A
-- 3 10 mA FOSC = 2.0 MHz, VDD = 5.5V
(During Flash programming)
LP osc configuration
D014 -- 15 45 A FOSC = 32 kHz, VDD = 2.0V,
WDT disabled
D020 IPD Power-down Current -- 3.0 16 A VDD = 2.0V, WDT enabled, industrial
D021 (Note 3) -- 0.4 7.0 A VDD = 2.0V, WDT disabled, commercial
D021A -- 0.4 9.0 A VDD = 2.0V, WDT disabled, industrial
D022* Module Differential -- 6.0 20* A WDTE bit set, VDD = 4.0V, commercial
Current (Note 5) -- -- 25* A WDTE bit set, VDD = 4.0V, industrial
IWDT Watchdog Timer
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD measurement.
DS35007A-page 44 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
9.3 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial)
DC Characteristics Standard Operating Conditions (unless otherwise stated)
All Pins Except Operating temperature 0C TA +70C (commercial)
Power Supply Pins
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec
Section 9.1 and Section 9.2.
Parame- Sym Characteristic Min Typ Max Units Conditions
ter
No.
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS -- 0.8 V 4.5V VDD 5.5V (Note 4)
D030A VSS -- 0.16VDD V entire range (Note 4)
D031 with Schmitt Trigger buffer VSS -- 0.2VDD V entire range
D032 MCLR, RA4/T0CKI Vss -- 0.2VDD V
D033 OSC1 (XT, HS and LP modes) Vss -- 0.3VDD V (Note 1)
D034 OSC1 (RC mode) Vss -- 0.1VDD V
Input High Voltage
VIH I/O ports --
D040 with TTL buffer 2.0 -- VDD V 4.5V VDD 5.5V (Note 4)
D040A
0.25VDD -- VDD V entire range (Note 4)
+0.8
D041 with Schmitt Trigger buffer 0.8 VDD -- VDD entire range
D042 MCLR, RA4/T0CKI 0.8 VDD -- VDD V
D043 OSC1 (XT, HS and LP modes) 0.7 VDD -- VDD V (Note 1)
D043A OSC1 (RC mode) 0.9 VDD VDD V
D050 VHYS Hysteresis of -- 0.1 -- V
Schmitt Trigger inputs
D070 IPURB PORTB weak pull-up current 50* 250* 400* A VDD = 5.0V, VPIN = VSS
Input Leakage Current
(Note 2,3)
D060 IIL I/O ports -- -- 1 A Vss VPIN VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI -- -- 5 A Vss VPIN VDD
D063 OSC1 -- -- 5 A Vss VPIN VDD, XT, HS
and LP osc configuration
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
1998 Microchip Technology Inc. Preliminary DS35007A-page 45
PIC16F84A
9.4 DC CHARACTERISTICS: PIC16F84A-04 (Commercial, Industrial)
PIC16F84A-20 (Commercial, Industrial)
PIC16LF84A-04 (Commercial, Industrial)
DC Characteristics Standard Operating Conditions (unless otherwise stated)
All Pins Except Operating temperature 0C TA +70C (commercial)
Power Supply Pins
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec Section 9.1
and Section 9.2.
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
Output Low Voltage
D080 VOL I/O ports -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V
D083 OSC2/CLKOUT
-- -- 0.6 V IOL = 1.6 mA, VDD = 4.5V,
Output High Voltage
(RC Mode Only)
D090 VOH I/O ports (Note 3) VDD-0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V
D092 OSC2/CLKOUT (Note 3) VDD-0.7 --
-- V IOH = -1.3 mA, VDD = 4.5V
D150
(RC Mode Only)
Open Drain High Voltage
VOD RA4 pin -- -- 8.5 V
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin -- -- 15 pF In XT, HS and LP modes
when external clock is used to
drive OSC1.
D101 CIO All I/O pins and OSC2 -- -- 50 pF
(RC mode)
D120 Data EEPROM Memory 1M* 10M -- E/W 25C at 5V
D121 ED Endurance VMIN --
VDRW VDD for read/write 5.5 V VMIN = Minimum operating
D122 -- 4
TDEW Erase/Write cycle time voltage
Program Flash Memory
8* ms
D130 EP Endurance 100* 1000 -- E/W
D131 VPR VDD for read VMIN --
5.5 V VMIN = Minimum operating
D132 VPEW VDD for erase/write 4.5 --
D133 TPEW Erase/Write cycle time -- 4 voltage
5.5 V
8 ms
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. Do not drive the PIC16F84A with an
external clock while the device is in RC mode, or chip damage may result.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
4: The user may choose the better of the two specs.
DS35007A-page 46 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
9.5 AC (Timing) Characteristics
9.5.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase symbols (pp) and their meanings:
pp
2 to os,osc OSC1
ost oscillator start-up timer
ck CLKOUT pwrt power-up timer
rbt RBx pins
cy cycle time t0 T0CKI
wdt watchdog timer
io I/O port
inp INT pin
mc MCLR
Uppercase symbols and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z High Impedance
1998 Microchip Technology Inc. Preliminary DS35007A-page 47
PIC16F84A
9.5.2 TIMING CONDITIONS
The temperature and voltages specified in Table 9-2
apply to all timing specifications unless otherwise
noted. All timings are measure between high and low
measurement points as indicated in Figure 9-1.
Figure 9-2 specifies the load conditions for the timing
specifications.
TABLE 9-2 TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
AC CHARACTERISTICS Operating temperature 0C TA +70C for commercial
-40C TA +85C for industrial
Operating voltage VDD range as described in DC spec Section 9.1 and Section 9.2
FIGURE 9-1: PARAMETER MEASUREMENT INFORMATION
0.7 VDD XTAL 0.9 VDD (High)
0.8 VDD RC (High)
0.3 VDD XTAL (Low) 0.1 VDD (Low)
0.15 VDD RC
OSC1 Measurement Points I/O Port Measurement Points
FIGURE 9-2: LOAD CONDITIONS
Load Condition 1 Load Condition 2
VDD/2
RL Pin CL
Pin CL VSS
VSS
RL = 464 for all pins except OSC2.
CL = 50 pF for OSC2 output.
15 pF
DS35007A-page 48 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
9.5.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 9-3: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
4 4
OSC1 3 3
1
2
CLKOUT
TABLE 9-3 EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ Max Units Conditions
FOSC External CLKIN Frequency(1) DC -- 2 MHz XT, RC osc (-04, LF)
DC -- 4 MHz XT, RC osc (-04)
DC -- 20 MHz HS osc (-20)
DC -- 200 kHz LP osc (-04, LF)
Oscillator Frequency(1) DC -- 2 MHz RC osc (-04, LF)
DC -- 4 MHz RC osc (-04)
0.1 -- 2 MHz XT osc (-04, LF)
0.1 -- 4 MHz XT osc (-04)
1.0 -- 20 MHz HS osc (-20)
DC -- 200 kHz LP osc (-04, LF)
1 Tosc External CLKIN Period(1) 500 -- -- ns XT, RC osc (-04, LF)
250 -- -- ns XT, RC osc (-04)
100 -- -- ns HS osc (-20)
5.0 -- -- s LP osc (-04, LF)
Oscillator Period(1) 500 -- -- ns RC osc (-04, LF)
250 -- -- ns RC osc (-04)
500 -- 10,000 ns XT osc (-04, LF)
250 -- 10,000 ns XT osc (-04)
100 -- 1,000 ns HS osc (-20)
5.0 -- -- s LP osc (-04, LF)
2 TCY Instruction Cycle Time(1) 0.4 4/Fosc DC s
3 TosL, Clock in (OSC1) High or Low 60 * -- -- ns XT osc (-04, LF)
TosH Time 50 * -- -- ns XT osc (-04)
2.0 * -- -- s LP osc (-04, LF)
35 * --
-- ns HS osc (-20)
4 TosR, Clock in (OSC1) Rise or Fall Time 25 * -- -- ns XT osc (-04)
TosF 50 * -- -- ns LP osc (-04, LF)
15 * -- -- ns HS osc (-20)
* These parameters are characterized but no tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1998 Microchip Technology Inc. Preliminary DS35007A-page 49
PIC16F84A
FIGURE 9-4: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1 11
10 22
CLKOUT 23 12
13 16
14 19 18
I/O Pin
(input)
17 15
I/O Pin old value new value
(output)
20, 21
Note: All tests must be done with specified capacitive loads (Figure 9-2) 50 pF on I/O pins and CLKOUT.
TABLE 9-4 CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
10 TosH2ckL OSC1 to CLKOUT Standard -- 15 30 * ns Note 1
10A Extended (LF) -- 15 120 * ns Note 1
11 TosH2ckH OSC1 to CLKOUT Standard -- 15 30 * ns Note 1
11A Extended (LF) -- 15 120 * ns Note 1
12 TckR CLKOUT rise time Standard -- 15 30 * ns Note 1
12A Extended (LF) -- 15 100 * ns Note 1
13 TckF CLKOUT fall time Standard -- 15 30 * ns Note 1
13A Extended (LF) -- 15 100 * ns Note 1
14 TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY +20 * ns Note 1
15 TioV2ckH Port in valid before Standard 0.30TCY + 30 * -- -- ns Note 1
CLKOUT Extended (LF) 0.30TCY + 80 * -- -- ns Note 1
16 TckH2ioI Port in hold after CLKOUT 0* -- -- ns Note 1
17 TosH2ioV OSC1 (Q1 cycle) to Standard -- -- 125 * ns
Port out valid Extended (LF) -- -- 250 * ns
18 TosH2ioI OSC1 (Q2 cycle) to Standard 10 * -- -- ns
Port input invalid Extended (LF) 10 * -- -- ns
(I/O in hold time)
19 TioV2osH Port input valid to Standard -75 * -- -- ns
OSC1 Extended (LF) -175 * -- -- ns
(I/O in setup time)
20 TioR Port output rise time Standard -- 10 35 * ns
20A Extended (LF) -- 10 70 * ns
21 TioF Port output fall time Standard -- 10 35 * ns
21A Extended (LF) -- 10 70 * ns
22 Tinp INT pin high Standard 20 * -- -- ns
22A or low time Extended (LF) 55 * -- -- ns
23 Trbp RB7:RB4 change INT Standard TOSC -- -- ns
23A high or low time Extended (LF) TOSC -- -- ns
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
By design
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS35007A-page 50 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
FIGURE 9-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD 30
MCLR 33
32
Internal
POR 34 31
PWRT 34
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
I/O Pins
TABLE 9-5 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2* -- -- s VDD = 5.0V, extended
31 Twdt Watchdog Timer Time-out Period 7 * 18 33 * ms VDD = 5.0V, extended
(No Prescaler)
32 Tost Oscillation Start-up Timer Period 1024TOSC ms TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28 * 72 132 * ms VDD = 5.0V, extended
34 TIOZ I/O Hi-impedance from MCLR -- -- 100 * ns
Low or reset
* These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1998 Microchip Technology Inc. Preliminary DS35007A-page 51
PIC16F84A
FIGURE 9-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
40 41
42
TABLE 9-6 TIMER0 CLOCK REQUIREMENTS
Parameter Sym Characteristic Min Typ Max Units Conditions
No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 * -- -- ns
With Prescaler 50 * -- -- ns 2.0V VDD 3.0V
30 * -- -- ns 3.0V VDD 6.0V
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 * -- -- ns
With Prescaler 50 * -- -- ns 2.0V VDD 3.0V
20 * -- -- ns 3.0V VDD 6.0V
42 Tt0P T0CKI Period TCY + 40 * -- -- ns N = prescale value
N (2, 4, ..., 256)
* These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS35007A-page 52 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
10.0 DC & AC CHARACTERISTICS GRAPHS/TABLES
No data available at this time.
1998 Microchip Technology Inc. Preliminary DS35007A-page 53
PIC16F84A
NOTES:
DS35007A-page 54 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
18L PDIP Example
XXXXXXXXXXXXXXXXX PIC16F84A-04I/P
XXXXXXXXXXXXXXXXX 9832SAW
AABBCDE
18L SOIC Example
XXXXXXXXXXXX PIC16F84A-04
XXXXXXXXXXXX /SO
XXXXXXXXXXXX
9848SAN
AABBCDE
20L SSOP Example
XXXXXXXXXX PIC16F84A-
XXXXXXXXXX 20/SS
AABBCDE 9822CAN
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA Year code (last 2 digits of calendar year)
BB Week code (week of January 1 is week `01')
C Facility code of the plant at which wafer is manufactured
O = Outside Vendor
D C = 5" Line
E S = 6" Line
H = 8" Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1998 Microchip Technology Inc. Preliminary DS35007A-page 55
PIC16F84A
11.2 K04-007 18-Lead Plastic Dual In-line (P) 300 mil
E
D
2
n 1
E1
A1
A
R L
c p
A2
eB B1
B
Units INCHES* MILLIMETERS
NOM
Dimension Limits MIN 0.300 MAX MIN NOM MAX
18
PCB Row Spacing 0.013 0.100 0.023 7.62 0.58
0.055 0.018 0.065 1.65
Number of Pins n 0.000 0.060 0.010 18 0.25
0.005 0.005 0.015 0.38
Pitch p 0.110 0.010 0.155 2.54 3.94
0.075 0.155 0.115 2.92
Lower Lead Width B 0.000 0.095 0.020 0.33 0.46 0.51
0.125 0.020 0.135 3.43
Upper Lead Width B1 0.890 0.130 0.900 1.40 1.52 22.86
0.245 0.895 0.265 6.73
Shoulder Radius R 0.230 0.255 0.270 0.00 0.13 6.86
0.310 0.250 0.387 9.83
Lead Thickness c 0.349 0.13 0.25
5 10 15 15
Top to Seating Plane A 5 10 15 2.79 3.94 15
Top of Lead to Seating Plane A1 1.91 2.41
Base to Seating Plane A2 0.00 0.51
Tip to Seating Plane L 3.18 3.30
Package Length D 22.61 22.73
Molded Package Width E 6.22 6.48
Radius to Radius Width E1 5.84 6.35
Overall Row Spacing eB 7.87 8.85
Mold Draft Angle Top 5 10
Mold Draft Angle Bottom 5 10
* Controlling Parameter.
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003"
(0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS35007A-page 56 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
11.3 K04-051 18-Lead Plastic Small Outline (SO) Wide, 300 mil
E1
p E
D
2
B n 1
X L
45 R2 A1
c A
R1 L1
A2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Pitch p 0.050 1.27
Number of Pins n 18 18
Overall Pack. Height A 0.093 0.099 0.104 2.36 2.50 2.64
Shoulder Height A1 0.048 0.058 0.068 1.22 1.47 1.73
Standoff A2 0.004 0.008 0.011 0.10 0.19 0.28
0.450 0.456 0.462 11.43 11.58 11.73
Molded Package Length D 0.292 0.296 0.299
7.42 7.51 7.59
Molded Package Width E
Outside Dimension E1 0.394 0.407 0.419 10.01 10.33 10.64
Chamfer Distance X 0.010 0.020 0.029 0.25 0.50 0.74
Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25
Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25
Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53
0 4 8 0 4 8
Foot Angle
0.010 0.015 0.020 0.25 0.38 0.51
Radius Centerline L1
Lead Thickness c 0.009 0.011 0.012 0.23 0.27 0.30
Lower Lead Width B 0.014 0.017 0.019 0.36 0.42 0.48
Mold Draft Angle Top 0 12 15 0 12 15
Mold Draft Angle Bottom 0 12 15 0 12 15
* Controlling Parameter.
Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003"
(0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
1998 Microchip Technology Inc. Preliminary DS35007A-page 57
PIC16F84A
11.4 K04-072 20-Lead Plastic Shrink Small Outine (SS) 5.30 mm
E1
E
p
D
B 2
n 1
L
R2
c
A
A1
R1
L1 A2
Units INCHES MILLIMETERS*
Dimension Limits MIN NOM MAX MIN NOM MAX
Pitch p 0.026 0.65
Number of Pins n 20 20
Overall Pack. Height A 0.068 0.073 0.078 1.73 1.86 1.99
Shoulder Height A1 0.026 0.036 0.046 0.66 0.91 1.17
Standoff A2 0.002 0.005 0.008 0.05 0.13 0.21
Molded Package Length D 0.278 0.283 0.289 7.07 7.20 7.33
Molded Package Width E 0.205 0.208 0.212 5.20 5.29 5.38
Outside Dimension E1 0.301 0.306 0.311 7.65 7.78 7.90
Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25
Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25
Foot Length L 0.015 0.020 0.025 0.38 0.51 0.64
Foot Angle 0 4 8 0 4 8
Radius Centerline L1 0.000 0.005 0.010 0.00 0.13 0.25
Lead Thickness c 0.005 0.007 0.009 0.13 0.18 0.22
Lower Lead Width B 0.010 0.012 0.015 0.25 0.32 0.38
Mold Draft Angle Top 0 5 10 0 5 10
Mold Draft Angle Bottom 0 5 10 0 5 10
* Controlling Parameter.
Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003"
(0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E."
DS35007A-page 58 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
APPENDIX A: REVISION HISTORY
Version Date Revision Description
A 9/14/98 This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16F8X Data Sheet, DS30430C.
APPENDIX B: CONVERSION CONSIDERATIONS
Considerations for converting from one PIC16X8X
device to another are listed in Table B-1.
TABLE B-1: CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A
Difference PIC16C84 PIC16F83/F84 PIC16CR83/ PIC16F84A
CR84
Program Memory 1k x 14 512 x 14 / 1k x 14 512 x 14 / 1k x 14 1k x 14
size
Data Memory size 36 x 8 36 x 8 / 68 x 8 36 x 8 / 68 x 8 68 x 8
Voltage Range 2.0V - 6.0V 2.0V - 6.0V 2.0V - 6.0V 2.0V - 5.5V
(-40C to +85C) (-40C to +85C) (-40C to +85C) (-40C to +125C)
Maximum Operat- 10MHz 10MHz 10MHz 20MHz
ing Frequency
Supply Current IDD (typ) = 60A IDD (typ) = 15A IDD (typ) = 15A IDD (typ) = 15A
(IDD). See parame- IDD (max) = 400A IDD (max) = 45A IDD (max) = 45A IDD (max) = 45A
ter # D014 in the (LP osc, FOSC = (LP osc, FOSC = (LP osc, FOSC = (LP osc, FOSC =
electrical spec's for 32kHz, VDD = 2.0V, 32kHz, VDD = 2.0V, 32kHz, VDD = 2.0V, 32kHz, VDD = 2.0V,
more detail. WDT disabled) WDT disabled) WDT disabled) WDT disabled)
Power-down Current IPD (typ) = 26A IPD (typ) = 0.4A IPD (typ) = 0.4A IPD (typ) = 0.4A
(IPD). See parame- IPD (max) = 100A IPD (max) = 9A IPD (max) = 6A IPD (max) = 9A
ters # D020, D021, (VDD = 2.0V, WDT (VDD = 2.0V, WDT (VDD = 2.0V, WDT (VDD = 2.0V, WDT
and D021A in the
electrical spec's for disabled, industrial) disabled, industrial) disabled, industrial) disabled, industrial)
more detail.
Input Low Voltage VIL (max) = 0.2VDD VIL (max) = 0.1VDD VIL (max) = 0.1VDD VIL (max) = 0.1VDD
(VIL). See parame- (Osc1, RC mode) (Osc1, RC mode) (Osc1, RC mode) (Osc1, RC mode)
ters # D032 and
D034 in the electri-
cal spec's for more
detail.
Input High Voltage VIH (min) = 0.36VDD VIH (min) = 2.4V VIH (min) = 2.4V VIH (min) = 2.4V
(VIH). See parame- (I/O Ports with TTL, (I/O Ports with TTL, (I/O Ports with TTL, (I/O Ports with TTL,
ter # D040 in the 4.5V VDD 5.5V) 4.5V VDD 5.5V) 4.5V VDD 5.5V) 4.5V VDD 5.5V)
electrical spec's for
more detail.
Data EEPROM TDEW (typ) = 10ms TDEW (typ) = 10ms TDEW (typ) = 10ms TDEW (typ) = 4ms
Memory TDEW (max) = 20ms TDEW (max) = 20ms TDEW (max) = 20ms TDEW (max) = 10ms
Erase/Write cycle
time (TDEW). See
parameter # D122 in
the electrical spec's
for more detail.
1998 Microchip Technology Inc. Preliminary DS35007A-page 59
PIC16F84A
TABLE B-1: CONVERSION CONSIDERATIONS - PIC16C84, PIC16F83/F84, PIC16CR83/CR84,
PIC16F84A
Difference PIC16C84 PIC16F83/F84 PIC16CR83/ PIC16F84A
CR84
Port Output TioR, TioF (max) = TioR, TioF (max) = TioR, TioF (max) = TioR, TioF (max) =
Rise/Fall time 25ns (C84) 35ns (C84) 35ns (C84) 35ns (C84)
(TioR, TioF). See TioR, TioF (max) = TioR, TioF (max) = TioR, TioF (max) = TioR, TioF (max) =
parameters #20, 60ns (LC84) 70ns (LC84) 70ns (LC84) 70ns (LC84)
20A, 21, and 21A in
the electrical spec's
for more detail.
MCLR on-chip fil- No Yes Yes Yes
ter. See parameter
#30 in the electrical
spec's for more
detail.
PORTA and crystal For crystal oscilla- N/A N/A N/A
oscillator values tor configurations
less than 500kHz operating below
500kHz, the device
may generate a spu-
rious internal
Q-clock when
PORTA switches
state.
RB0/INT pin TTL TTL/ST* TTL/ST* TTL/ST*
(* Schmitt Trigger) (* Schmitt Trigger) (* Schmitt Trigger)
EEADR and It is recommended N/A N/A N/A
IDD that the
EEADR bits
be cleared. When
either of these bits is
set, the maximum
IDD for the device is
higher than when
both are cleared.
The polarity of the PWRTE PWRTE PWRTE PWRTE
PWRTE bit
Recommended REXT = 3k - 100k REXT = 5k - 100k REXT = 5k - 100k REXT = 3k - 100k
value of REXT for RC
oscillator circuits
GIE bit uninten- If an interrupt occurs N/A N/A N/A
tional enable while the Global
Interrupt Enable
(GIE) bit is being
cleared, the GIE bit
may unintentionally
be re-enabled by the
user's Interrupt Ser-
vice Routine (the
RETFIE instruction).
Packages PDIP, SOIC PDIP, SOIC PDIP, SOIC PDIP, SOIC, SSOP
DS35007A-page 60 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
NOTES:
1998 Microchip Technology Inc. Preliminary DS35007A-page 61
PIC16F84A To convert code written for PIC16C5X to PIC16F84A,
the user should take the following steps:
APPENDIX C: MIGRATION FROM
BASELINE TO 1. Remove any program memory page select
MIDRANGE DEVICES operations (PA2, PA1, PA0 bits) for CALL, GOTO.
This section discusses how to migrate from a baseline 2. Revisit any computed jump operations (write to
device (i.e., PIC16C5X) to a midrange device (i.e., PC or add to PC, etc.) to make sure page bits
PIC16CXXX). are set properly under the new scheme.
The following is the list of feature improvements over 3. Eliminate any data memory page switching.
the PIC16C5X microcontroller family: Redefine data variables for reallocation.
1. Instruction word length is increased to 14 bits. 4. Verify all writes to STATUS, OPTION, and FSR
This allows larger page sizes both in program registers since these have changed.
memory (2K now as opposed to 512 before) and
the register file (128 bytes now versus 32 bytes 5. Change reset vector to 0000h.
before).
2. A PC latch register (PCLATH) is added to handle
program memory paging. PA2, PA1 and PA0 bits
are removed from the status register and placed
in the option register.
3. Data memory paging is redefined slightly. The
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW. Two
instructions, TRIS and OPTION, are being
phased out although they are kept for
compatibility with PIC16C5X.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, the Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change features.
13. T0CKI pin is also a port pin (RA4/T0CKI).
14. FSR is a full 8-bit register.
15. "In system programming" is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
DS35007A-page 62 Preliminary 1998 Microchip Technology Inc.
INDEX PIC16F84A
A INTCON Register ........................................ 7, 10, 18, 24, 28
EEIE Bit ............................................................... 10, 29
Absolute Maximum Ratings ............................................... 41 GIE Bit ........................................................... 10, 28, 29
AC (Timing) Characteristics ............................................... 47 INTE Bit ............................................................... 10, 29
Architecture, Block Diagram ................................................ 3 INTF Bit ............................................................... 10, 29
Assembler RBIE Bit ............................................................... 10, 29
RBIF Bit ......................................................... 10, 15, 29
MPASM Assembler .................................................... 37 T0IE Bit ................................................................ 10, 29
T0IF Bit .......................................................... 10, 18, 29
B
Interrupt Sources ......................................................... 21, 28
Banking, Data Memory .................................................... 6, 8 Block Diagram ........................................................... 28
Data EEPROM Write Complete ........................... 28, 31
C Interrupt on Change (RB7:RB4) ................ 4, 15, 28, 31
RB0/INT Pin, External ............................... 4, 16, 28, 31
CLKIN Pin ............................................................................ 4 TMR0 Overflow .................................................... 18, 28
CLKOUT Pin ........................................................................ 4
Code Protection ........................................................... 21, 32 Interrupts, Context Saving During ..................................... 29
Configuration Bits ............................................................... 21 Interrupts, Enable Bits
Conversion Considerations ................................................ 59
Data EEPROM Write Complete Enable
D (EEIE Bit) ............................................................. 10, 29
Global Interrupt Enable (GIE Bit) ............................... 10
Data EEPROM Memory ..................................................... 19 Interrupt on Change (RB7:RB4) Enable
EEADR Register .................................................... 7, 24 (RBIE Bit) ................................................................... 10
EECON1 Register ............................................ 7, 19, 24 RB0/INT Enable (INTE Bit) ........................................ 10
EECON2 Register ............................................ 7, 19, 24 TMR0 Overflow Enable (T0IE Bit) ............................. 10
EEDATA Register .................................................. 7, 24 Interrupts, Flag Bits ........................................................... 28
Write Complete Enable (EEIE Bit) ....................... 10, 29 Data EEPROM Write Complete Flag
Write Complete Flag (EEIF Bit) ............................ 19, 29 (EEIF Bit) ............................................................. 19, 29
Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ....... 10
Data EEPROM Write Complete ......................................... 29 RB0/INT Flag (INTF Bit) ............................................ 10
Data Memory ....................................................................... 6 TMR0 Overflow Flag (T0IF Bit) .................................. 10
Bank Select (RP0 Bit) .............................................. 6, 8 K
Banking ........................................................................ 6
DC & AC Characteristics Graphs/Tables ........................... 53 KeeLoq Evaluation and Programming Tools .................. 38
DC Characteristics ........................................... 43, 44, 45, 46
Development Support ........................................................ 35 M
Development Tools ............................................................ 35
Master Clear (MCLR)
E MCLR Pin .....................................................................4
MCLR Reset, Normal Operation ................................ 23
EECON1 Register .............................................................. 19 MCLR Reset, SLEEP .......................................... 23, 31
EEIF Bit ................................................................ 19, 29
RD Bit ......................................................................... 19 Memory Organization ...........................................................5
WR Bit ........................................................................ 19 Data EEPROM Memory ............................................ 19
WREN Bit ................................................................... 19 Data Memory ................................................................6
WRERR Bit ................................................................ 19 Program Memory ..........................................................5
Electrical Characteristics .................................................... 41 Migration from Baseline to Midrange Devices ................... 62
Endurance ............................................................................ 1 MPLAB Integrated Development Environment
Errata ................................................................................... 2 Software ............................................................................ 37
External Power-on Reset Circuit ........................................ 25
O
F
On-Line Support ................................................................ 65
Firmware Instructions ......................................................... 33 OPCODE Field Descriptions ............................................. 33
ftp site ................................................................................ 65 OPTION_REG Register ................................. 7, 9, 16, 18, 24
Fuzzy Logic Dev. System (fuzzyTECH-MP) ................... 37
INTEDG Bit ............................................................ 9, 29
I PS2:PS0 Bits ......................................................... 9, 17
PSA Bit .................................................................. 9, 17
I/O Ports ............................................................................. 13 RBPU Bit ......................................................................9
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 35 T0CS Bit .......................................................................9
ID Locations ................................................................. 21, 32 T0SE Bit .......................................................................9
In-Circuit Serial Programming (ICSP) .......................... 21, 32 OSC1 Pin ..............................................................................4
Indirect Addressing ............................................................ 11 OSC2 Pin ..............................................................................4
Oscillator Configuration ............................................... 21, 22
FSR Register ............................................... 6, 7, 11, 24 HS ........................................................................ 22, 28
INDF Register ........................................................ 7, 24 LP ........................................................................ 22, 28
Instruction Format .............................................................. 33 RC ................................................................. 22, 23, 28
Instruction Set .................................................................... 33 Selection (FOSC1:FOSC0 Bits) ................................ 21
Summary Table .......................................................... 34 XT ........................................................................ 22, 28
INT Interrupt (RB0/INT) ...................................................... 29
1998 Microchip Technology Inc. Preliminary DS35007A-page 63
PIC16F84A S
P Saving W Register and STATUS in RAM .......................... 29
SEEVAL Evaluation and Programming System .............. 37
Packaging .......................................................................... 55 SLEEP ............................................................. 21, 23, 29, 31
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 36 Software Simulator (MPLAB-SIM) ..................................... 37
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 36 Special Features of the CPU ............................................. 21
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 36 Special Function Registers .............................................. 6, 7
PICSTART Plus Entry Level Development System ........ 35 Speed, Operating ..................................................... 1, 22, 49
Pinout Descriptions .............................................................. 4 Stack .................................................................................. 11
Pointer, FSR ....................................................................... 11 STATUS Register ................................................ 7, 8, 24, 29
PORTA ........................................................................... 4, 13
C Bit ....................................................................... 8, 34
Initializing ................................................................... 13 DC Bit .................................................................... 8, 34
PORTA Register ........................................ 7, 13, 14, 24 PD Bit ............................................ 8, 23, 28, 31, 32, 34
RA3:RA0 Block Diagram ............................................ 13 Reset Conditions ....................................................... 24
RA4 Block Diagram .................................................... 14 RP0 Bit .................................................................... 6, 8
RA4/T0CKI Pin ................................................. 4, 13, 17 TO Bit ...................................... 8, 23, 28, 30, 31, 32, 34
TRISA Register .................................... 7, 13, 14, 18, 24 Z Bit ....................................................................... 8, 34
PORTB ........................................................................... 4, 15
Initializing ................................................................... 15 T
PORTB Register ........................................ 7, 15, 16, 24
Pull-up Enable (RBPU Bit) ........................................... 9 Time-out (TO) Bit. See Power-on Reset (POR)
RB0/INT Edge Select (INTEDG Bit) ............................. 9 Timer0 ................................................................................ 17
RB0/INT Pin, External ...................................... 4, 16, 29
RB3:RB0 Block Diagram ............................................ 15 Block Diagram ........................................................... 17
RB7:RB4 Block Diagram ............................................ 15 Clock Source Edge Select (T0SE Bit) ......................... 9
RB7:RB4 Interrupt on Change ......................... 4, 15, 29 Clock Source Select (T0CS Bit) .................................. 9
RB7:RB4 Interrupt on Change Enable (RBIE Bit) ...... 10 Overflow Enable (T0IE Bit) .................................. 10, 29
RB7:RB4 Interrupt on Change Flag (RBIF Bit) .... 10, 15 Overflow Flag (T0IF Bit) ................................ 10, 18, 29
TRISB Register .......................................... 7, 15, 16, 24 Overflow Interrupt ................................................ 18, 29
Power-on Reset (POR) .......................................... 21, 23, 25 RA4/T0CKI Pin, External Clock ................................. 17
Oscillator Start-up Timer (OST) ........................... 21, 25 TMR0 Register ................................................ 7, 18, 24
PD Bit ............................................. 8, 23, 28, 31, 32, 34 Timing Diagrams
Power-up Timer (PWRT) ..................................... 21, 25 Diagrams and Specifications ..................................... 49
PWRT Enable (PWRTE Bit) ....................................... 21 Time-out Sequence on Power-up ........................ 26, 27
Time-out Sequence .................................................... 28
Time-out Sequence on Power-up ........................ 26, 27 W
TO Bit ....................................... 8, 23, 28, 30, 31, 32, 34
Prescaler ............................................................................ 17 W Register ................................................................... 24, 29
Assignment (PSA Bit) ............................................ 9, 17 Wake-up from SLEEP ................................ 21, 25, 28, 29, 31
Block Diagram ............................................................ 18
Rate Select (PS2:PS0 Bits) ................................... 9, 17 Interrupts ............................................................. 31, 32
Switching Prescaler Assignment ................................ 18 MCLR Reset .............................................................. 31
PRO MATE II Universal Programmer .............................. 35 WDT Reset ................................................................ 31
Product Identification System ............................................. 67 Watchdog Timer (WDT) ............................................... 21, 30
Program Counter ................................................................ 11 Block Diagram ........................................................... 30
PCL Register .................................................... 7, 11, 24 Enable (WDTE Bit) .................................................... 21
PCLATH Register ............................................ 7, 11, 24 Programming Considerations .................................... 30
Reset Conditions ........................................................ 24 RC Oscillator ............................................................. 30
Program Memory ................................................................. 5 Time-out Period ......................................................... 30
General Purpose Registers .......................................... 6 WDT Reset, Normal Operation .................................. 23
Interrupt Vector ...................................................... 5, 29 WDT Reset, SLEEP ............................................ 23, 31
Reset Vector ................................................................ 5 WWW, On-Line Support ................................................ 2, 65
Special Function Registers ...................................... 6, 7
Programming, Device Instructions ..................................... 33
R
RAM. See Data Memory
Reader Response .............................................................. 66
Register File ......................................................................... 6
Reset ............................................................................ 21, 23
Block Diagram ............................................................ 23
Reset Conditions for All Registers ............................. 24
Reset Conditions for Program Counter ...................... 24
Reset Conditions for STATUS Register ..................... 24
WDT Reset. See Watchdog Timer (WDT)
Revision History ................................................................. 59
DS35007A-page 64 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
ON-LINE SUPPORT Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
Microchip provides on-line support on the Microchip system users a listing of the latest versions of all of
World Wide Web (WWW) site. Microchip's development systems software products.
Plus, this line provides information on how customers
The web site is used by Microchip as a means to make can receive any currently available upgrade kits.The
files and information easily available to customers. To Hot Line Numbers are:
view the site, the user must have access to the Internet 1-800-755-2345 for U.S. and most of Canada, and
and a web browser, such as Netscape or Microsoft 1-602-786-7302 for the rest of the world.
Explorer. Files are also available for FTP download
from our FTP site. 980106
Connecting to the Microchip InternetWeb Site Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks of
The Microchip web site is available by using your Microchip Technology Incorporated in the U.S.A. and other
favorite Internet browser to attach to: countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are
trademarks and SQTP is a service mark of Microchip in
www.microchip.com the U.S.A.
All other trademarks mentioned herein are the property of
The file transfer site is available by using an FTP ser- their respective companies.
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
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Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
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available for consideration is:
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Links to other useful web sites related to
Microchip Products
Conferences for products, Development Sys-
tems, technical information and more
Listing of seminars and events
1998 Microchip Technology Inc. Preliminary DS35007A-page 65
PIC16F84A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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Device: PIC16F84A Literature Number: DS35007A
Questions:
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3. Do you find the organization of this data sheet easy to follow? If not, why?
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DS35007A-page66 Preliminary 1998 Microchip Technology Inc.
PIC16F84A
PIC16F84A PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -XX X /XX XXX Examples:
Device Frequency Temperature Package Pattern a) PIC16F84A -04/P 301 = Commercial
temp., PDIP package, 4 MHz, normal
Range Range VDD limits, QTP pattern #301.
Device PIC16F84A(1), PIC16F84AT(2) b) PIC16LF84A - 04I/SO = Industrial temp.,
PIC16LF84A(1), PIC16LF84AT(2) SOIC package, 200 kHz, Extended VDD
Frequency limits.
Range 04 = 4 MHz
Temperature c) PIC16F84A - 20I/P = Industrial temp.,
Range 20 = 20 MHz PDIP package, 20MHz, normal VDD lim-
its.
blank = 0C to +70C (Commercial)
I = -40C to +85C (Industrial)
Package P = PDIP
Pattern
SO = SOIC (Gull Wing, 300 mil body) Note 1: F = Standard VDD range
2: LF = Extended VDD range
SS = SSOP T = in tape and reel - SOIC, SSOP
3-digit Pattern Code for QTP, ROM (blank otherwise) packages only.
1998 Microchip Technology Inc. Preliminary DS35007A-page 67
WORLDWIDE SALES AND SERVICE
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All rights reserved. 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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1999 Microchip Technology Inc.
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