PIC16F8X
18-pin Flash/EEPROM 8-Bit Microcontrollers
Devices Included in this Data Sheet: Pin Diagrams
• PIC16F83 PDIP, SOIC
• PIC16F84
• PIC16CR83 RA2 1 18 RA1
• PIC16CR84 RA3 2 17 RA0
• Extended voltage range devices available RA4/T0CKI 3 PIC16CR8X PIC16F8X 16 OSC1/CLKIN
(PIC16LF8X, PIC16LCR8X) MCLR 4 15 OSC2/CLKOUT
High Performance RISC CPU Features: VSS 5 14 VDD
RB0/INT 6 13 RB7
• Only 35 single word instructions to learn RB1 7 12 RB6
• All instructions single cycle except for program RB2 8 11 RB5
branches which are two-cycle RB3 9 10 RB4
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Program Data Data Max. Special Microcontroller Features:
Device Memory RAM EEPROM Freq • In-Circuit Serial Programming (ICSP™) - via two
(words) (bytes) (bytes) (MHz) pins (ROM devices support only Data EEPROM
PIC16F83 512 Flash 36 64 10 programming)
PIC16F84 1 K Flash 68 64 10 • Power-on Reset (POR)
PIC16CR83 512 ROM 36 64 10 • Power-up Timer (PWRT)
PIC16CR84 1 K ROM 68 64 10 • Oscillator Start-up Timer (OST)
• 14-bit wide instructions • Watchdog Timer (WDT) with its own on-chip RC
• 8-bit wide data path oscillator for reliable operation
• 15 special function hardware registers • Code-protection
• Eight-level deep hardware stack • Power saving SLEEP mode
• Direct, indirect and relative addressing modes • Selectable oscillator options
• Four interrupt sources: CMOS Flash/EEPROM Technology:
- External RB0/INT pin • Low-power, high-speed technology
- TMR0 timer overflow • Fully static design
- PORTB interrupt on change • Wide operating voltage range:
- Data EEPROM write complete
• 1000 erase/write cycles Flash program memory - Commercial: 2.0V to 6.0V
• 10,000,000 erase/write cycles EEPROM data mem- - Industrial: 2.0V to 6.0V
ory • Low power consumption:
• EEPROM Data Retention > 40 years - < 2 mA typical @ 5V, 4 MHz
- 15 A typical @ 2V, 32 kHz
Peripheral Features: - < 1 A typical standby current @ 2V
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
1996-2013 Microchip Technology Inc. DS30430D-page 1
PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: What’s New In This Data Sheet ................................................................................................................................. 114
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.
DS30430D-page 2 1996-2013 Microchip Technology Inc.
PIC16F8X
1.0 GENERAL DESCRIPTION Table 1-1 lists the features of the PIC16F8X. A simpli-
The PIC16F8X is a group in the PIC16CXX family of fied block diagram of the PIC16F8X is shown in
low-cost, high-performance, CMOS, fully-static, 8-bit Figure 3-1.
microcontrollers. This group contains the following The PIC16F8X fits perfectly in applications ranging
devices: from high speed automotive and appliance motor
• PIC16F83 control to low-power remote sensors, electronic locks,
• PIC16F84 security devices and smart cards. The Flash/EEPROM
technology makes customization of application
• PIC16CR83 programs (transmitter codes, motor speeds, receiver
• PIC16CR84 frequencies, security codes, etc.) extremely fast and
All PIC® microcontrollers employ an advanced RISC convenient. The small footprint packages make this
architecture. PIC16F8X devices have enhanced core microcontroller series perfect for all applications with
features, eight-level deep stack, and multiple internal space limitations. Low-cost, low-power, high
and external interrupt sources. The separate performance, ease-of-use and I/O flexibility make the
instruction and data buses of the Harvard architecture PIC16F8X very versatile even in areas where no
allow a 14-bit wide instruction word with a separate microcontroller use has been considered before
8-bit wide data bus. The two stage instruction pipeline (e.g., timer functions; serial communication; capture,
allows all instructions to execute in a single cycle, compare and PWM functions; and co-processor
except for program branches (which require two applications).
cycles). A total of 35 instructions (reduced instruction The serial in-system programming feature (via two
set) are available. Additionally, a large register set is pins) offers flexibility of customizing the product after
used to achieve a very high performance level. complete assembly and testing. This feature can be
PIC16F8X microcontrollers typically achieve a 2:1 code used to serialize a product, store calibration data, or
compression and up to a 4:1 speed improvement (at 20 program the device with the current firmware before
MHz) over other 8-bit microcontrollers in their class. shipping.
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of 1.1 Family and Upward Compatibility
Data EEPROM memory, and 13 I/O pins. A timer/coun-
ter is also available. Those users familiar with the PIC16C5X family of
The PIC16CXX family has special features to reduce microcontrollers will realize that this is an enhanced
external components, thus reducing cost, enhancing version of the PIC16C5X architecture. Please refer to
system reliability and reducing power consumption. Appendix A for a detailed list of enhancements. Code
There are four oscillator options, of which the single pin written for PIC16C5X devices can be easily ported to
RC oscillator provides a low-cost solution, the LP PIC16F8X devices (Appendix B).
oscillator minimizes power consumption, XT is a 1.2 Development Support
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving. The PIC16CXX family is supported by a full-featured
The user can wake the chip from sleep through several macro assembler, a software simulator, an in-circuit
external and internal interrupts and resets. emulator, a low-cost development programmer and a
A highly reliable Watchdog Timer with its own on-chip full-featured programmer. A “C” compiler and fuzzy
RC oscillator provides protection against software lock- logic support tools are also available.
up.
The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).
1996-2013 Microchip Technology Inc. DS30430D-page 3
PIC16F8X
TABLE 1-1 PIC16F8X FAMILY OF DEVICES
PIC16F83 PIC16CR83 PIC16F84 PIC16CR84
Clock Maximum Frequency 10 10 10 10
of Operation (MHz)
Flash Program Memory 512 — 1K —
EEPROM Program Memory — — — —
Memory ROM Program Memory — 512 — 1K
Data Memory (bytes) 36 36 68 68
Data EEPROM (bytes) 64 64 64 64
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Interrupt Sources 4 4 4 4
I/O Pins 13 13 13 13
Features Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP,
SOIC SOIC SOIC SOIC
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30430D-page 4 1996-2013 Microchip Technology Inc.
PIC16F8X
2.0 PIC16F8X DEVICE VARIETIES 2.3 Serialized Quick-Turnaround-
A variety of frequency ranges and packaging options Production (SQTPSM ) Devices
are available. Depending on application and production Microchip offers the unique programming service
requirements the proper device option can be selected where a few user-defined locations in each device are
using the information in this section. When placing programmed with different serial numbers. The serial
orders, please use the “PIC16F8X Product numbers may be random, pseudo-random
Identification System” at the back of this data sheet to or sequential.
specify the correct part number. Serial programming allows each device to have a
There are four device “types” as indicated in the device unique number which can serve as an entry-code,
number. password or ID number.
1. F, as in PIC16F84. These devices have Flash For information on submitting a SQTP code, please
program memory and operate over the standard contact your Microchip Regional Sales Office.
voltage range.
2. LF, as in PIC16LF84. These devices have Flash 2.4 ROM Devices
program memory and operate over an extended Some of Microchip’s devices have a corresponding
voltage range. device where the program memory is a ROM. These
3. CR, as in PIC16CR83. These devices have devices give a cost savings over Microchip’s traditional
ROM program memory and operate over the user programmed devices (EPROM, EEPROM).
standard voltage range.
4. LCR, as in PIC16LCR84. These devices have ROM devices (PIC16CR8X) do not allow serialization
ROM program memory and operate over an information in the program memory space. The user
extended voltage range. may program this information into the Data EEPROM.
When discussing memory maps and other architectural For information on submitting a ROM code, please
features, the use of F and CR also implies the LF and contact your Microchip Regional Sales Office.
LCR versions.
2.1 Flash Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed in-
circuit, or by device programmers, such as Microchip's
PICSTART® Plus or PRO MATE® II programmers.
2.2 Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices have all Flash
locations and configuration options already pro-
grammed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available.
For information on submitting a QTP code, please
contact your Microchip Regional Sales Office.
1996-2013 Microchip Technology Inc. DS30430D-page 5
PIC16F8X
NOTES:
DS30430D-page 6 1996-2013 Microchip Technology Inc.
PIC16F8X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CXX uses a Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC16CXX opcodes are 14-bits wide, enabling single
word instructions. The full 14-bit wide program memory
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions exe-
cute in a single cycle except for program branches.
The PIC16F83 and PIC16CR83 address 512 x 14 of
program memory, and the PIC16F84 and PIC16CR84
address 1K x 14 program memory. All program mem-
ory is internal.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. An orthogonal (symmetrical)
instruction set makes it possible to carry out any oper-
ation on any register using any addressing mode. This
symmetrical nature and lack of ‘special optimal
situations’ make programming with the PIC16CXX
simple yet efficient. In addition, the learning curve is
reduced significantly.
1996-2013 Microchip Technology Inc. DS30430D-page 7
PIC16F8X
PIC16CXX devices contain an 8-bit ALU and working The W register is an 8-bit working register used for ALU
register. The ALU is a general purpose arithmetic unit. operations. It is not an addressable register.
It performs arithmetic and Boolean functions between Depending on the instruction executed, the ALU may
data in the working register and any register file. affect the values of the Carry (C), Digit Carry (DC), and
The ALU is 8-bits wide and capable of addition, Zero (Z) bits in the STATUS register. The C and DC bits
subtraction, shift and logical operations. Unless operate as a borrow and digit borrow out bit,
otherwise mentioned, arithmetic operations are two's respectively, in subtraction. See the SUBLW and SUBWF
complement in nature. In two-operand instructions, instructions for examples.
typically one operand is the working register A simplified block diagram for the PIC16F8X is shown
(W register), and the other operand is a file register or in Figure 3-1, its corresponding pin description is
an immediate constant. In single operand instructions, shown in Table 3-1.
the operand is either the W register or a file register.
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
13 Data Bus 8
Flash/ROM Program Counter EEPROM Data Memory
Program
Memory
PIC16F83/CR83 RAM
512 x 14 File Registers EEPROM
PIC16F84/CR84 8 Level Stack PIC16F83/CR83 EEDATA Data Memory
1K x 14 (13-bit) 36 x 8 64 x 8
PIC16F84/CR84
Program 68 x 8
Bus 14 7 RAM Addr
EEADR
Instruction reg Addr Mux
5 Direct Addr 7 Indirect TMR0
Addr
FSR reg
RA4/T0CKI
STATUS reg
8
Power-up MUX
Timer 8 I/O Ports
Instruction Oscillator
Decode & Start-up Timer ALU
Control
Power-on RA3:RA0
Reset
Timing Watchdog W reg RB7:RB1
Generation Timer
RB0/INT
OSC2/CLKOUT MCLR VDD, VSS
OSC1/CLKIN
DS30430D-page 8 1996-2013 Microchip Technology Inc.
PIC16F8X
TABLE 3-1 PIC16F8X PINOUT DESCRIPTION
Pin Name DIP SOIC I/O/P Buffer Description
No. No. Type Type
OSC1/CLKIN 16 16 I ST/CMOS (3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0 17 17 I/O TTL
RA1 18 18 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0 timer/
counter. Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT 6 6 I/O TTL/ST (1) RB0/INT can also be selected as an external interrupt pin.
RB1 7 7 I/O TTL
RB2 8 8 I/O TTL
RB3 9 9 I/O TTL
RB4 10 10 I/O TTL Interrupt on change pin.
RB5 11 11 I/O TTL Interrupt on change pin.
RB6 12 12 I/O TTL/ST (2) Interrupt on change pin. Serial programming clock.
RB7 13 13 I/O TTL/ST (2) Interrupt on change pin. Serial programming data.
VSS 5 5 P — Ground reference for logic and I/O pins.
VDD 14 14 P — Positive supply for logic and I/O pins.
Legend: I= input O = output I/O = Input/Output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1996-2013 Microchip Technology Inc. DS30430D-page 9
PIC16F8X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1,
four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are
clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle
program counter (PC) is incremented every Q1, the while decode and execute takes another instruction
instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction
latched into the instruction register in Q4. The effectively executes in one cycle. If an instruction
instruction is decoded and executed during the causes the program counter to change (e.g., GOTO)
following Q1 through Q4. The clocks and instruction then two cycles are required to complete the instruction
execution flow is shown in Figure 3-2. (Example 3-1).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 phase
clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30430D-page 10 1996-2013 Microchip Technology Inc.
PIC16F8X
4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP
There are two memory blocks in the PIC16F8X. These AND STACK - PIC16F83/CR83
are the program memory and the data memory. Each PC
block has its own bus, so that access to each block can CALL, RETURN 13
occur during the same oscillator cycle. RETFIE, RETLW
The data memory can further be broken down into the Stack Level 1
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that Stack Level 8
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the Reset Vector 0000h
section discussing each individual peripheral module. User Memory Peripheral Interrupt Vector 0004h
The data memory area also contains the data Space
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range 1FFh
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1 Program Memory Organization
The PIC16FXX has a 13-bit program counter capable 1FFFh
of addressing an 8K x 14 program memory space. For
the PIC16F83 and PIC16CR83, the first 512 x 14
(0000h-01FFh) are physically implemented FIGURE 4-2: PROGRAM MEMORY MAP
(Figure 4-1). For the PIC16F84 and PIC16CR84, the AND STACK - PIC16F84/CR84
first 1K x 14 (0000h-03FFh) are physically imple-
mented (Figure 4-2). Accessing a location above the PC
physically implemented address will cause a wrap- CALL, RETURN 13
around. For example, for the PIC16F84 locations 20h, RETFIE, RETLW
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h Stack Level 1
will be the same instruction.
The reset vector is at 0000h and the interrupt vector is Stack Level 8
at 0004h. Reset Vector 0000h
Peripheral Interrupt Vector 0004h
User Memory Space
3FFh
1FFFh
1996-2013 Microchip Technology Inc. DS30430D-page 11
PIC16F8X
4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE
The data memory is partitioned into two areas. The first All devices have some amount of General Purpose
is the Special Function Registers (SFR) area, while the Register (GPR) area. Each GPR is 8 bits wide and is
second is the General Purpose Registers (GPR) area. accessed either directly or indirectly through the FSR
The SFRs control the operation of the device. (Section 4.5).
Portions of data memory are banked. This is for both The GPR addresses in bank 1 are mapped to
the SFR area and the GPR area. The GPR area is addresses in bank 0. As an example, addressing loca-
banked to allow greater than 116 bytes of general tion 0Ch or 8Ch will access the same GPR.
purpose RAM. The banked areas of the SFR are for the 4.2.2 SPECIAL FUNCTION REGISTERS
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection. The Special Function Registers (Figure 4-1, Figure 4-2
These control bits are located in the STATUS Register. and Table 4-1) are used by the CPU and Peripheral
Figure 4-1 and Figure 4-2 show the data memory map functions to control the device operation. These
organization. registers are static RAM.
Instructions MOVWF and MOVF can move values from The special function registers can be classified into two
the W register to any location in the register file (“F”), sets, core and peripheral. Those associated with the
and vice-versa. core functions are described in this section. Those
The entire data memory can be accessed either related to the operation of the peripheral features are
directly using the absolute address of each register file described in the section for that specific feature.
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
DS30430D-page 12 1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 4-1: REGISTER FILE MAP - FIGURE 4-2: REGISTER FILE MAP -
PIC16F83/CR83 PIC16F84/CR84
File Address File Address File Address File Address
00h Indirect addr.(1) Indirect addr.(1) 80h 00h Indirect addr.(1) Indirect addr.(1) 80h
01h TMR0 OPTION 81h 01h TMR0 OPTION 81h
02h PCL PCL 82h 02h PCL PCL 82h
03h STATUS STATUS 83h 03h STATUS STATUS 83h
04h FSR FSR 84h 04h FSR FSR 84h
05h PORTA TRISA 85h 05h PORTA TRISA 85h
06h PORTB TRISB 86h 06h PORTB TRISB 86h
07h 87h 07h 87h
08h EEDATA EECON1 88h 08h EEDATA EECON1 88h
09h EEADR EECON2(1) 89h 09h EEADR EECON2(1) 89h
0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh
0Ch 8Ch 0Ch 8Ch
36
General Mapped
Purpose (accesses)
registers in Bank 0 68
(SRAM) General Mapped
Purpose (accesses)
2Fh AFh registers in Bank 0
30h B0h (SRAM)
4Fh CFh
50h D0h
7Fh FFh 7Fh FFh
Bank 0 Bank 1 Bank 0 Bank 1
Unimplemented data memory location; read as '0'. Unimplemented data memory location; read as '0'.
Note 1: Not a physical register. Note 1: Not a physical register.
1996-2013 Microchip Technology Inc. DS30430D-page 13
PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset (Note3)
Bank 0
00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000
03h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
07h Unimplemented location, read as '0' ---- ---- ---- ----
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000
83h STATUS (2) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
85h TRISA — — — PORTA data direction register ---1 1111 ---1 1111
86h TRISB PORTB data direction register 1111 1111 1111 1111
87h Unimplemented location, read as '0' ---- ---- ---- ----
88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC is never transferred
to PCLATH.
2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430D-page 14 1996-2013 Microchip Technology Inc.
PIC16F8X
4.2.2.1 STATUS REGISTER Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 9-2)
The STATUS register contains the arithmetic status of because these instructions do not affect any status bit.
the ALU, the RESET status and the bank select bit for
data memory. Note 1: The IRP and RP1 bits (STATUS) are
As with any register, the STATUS register can be the not used by the PIC16F8X and should be
destination for any instruction. If the STATUS register is programmed as cleared. Use of these bits
the destination for an instruction that affects the Z, DC as general purpose R/W bits is NOT
or C bits, then the write to these three bits is disabled. recommended, since this may affect
These bits are set or cleared according to device logic. upward compatibility with future products.
Furthermore, the TO and PD bits are not writable. Note 2: The C and DC bits operate as a borrow
Therefore, the result of an instruction with the STATUS and digit borrow out bit, respectively, in
register as destination may be different than intended. subtraction. See the SUBLW and SUBWF
For example, CLRF STATUS will clear the upper-three instructions for examples.
bits and set the Z bit. This leaves the STATUS register Note 3: When the STATUS register is the
as 000u u1uu (where u = unchanged). destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
FIGURE 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low
order bit of the source register.
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PIC16F8X
4.2.2.2 OPTION_REG REGISTER
Note: When the prescaler is assigned to
The OPTION_REG register is a readable and writable the WDT (PSA = '1'), TMR0 has a 1:1
register which contains various control bits to configure prescaler assignment.
the TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-1: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
bit7 bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled (by individual port latch values)
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
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PIC16F8X
4.2.2.3 INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
The INTCON register is a readable and writable condition occurs regardless of the state of
register which contains the various enable bits for all its corresponding enable bit or the global
interrupt sources. enable bit, GIE (INTCON).
FIGURE 4-1: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
bit7 bit0 W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
Note: For the operation of the interrupt structure, please refer to Section 8.5.
bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1: INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
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4.3 Program Counter: PCL and PCLATH manipulation of the PCLATH is not required for
the return instructions (which “pops” the PC from the
The Program Counter (PC) is 13-bits wide. The low stack).
byte is the PCL register, which is a readable and
writable register. The high byte of the PC (PC) is Note: The PIC16F8X ignores the PCLATH
not directly readable nor writable and comes from the bits, which are used for program memory
PCLATH register. The PCLATH (PC latch high) register pages 1, 2 and 3 (0800h - 1FFFh). The
is a holding register for PC. The contents of use of PCLATH as general purpose
PCLATH are transferred to the upper byte of the R/W bits is not recommended since this
program counter when the PC is loaded with a new may affect upward compatibility with
value. This occurs during a CALL, GOTO or a write to future products.
PCL. The high bits of PC are loaded from PCLATH as 4.4 Stack
shown in Figure 4-1.
The PIC16FXX has an 8 deep x 13-bit wide hardware
FIGURE 4-1: LOADING OF PC IN stack (Figure 4-1). The stack space is not part of either
DIFFERENT SITUATIONS program or data space and the stack pointer is not
PCH PCL readable or writable.
12 8 7 0 The entire 13-bit PC is “pushed” onto the stack when a
PC INST with PCL CALL instruction is executed or an interrupt is acknowl-
as dest
PCLATH 8 edged. The stack is “popped” in the event of a
5 ALU result RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a push or a pop operation.
PCLATH
Note: There are no instruction mnemonics
PCH PCL called push or pop. These are actions that
12 11 10 8 7 0 occur from the execution of the CALL,
PC GOTO, CALL RETURN, RETLW, and RETFIE instruc-
PCLATH 11 tions, or the vectoring to an interrupt
2 Opcode address.
PCLATH The stack operates as a circular buffer. That is, after the
stack has been pushed eight times, the ninth push over-
writes the value that was stored from the first push. The
4.3.1 COMPUTED GOTO tenth push overwrites the second push (and so on).
A computed GOTO is accomplished by adding an offset If the stack is effectively popped nine times, the PC
to the program counter (ADDWF PCL). When doing a value is the same as the value from the first pop.
table read using a computed GOTO method, care should Note: There are no status bits to indicate stack
be exercised if the table location crosses a PCL memory overflow or stack underflow conditions.
boundary (each 256 word block). Refer to the application
note “Implementing a Table Read” (AN556).
4.3.2 PROGRAM MEMORY PAGING
The PIC16F83 and PIC16CR83 have 512 words of pro-
gram memory. The PIC16F84 and PIC16CR84 have
1K of program memory. The CALL and GOTO instruc-
tions have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. For future PIC16F8X program memory
expansion, there must be another two bits to specify
the program memory page. These paging bits come
from the PCLATH bits (Figure 4-1). When doing a
CALL or a GOTO instruction, the user must ensure that
these page bits (PCLATH) are programmed to
the desired program memory page. If a CALL instruc-
tion (or interrupt) is executed, the entire 13-bit PC is
“pushed” onto the stack (see next section). Therefore,
DS30430D-page 18 1996-2013 Microchip Technology Inc.
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4.5 Indirect Addressing; INDF and FSR A simple program to clear RAM locations 20h-2Fh
Registers using indirect addressing is shown in Example 4-2.
The INDF register is not a physical register. Address- EXAMPLE 4-2: HOW TO CLEAR RAM
ing INDF actually addresses the register whose USING INDIRECT
address is contained in the FSR register (FSR is a ADDRESSING
pointer). This is indirect addressing. movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
EXAMPLE 4-1: INDIRECT ADDRESSING NEXT clrf INDF ;clear INDF register
• Register file 05 contains the value 10h incf FSR ;inc pointer
• Register file 06 contains the value 0Ah btfss FSR,4 ;all done?
• Load the value 05 into the FSR register goto NEXT ;NO, clear next
• A read of the INDF register will return the value of CONTINUE
10h : ;YES, continue
• Increment the value of the FSR register by one An effective 9-bit address is obtained by concatenating
(FSR = 06) the 8-bit FSR register and the IRP bit (STATUS), as
• A read of the INDF register now will return the shown in Figure 4-1. However, IRP is not used in the
value of 0Ah. PIC16F8X.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 4-1: DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
RP1 RP0 6 from opcode 0 IRP 7 (FSR) 0
bank select location select bank select location select
00 01 10 11
00h 00h
not used not used
0Bh
0Ch
Data 2Fh (1) Addresses
Memory (3) 30h (1) map back
to Bank 0
4Fh (2)
50h (2)
7Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: PIC16F83 and PIC16CR83 devices.
2: PIC16F84 and PIC16CR84 devices
3: For memory map detail see Figure 4-1.
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PIC16F8X
NOTES:
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5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA
The PIC16F8X has two ports, PORTA and PORTB. CLRF PORTA ; Initialize PORTA by
; setting output
Some port pins are multiplexed with an alternate func- ; data latches
tion for other features on the device. BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Value used to
5.1 PORTA and TRISA Registers ; initialize data
; direction
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger MOVWF TRISA ; Set RA as inputs
input and an open drain output. All other RA port pins ; RA4 as outputs
have TTL input levels and full CMOS output drivers. All ; TRISA are always
pins have data direction bits (TRIS registers) which can ; read as '0'.
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding FIGURE 5-2: BLOCK DIAGRAM OF PIN RA4
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit Data
(=0) will make the corresponding PORTA pin an output, bus D Q
i.e., put the contents of the output latch on the selected WR
pin. PORT CK Q
N RA4 pin
Reading the PORTA register reads the status of the pins Data Latch
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write VSS
to a port implies that the port pins are first read, then this D Q
value is modified and written to the port data latch. WR
TRIS CK Q
The RA4 pin is multiplexed with the TMR0 clock input. Schmitt
TRIS Latch Trigger
FIGURE 5-1: BLOCK DIAGRAM OF PINS input
buffer
RA3:RA0
Data RD TRIS
bus
D Q
VDD Q D
WR
Port CK Q
P EENN
RD PORT
Data Latch
N I/O pin TMR0 clock input
D Q
WR VSS Note: I/O pin has protection diodes to VSS only.
TRIS CK Q
TRIS Latch TTL
input
buffer
RD TRIS
Q D
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
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PIC16F8X
TABLE 5-1 PORTA FUNCTIONS
Name Bit0 Buffer Type Function
RA0 bit0 TTL Input/output
RA1 bit1 TTL Input/output
RA2 bit2 TTL Input/output
RA3 bit3 TTL Input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset
05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'
DS30430D-page 22 1996-2013 Microchip Technology Inc.
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5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
PORTB is an 8-bit wide bi-directional port. The interrupt in the following manner:
corresponding data direction register is TRISB. A '1' on a) Read (or write) PORTB. This will end the mis-
any bit in the TRISB register puts the corresponding match condition.
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output b) Clear flag bit RBIF.
latch on the selected pin(s). A mismatch condition will continue to set the RBIF bit.
Each of the PORTB pins have a weak internal pull-up. Reading PORTB will end the mismatch condition, and
A single control bit can turn on all the pull-ups. This is allow the RBIF bit to be cleared.
done by clearing the RBPU (OPTION_REG) bit. This interrupt on mismatch feature, together with
The weak pull-up is automatically turned off when the software configurable pull-ups on these four pins allow
port pin is configured as an output. The pull-ups are easy interface to a key pad and make it possible for
disabled on a Power-on Reset. wake-up on key-depression (see AN552 in the
Four of PORTB’s pins, RB7:RB4, have an interrupt on Embedded Control Handbook).
change feature. Only pins configured as inputs can Note 1: For a change on the I/O pin to be
cause this interrupt to occur (i.e., any RB7:RB4 pin recognized, the pulse width must be at
configured as an output is excluded from the interrupt least TCY (4/fOSC) wide.
on change comparison). The pins value in input mode The interrupt on change feature is recommended for
are compared with the old value latched on the last wake-up on key depression operation and operations
read of PORTB. The “mismatch” outputs of the pins are where PORTB is only used for the interrupt on change
OR’ed together to generate the RB port feature. Polling of PORTB is not recommended while
change interrupt. using the interrupt on change feature.
FIGURE 5-3: BLOCK DIAGRAM OF PINS FIGURE 5-4: BLOCK DIAGRAM OF PINS
RB7:RB4 RB3:RB0
VDD
VDD RBPU(1) weak
RBPU(1) P pull-up
P weak Data Latch
pull-up Data bus
Data Latch D Q
Data bus D Q I/O
WR Port CK pin(2)
I/O
WR Port pin(2)
CK
TRIS Latch
TRIS Latch D Q TTL
D Q WR TRIS Input
CK Buffer
WR TRIS CK TTL
Input
Buffer
RD TRIS
RD TRIS Latch Q D
Q D RD Port EN
RD Port EN
Set RBIF RB0/INT
Schmitt Trigger RD Port
From other Q D Buffer
RB7:RB4 pins Note 1: TRISB = '1' enables weak pull-up
EN (if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.
1996-2013 Microchip Technology Inc. DS30430D-page 23
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EXAMPLE 5-1: INITIALIZING PORTB
CLRF PORTB ; Initialize PORTB by
; setting output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB as inputs
; RB as outputs
; RB as inputs
TABLE 5-3 PORTB FUNCTIONS
Name Bit Buffer Type I/O Consistency Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger.
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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5.3 I/O Programming Considerations 5.3.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
5.3.1 BI-DIRECTIONAL I/O PORTS
The actual write to an I/O port happens at the end of an
Any instruction which writes, operates internally as a instruction cycle, whereas for reading, the data must be
read followed by a write operation. The BCF and BSF valid at the beginning of the instruction cycle
instructions, for example, read the register into the (Figure 5-5). Therefore, care must be exercised if a
CPU, execute the bit operation and write the result back write followed by a read operation is carried out on the
to the register. Caution must be used when these same I/O port. The sequence of instructions should be
instructions are applied to a port with both inputs and such that the pin voltage stabilizes (load dependent)
outputs defined. For example, a BSF operation on bit5 before the next instruction which causes that file to be
of PORTB will cause all eight bits of PORTB to be read read into the CPU is executed. Otherwise, the previous
into the CPU. Then the BSF operation takes place on state of that pin may be read into the CPU rather than
bit5 and PORTB is written to the output latches. If the new state. When in doubt, it is better to separate
another bit of PORTB is used as a bi-directional I/O pin these instructions with a NOP or another instruction not
(i.e., bit0) and it is defined as an input at this time, the accessing this I/O port.
input signal present on the pin itself would be read into Example 5-1 shows the effect of two sequential
the CPU and rewritten to the data latch of this particular read-modify-write instructions (e.g., BCF, BSF, etc.) on
pin, overwriting the previous content. As long as the pin an I/O port.
stays in the input mode, no problem occurs. However, if
bit0 is switched into output mode later on, the content EXAMPLE 5-1: READ-MODIFY-WRITE
of the data latch is unknown.
Reading the port register, reads the values of the port INSTRUCTIONS ON AN
pins. Writing to the port register writes the value to the I/O PORT
port latch. When using read-modify-write instructions ;Initial PORT settings: PORTB Inputs
(i.e., BCF, BSF, etc.) on a port, the value of the port ; PORTB Outputs
;PORTB have external pull-ups and are
pins is read, the desired operation is done to this value, ;not connected to other circuitry
and this value is then written to the port latch. ;
A pin actively outputting a Low or High should not be ; PORT latch PORT pins
driven from external devices at the same time in order ; ---------- ---------
to change the level on this pin (“wired-or”, “wired-and”). BCF PORTB, 7 ; 01pp ppp 11pp ppp
The resulting high output current may damage the chip. BCF PORTB, 6 ; 10pp ppp 11pp ppp
BSF STATUS, RP0 ;
BCF TRISB, 7 ; 10pp ppp 11pp ppp
BCF TRISB, 6 ; 10pp ppp 10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
FIGURE 5-5: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction MOVWF PORTB MOVF PORTB,W followed by a read from PORTB.
fetched write to NOP NOP
PORTB Note that:
RB7:RB0 data setup time = (0.25TCY - TPD)
Port pin where TCY = instruction cycle
sampled here TPD = propagation delay
Instruction TPD Therefore, at higher clock frequencies,
executed NOP a write followed by a read may be prob-
MOVWF PORTB MOVF PORTB,W lematic.
write to
PORTB
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NOTES:
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6.0 TIMER0 MODULE AND TMR0 edge select bit, T0SE (OPTION_REG). Clearing bit
REGISTER T0SE selects the rising edge. Restrictions on the exter-
nal clock input are discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following The prescaler is shared between the Timer0 Module
features: and the Watchdog Timer. The prescaler assignment is
• 8-bit timer/counter controlled, in software, by control bit PSA
• Readable and writable (OPTION_REG). Clearing bit PSA will assign the
• 8-bit software programmable prescaler prescaler to the Timer0 Module. The prescaler is not
• Internal or external clock select readable or writable. When the prescaler (Section 6.3)
• Interrupt on overflow from FFh to 00h is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
• Edge select for external clock
Timer mode is selected by clearing the T0CS bit 6.1 TMR0 Interrupt
(OPTION_REG). In timer mode, the Timer0 mod- The TMR0 interrupt is generated when the TMR0
ule (Figure 6-1) will increment every instruction cycle register overflows from FFh to 00h. This overflow sets
(without prescaler). If the TMR0 register is written, the the T0IF bit (INTCON). The interrupt can be
increment is inhibited for the following two cycles masked by clearing enable bit T0IE (INTCON). The
(Figure 6-2 and Figure 6-3). The user can work around T0IF bit must be cleared in software by the Timer0
this by writing an adjusted value to the TMR0 register. Module interrupt service routine before re-enabling this
Counter mode is selected by setting the T0CS bit interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
(OPTION_REG). In this mode TMR0 will increment the processor from SLEEP since the timer is shut off
either on every rising or falling edge of pin RA4/T0CKI. during SLEEP.
The incrementing edge is determined by the T0 source
FIGURE 6-1: TMR0 BLOCK DIAGRAM
Data bus
FOSC/4 0 PSout
8
1 Sync with
1 Internal TMR0 register
RA4/T0CKI Programmable 0 clocks PSout
pin Prescaler
T0SE (2 cycle delay)
3 Set bit T0IF
PS2, PS1, PS0 PSA on Overflow
T0CS
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION_REG register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0
Instruction Read TMR0
Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
1996-2013 Microchip Technology Inc. DS30430D-page 27
PIC16F8X
FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 NT0 NT0+1
Instruction Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
Execute executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 6-4: TMR0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
TMR0 timer FEh FFh 00h 01h 02h
4 1 1
T0IF bit
(INTCON)
GIE bit
(INTCON)
INSTRUCTION FLOW Interrupt Latency(2)
PC PC PC +1 PC +1 0004h 0005h
Instruction Inst (PC) Inst (PC+1)
fetched Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30430D-page 28 1996-2013 Microchip Technology Inc.
PIC16F8X
6.2 Using TMR0 with External Clock 6.2.2 TMR0 INCREMENT DELAY
When an external clock input is used for TMR0, it must Since the prescaler output is synchronized with the
meet certain requirements. The external clock internal clocks, there is a small delay from the time the
requirement is due to internal phase clock (TOSC) external clock edge occurs to the time the Timer0
synchronization. Also, there is a delay in the actual Module is actually incremented. Figure 6-5 shows the
incrementing of the TMR0 register after delay from the external clock edge to the timer
synchronization. incrementing.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION 6.3 Prescaler
When no prescaler is used, the external clock input is An 8-bit counter is available as a prescaler for the
the same as the prescaler output. The synchronization Timer0 Module, or as a postscaler for the Watchdog
of pin RA4/T0CKI with the internal phase clocks is Timer (Figure 6-6). For simplicity, this counter is being
accomplished by sampling the prescaler output on the referred to as “prescaler” throughout this data sheet.
Q2 and Q4 cycles of the internal phase clocks Note that there is only one prescaler available which is
(Figure 6-5). Therefore, it is necessary for T0CKI to be mutually exclusive between the Timer0 Module and the
high for at least 2Tosc (plus a small RC delay) and low Watchdog Timer. Thus, a prescaler assignment for the
for at least 2Tosc (plus a small RC delay). Refer to the Timer0 Module means that there is no prescaler for the
electrical specification of the desired device. Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is The PSA and PS2:PS0 bits (OPTION_REG)
divided by an asynchronous ripple counter type determine the prescaler assignment and prescale ratio.
prescaler so that the prescaler output is symmetrical. When assigned to the Timer0 Module, all instructions
For the external clock to meet the sampling writing to the Timer0 Module (e.g., CLRF 1, MOVWF
requirement, the ripple counter must be taken into 1, BSF 1,x ....etc.) will clear the prescaler. When
account. Therefore, it is necessary for T0CKI to have a assigned to WDT, a CLRWDT instruction will clear the
period of at least 4Tosc (plus a small RC delay) divided prescaler along with the Watchdog Timer. The
by the prescaler value. The only requirement on T0CKI prescaler is not readable or writable.
high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the AC Electrical
Specifications of the desired device.
1996-2013 Microchip Technology Inc. DS30430D-page 29
PIC16F8X
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Ext. Clock Input or
Prescaler Out (Note 2)
Ext. Clock/Prescaler (Note 3)
Output After Sampling
Increment TMR0 (Q4)
TMR0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate where sampling occurs. A small clock pulse may be missed by sampling.
FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER
CLKOUT (= Fosc/4) Data Bus
0 M 1 8
RA4/T0CKI U M SYNC
pin X U 2 TMR0 register
1 0 X Cycles
T0SE
T0CS PSA Set bit T0IF
on overflow
0 8-bit Prescaler
M
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
WDT Enable bit 0 1
MUX PSA
WDT
time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION_REG register.
DS30430D-page 30 1996-2013 Microchip Technology Inc.
PIC16F8X
6.3.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: CHANGING PRESCALER
The prescaler assignment is fully under software (TIMER0WDT)
control (i.e., it can be changed “on the fly” during BCF STATUS, RP0 ;Bank 0
CLRF TMR0 ;Clear TMR0
program execution). ; and Prescaler
Note: To avoid an unintended device RESET, the BSF STATUS, RP0 ;Bank 1
following instruction sequence CLRWDT ;Clears WDT
(Example 6-1) must be executed when MOVLW b'xxxx1xxx' ;Select new
MOVWF OPTION_REG ; prescale value
changing the prescaler assignment from BCF STATUS, RP0 ;Bank 0
Timer0 to the WDT. This sequence must
be taken even if the WDT is disabled. To EXAMPLE 6-2: CHANGING PRESCALER
change prescaler from the WDT to the (WDTTIMER0)
Timer0 module use the sequence shown in CLRWDT ;Clear WDT and
Example 6-2. ; prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW b'xxxx0xxx' ;Select TMR0, new
; prescale value
’ and clock source
MOVWF OPTION_REG ;
BCF STATUS, RP0 ;Bank 0
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER0
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 0000
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged. - = unimplemented read as '0'. Shaded cells are not associated with Timer0.
1996-2013 Microchip Technology Inc. DS30430D-page 31
PIC16F8X
NOTES:
DS30430D-page 32 1996-2013 Microchip Technology Inc.
PIC16F8X
7.0 DATA EEPROM MEMORY data memory is rated for high erase/write cycles. The
The EEPROM data memory is readable and writable write time is controlled by an on-chip timer. The write-
during normal operation (full VDD range). This memory time will vary with voltage and temperature as well as
is not directly mapped in the register file space. Instead from chip to chip. Please refer to AC specifications for
it is indirectly addressed through the Special Function exact limits.
Registers. There are four SFRs used to read and write When the device is code protected, the CPU may
this memory. These registers are: continue to read and write the data EEPROM memory.
• EECON1 The device programmer can no longer access
• EECON2 this memory.
• EEDATA 7.1 EEADR
• EEADR
EEDATA holds the 8-bit data for read/write, and EEADR The EEADR register can address up to a maximum of
holds the address of the EEPROM location being 256 bytes of data EEPROM. Only the first 64 bytes of
accessed. PIC16F8X devices have 64 bytes of data data EEPROM are implemented.
EEPROM with an address range from 0h to 3Fh. The upper two bits are address decoded. This means
The EEPROM data memory allows byte read and write. that these two bits must always be '0' to ensure that the
A byte write automatically erases the location and address is in the 64 byte memory space.
writes the new data (erase before write). The EEPROM
FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)
U U U R/W-0 R/W-x R/W-0 R/S-0 R/S-x
— — — EEIF WRERR WREN WR RD R = Readable bit
bit7 bit0 W = Writable bit
S = Settable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:5 Unimplemented: Read as '0'
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
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PIC16F8X
7.2 EECON1 and EECON2 Registers 7.4 Writing to the EEPROM Data Memory
EECON1 is the control register with five low order bits To write an EEPROM data location, the user must first
physically implemented. The upper-three bits are non- write the address to the EEADR register and the data
existent and read as '0's. to the EEDATA register. Then the user must follow a
Control bits RD and WR initiate read and write, specific sequence to initiate the write for each byte.
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion EXAMPLE 7-1: DATA EEPROM WRITE
of the read or write operation. The inability to clear the BSF STATUS, RP0 ; Bank 1
WR bit in software prevents the accidental, premature BCF INTCON, GIE ; Disable INTs.
termination of a write operation. BSF EECON1, WREN ; Enable Write
The WREN bit, when set, will allow a write operation. MOVLW 55h ;
On power-up, the WREN bit is clear. The WRERR bit is MOVWF EECON2 ; Write 55h
set when a write operation is interrupted by a MCLR Required Sequence MOVLW AAh ;
reset or a WDT time-out reset during normal operation. MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit
In these situations, following reset, the user can check ; begin write
the WRERR bit and rewrite the location. The data and BSF INTCON, GIE ; Enable INTs.
address will be unchanged in the EEDATA and The write will not initiate if the above sequence is not
EEADR registers. exactly followed (write 55h to EECON2, write AAh to
Interrupt flag bit EEIF is set when write is complete. It EECON2, then set WR bit) for each byte. We strongly
must be cleared in software. recommend that interrupts be disabled during this
EECON2 is not a physical register. Reading EECON2 code segment.
will read all '0's. The EECON2 register is used Additionally, the WREN bit in EECON1 must be set to
exclusively in the Data EEPROM write sequence. enable write. This mechanism prevents accidental
7.3 Reading the EEPROM Data Memory writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
To read a data memory location, the user must write the keep the WREN bit clear at all times, except when
address to the EEADR register and then set control bit updating EEPROM. The WREN bit is not cleared
RD (EECON1). The data is available, in the very by hardware
next cycle, in the EEDATA register; therefore it can be After a write sequence has been initiated, clearing the
read in the next instruction. EEDATA will hold this value WREN bit will not affect this write cycle. The WR bit will
until another read or until it is written to by the user be inhibited from being set unless the WREN bit is set.
(during a write operation). At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
EXAMPLE 7-1: DATA EEPROM READ Interrupt Flag bit (EEIF) is set. The user can either
BCF STATUS, RP0 ; Bank 0 enable this interrupt or poll this bit. EEIF must be
MOVLW CONFIG_ADDR ; cleared by software.
MOVWF EEADR ; Address to read
BSF STATUS, RP0 ; Bank 1
BSF EECON1, RD ; EE Read
BCF STATUS, RP0 ; Bank 0
MOVF EEDATA, W ; W = EEDATA
DS30430D-page 34 1996-2013 Microchip Technology Inc.
PIC16F8X
7.5 Write Verify SUBWF EEDATA, W ;
BTFSS STATUS, Z ; Is difference 0?
Depending on the application, good programming prac- GOTO WRITE_ERR ; NO, Write error
tice may dictate that the value written to the Data : ; YES, Good write
EEPROM should be verified (Example 7-1) to the : ; Continue program
desired value to be written. This should be used in 7.6 Protection Against Spurious Writes
applications where an EEPROM bit will be stressed
near the specification limit. The Total Endurance disk There are conditions when the device may not want to
will help determine your comfort level. write to the data EEPROM memory. To protect against
Generally the EEPROM write failure will be a bit which spurious EEPROM writes, various mechanisms have
was written as a '1', but reads back as a '0' (due to been built in. On power-up, WREN is cleared. Also, the
leakage off the bit). Power-up Timer (72 ms duration) prevents
EEPROM write.
EXAMPLE 7-1: WRITE VERIFY The write initiate sequence and the WREN bit together
BCF STATUS, RP0 ; Bank 0 help prevent an accidental write during brown-out,
: ; Any code can go here power glitch, or software malfunction.
: ; 7.7 Data EEPROM Operation during Code
MOVF EEDATA, W ; Must be in Bank 0
BSF STATUS, RP0 ; Bank 1 Protect
READ
BSF EECON1, RD ; YES, Read the When the device is code protected, the CPU is able to
; value written read and write unscrambled data to the Data EEPROM.
BCF STATUS, RP0 ; Bank 0 For ROM devices, there are two code protection bits
; (Section 8.1). One for the ROM program memory and
; Is the value written (in W reg) and one for the Data EEPROM memory.
; read (in EEDATA) the same?
;
TABLE 7-1 REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset
08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu
09h EEADR EEPROM address register xxxx xxxx uuuu uuuu
88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000
89h EECON2 EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not
used by Data EEPROM.
1996-2013 Microchip Technology Inc. DS30430D-page 35
PIC16F8X
NOTES:
DS30430D-page 36 1996-2013 Microchip Technology Inc.
PIC16F8X
8.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real time applications. The PIC16F8X has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These features are:
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC16F8X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. This
design keeps the device in reset while the power supply
stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode offers a very low current power-down
mode. The user can wake-up from SLEEP through
external reset, Watchdog Timer time-out or through an
interrupt. Several oscillator options are provided to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select the various options.
1996-2013 Microchip Technology Inc. DS30430D-page 37
PIC16F8X
8.1 Configuration Bits Address 2007h is beyond the user program memory
space and it belongs to the special test/configuration
The configuration bits can be programmed (read as '0') memory space (2000h - 3FFFh). This space can only
or left unprogrammed (read as '1') to select various be accessed during programming.
device configurations. These bits are mapped in To find out how to program the PIC16C84, refer to
program memory location 2007h. PIC16C84 EEPROM Memory Programming Specifica-
tion (DS30189).
FIGURE 8-1: CONFIGURATION WORD - PIC16CR83 AND PIC16CR84
R-u R-u R-u R-u R-u R-u R/P-u R-u R-u R-u R-u R-u R-u R-u
CP CP CP CP CP CP DP CP CP CP PWRTE WDTE FOSC1 FOSC0
bit13 bit0
R = Readable bit
P = Programmable bit
- n = Value at POR reset
u = unchanged
bit 13:8 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 7 DP: Data Memory Code Protection bit
1 = Code protection off
0 = Data memory is code protected
bit 6:4 CP: Program Memory Code Protection bit
1 = Code protection off
0 = Program memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
DS30430D-page 38 1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-2: CONFIGURATION WORD - PIC16F83 AND PIC16F84
R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u
CP CP CP CP CP CP CP CP CP CP PWRTE WDTE FOSC1 FOSC0
bit13 bit0
R = Readable bit
P = Programmable bit
-n = Value at POR reset
u = unchanged
bit 13:4 CP: Code Protection bit
1 = Code protection off
0 = All memory is code protected
bit 3 PWRTE: Power-up Timer Enable bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1:0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
8.2 Oscillator Configurations FIGURE 8-3: CRYSTAL/CERAMIC
8.2.1 OSCILLATOR TYPES RESONATOR OPERATION
(HS, XT OR LP OSC
The PIC16F8X can be operated in four different CONFIGURATION)
oscillator modes. The user can program two C1(1) OSC1
configuration bits (FOSC1 and FOSC0) to select one of
these four modes: To
internal
• LP Low Power Crystal XTAL RF(3) logic
• XT Crystal/Resonator OSC2
• HS High Speed Crystal/Resonator RS(2) SLEEP
• RC Resistor/Capacitor C2(1) PIC16FXX
8.2.2 CRYSTAL OSCILLATOR / CERAMIC Note1: See Table 8-1 for recommended values of
RESONATORS C1 and C2.
In XT, LP or HS modes a crystal or ceramic resonator 2: A series resistor (RS) may be required for
is connected to the OSC1/CLKIN and OSC2/CLKOUT AT strip cut crystals.
pins to establish oscillation (Figure 8-3). 3: RF varies with the crystal chosen.
The PIC16F8X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the device
can have an external clock source to drive the
OSC1/CLKIN pin (Figure 8-4).
1996-2013 Microchip Technology Inc. DS30430D-page 39
PIC16F8X
FIGURE 8-4: EXTERNAL CLOCK INPUT Crystals Tested:
OPERATION (HS, XT OR LP
OSC CONFIGURATION) 32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz Epson C-2 100.00 KC-P 20 PPM
200 kHz STD XTL 200.000 KHz 20 PPM
Clock from OSC1 1.0 MHz ECS ECS-10-13-2 50 PPM
ext. system PIC16FXX 2.0 MHz ECS ECS-20-S-2 50 PPM
Open OSC2 4.0 MHz ECS ECS-40-S-4 50 PPM
10.0 MHz ECS ECS-100-S-4 50 PPM
TABLE 8-1 CAPACITOR SELECTION FOR 8.2.3 EXTERNAL CRYSTAL OSCILLATOR
CERAMIC RESONATORS CIRCUIT
Ranges Tested: Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Mode Freq OSC1/C1 OSC2/C2 Prepackaged oscillators provide a wide operating
XT 455 kHz 47 - 100 pF 47 - 100 pF range and better stability. A well-designed crystal
2.0 MHz 15 - 33 pF 15 - 33 pF oscillator will provide good performance with TTL
4.0 MHz 15 - 33 pF 15 - 33 pF gates. Two types of crystal oscillator circuits are
HS 8.0 MHz 15 - 33 pF 15 - 33 pF available; one with series resonance, and one with
10.0 MHz 15 - 33 pF 15 - 33 pF parallel resonance.
Note : Recommended values of C1 and C2 are identical to Figure 8-5 shows a parallel resonant oscillator circuit.
the ranges tested table. The circuit is designed to use the fundamental
Higher capacitance increases the stability of the frequency of the crystal. The 74AS04 inverter performs
oscillator but also increases the start-up time. the 180-degree phase shift that a parallel oscillator
These values are for design guidance only. Since requires. The 4.7 k resistor provides negative
each resonator has its own characteristics, the user feedback for stability. The 10 k potentiometer biases
should consult the resonator manufacturer for the the 74AS04 in the linear region. This could be used for
appropriate values of external components. external oscillator designs.
Resonators Tested:
455 kHz Panasonic EFO-A455K04B 0.3% FIGURE 8-5: EXTERNAL PARALLEL
2.0 MHz Murata Erie CSA2.00MG 0.5% RESONANT CRYSTAL
4.0 MHz Murata Erie CSA4.00MG 0.5% OSCILLATOR CIRCUIT
8.0 MHz Murata Erie CSA8.00MT 0.5% +5V
10.0 MHz Murata Erie CSA10.00MTZ 0.5% To Other
Devices PIC16FXX
None of the resonators had built-in capacitors. 10k
4.7k 74AS04
TABLE 8-2 CAPACITOR SELECTION FOR 74AS04 CLKIN
CRYSTAL OSCILLATOR
Mode Freq OSC1/C1 OSC2/C2 10k
LP 32 kHz 68 - 100 pF 68 - 100 pF XTAL
200 kHz 15 - 33 pF 15 - 33 pF
XT 100 kHz 100 - 150 pF 100 - 150 pF 10k
2 MHz 15 - 33 pF 15 - 33 pF 20 pF 20 pF
4 MHz 15 - 33 pF 15 - 33 pF
HS 4 MHz 15 - 33 pF 15 - 33 pF
10 MHz 15 - 33 pF 15 - 33 pF Figure 8-6 shows a series resonant oscillator circuit.
Note : Higher capacitance increases the stability of This circuit is also designed to use the fundamental
oscillator but also increases the start-up time. frequency of the crystal. The inverter performs a
These values are for design guidance only. Rs may 180-degree phase shift. The 330 k resistors provide
be required in HS mode as well as XT mode to the negative feedback to bias the inverters in their
avoid overdriving crystals with low drive level speci- linear region.
fication. Since each crystal has its own characteris-
tics, the user should consult the crystal
manufacturer for appropriate values of external
components.
For VDD > 4.5V, C1 = C2 30 pF is recommended.
DS30430D-page 40 1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-6: EXTERNAL SERIES FIGURE 8-7: RC OSCILLATOR MODE
RESONANT CRYSTAL VDD
OSCILLATOR CIRCUIT
Rext
OSC1 Internal
To Other clock
330 k 330 k Devices PIC16FXX
74AS04 74AS04 74AS04 Cext PIC16FXX
CLKIN VSS
0.1F OSC2/CLKOUT
Fosc/4
XTAL Recommended values: 5 k Rext 100 k
Cext > 20pF
Note: When the device oscillator is in RC mode,
8.2.4 RC OSCILLATOR do not drive the OSC1 pin with an external
clock or you may damage the device.
For timing insensitive applications the RC device option 8.3 Reset
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the The PIC16F8X differentiates between various kinds
resistor (Rext) values, capacitor (Cext) values, and the of reset:
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal • Power-on Reset (POR)
process parameter variation. Furthermore, the • MCLR reset during normal operation
difference in lead frame capacitance between package • MCLR reset during SLEEP
types also affects the oscillation frequency, especially • WDT Reset (during normal operation)
for low Cext values. The user needs to take into • WDT Wake-up (during SLEEP)
account variation due to tolerance of the external
R and C components. Figure 8-7 shows how an R/C Figure 8-8 shows a simplified block diagram of the
combination is connected to the PIC16F8X. For Rext on-chip reset circuit. The MCLR reset path has a noise
values below 4 k, the oscillator operation may filter to ignore small pulses. The electrical specifica-
become unstable, or stop completely. For very high tions state the pulse width requirements for the MCLR
Rext values (e.g., 1 M), the oscillator becomes pin.
sensitive to noise, humidity and leakage. Thus, we Some registers are not affected in any reset condition;
recommend keeping Rext between 5 k and 100 k. their status is unknown on a POR reset and unchanged
Although the oscillator will operate with no external in any other reset. Most other registers are reset to a
capacitor (Cext = 0 pF), we recommend using values “reset state” on POR, MCLR or WDT reset during
above 20 pF for noise and stability reasons. With little normal operation and on MCLR reset during SLEEP.
or no external capacitance, the oscillation frequency They are not affected by a WDT reset during SLEEP,
can vary dramatically due to changes in external since this reset is viewed as the resumption of normal
capacitances, such as PCB trace capacitance or operation.
package lead frame capacitance. Table 8-3 gives a description of reset conditions for the
See the electrical specification section for RC program counter (PC) and the STATUS register.
frequency variation from part to part due to normal Table 8-4 gives a full description of reset states for all
process variation. The variation is larger for larger R registers.
(since leakage current variation will affect RC The TO and PD bits are set or cleared differently in dif-
frequency more for large R) and for smaller C (since ferent reset situations (Section 8.7). These bits are
variation of input capacitance has a greater affect on used in software to determine the nature of the reset.
RC frequency).
See the electrical specification section for variation of
oscillator frequency due to VDD for given Rext/Cext
values as well as frequency variation due to
operating temperature.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (see Figure 3-2
for waveform).
1996-2013 Microchip Technology Inc. DS30430D-page 41
PIC16F8X
FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT WDT SLEEP
Module Time_Out
Reset
VDD rise
detect Power_on_Reset S
VDD
OST/PWRT
OST Chip_Reset
10-bit Ripple counter R Q
OSC1/
CLKIN
PWRT
On-chip
RC OSC(1) 10-bit Ripple counter
Enable PWRT
Note 1: This is a separate oscillator from the See Table 8-5
RC oscillator of the CLKIN pin. Enable OST
DS30430D-page 42 1996-2013 Microchip Technology Inc.
PIC16F8X
TABLE 8-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
Condition Program Counter STATUS Register
Power-on Reset 000h 0001 1xxx
MCLR Reset during normal operation 000h 000u uuuu
MCLR Reset during SLEEP 000h 0001 0uuu
WDT Reset (during normal operation) 000h 0000 1uuu
WDT Wake-up PC + 1 uuu0 0uuu
Interrupt wake-up from SLEEP PC + 1 (1) uuu1 0uuu
Legend: u = unchanged, x = unknown.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 8-4 RESET CONDITIONS FOR ALL REGISTERS
MCLR Reset during: Wake-up from SLEEP:
– normal operation – through interrupt
Register Address Power-on Reset – SLEEP – through WDT Time-out
WDT Reset during nor-
mal operation
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h ---- ---- ---- ---- ---- ----
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000h 0000h PC + 1(2)
STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---x xxxx ---u uuuu ---u uuuu
PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu
EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1)
INDF 80h ---- ---- ---- ---- ---- ----
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
PCL 82h 0000h 0000h PC + 1
STATUS 83h 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu
TRISA 85h ---1 1111 ---1 1111 ---u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
EECON1 88h ---0 x000 ---0 q000 ---0 uuuu
EECON2 89h ---- ---- ---- ---- ---- ----
PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 8Bh 0000 000x 0000 000u uuuu uuuu(1)
Legend: u = unchanged, x = unknown, -= unimplemented bit read as '0',
q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: Table 8-3 lists the reset value for each specific condition.
1996-2013 Microchip Technology Inc. DS30430D-page 43
PIC16F8X
8.4 Power-on Reset (POR) FIGURE 8-9: EXTERNAL POWER-ON
A Power-on Reset pulse is generated on-chip when RESET CIRCUIT (FOR SLOW
VDD rise is detected (in the range of 1.2V - 1.7V). To VDD POWER-UP)
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will VDD VDD
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for VDD D R
must be met for this to operate properly. See Electrical R1
Specifications for details. MCLR
When the device starts normal operation (exits the C PIC16FXX
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device Note 1: External Power-on Reset circuit is required
must be held in reset until the operating conditions only if VDD power-up rate is too slow. The
are met. diode D helps discharge the capacitor
For additional information, refer to Application Note quickly when VDD powers down.
AN607, "Power-up Trouble Shooting." 2: R < 40 k is recommended to make sure
The POR circuit does not produce an internal reset that voltage drop across R does not exceed
when VDD declines. 0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
8.5 Power-up Timer (PWRT) degrade VIH level on the MCLR pin.
3: R1 = 100 to 1 k will limit any current
The Power-up Timer (PWRT) provides a fixed 72 ms flowing into MCLR from external
nominal time-out (TPWRT) from POR (Figure 8-10, capacitor C in the event of an MCLR pin
Figure 8-11, Figure 8-12 and Figure 8-13). The breakdown due to ESD or EOS.
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT delay allows the VDD to rise to an accept-
able level (Possible exception shown in Figure 8-13).
A configuration bit, PWRTE, can enable/disable the
PWRT. See either Figure 8-1 or Figure 8-2 for the oper-
ation of the PWRTE bit for a particular device.
The power-up time delay TPWRT will vary from chip to
chip due to VDD, temperature, and process variation.
See DC parameters for details.
8.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 8-10, Figure 8-11,
Figure 8-12 and Figure 8-13). This ensures the crystal
oscillator or resonator has started and stabilized.
The OST time-out (TOST) is invoked only for XT, LP and
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When VDD rises very slowly, it is possible that the
TPWRT time-out and TOST time-out will expire before
VDD has reached its final value. In this case
(Figure 8-13), an external power-on reset circuit may
be necessary (Figure 8-9).
DS30430D-page 44 1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
1996-2013 Microchip Technology Inc. DS30430D-page 45
PIC16F8X
FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
When VDD rises very slowly, it is possible that the TPWRT time-out and TOST time-out will expire before VDD
has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS30430D-page 46 1996-2013 Microchip Technology Inc.
PIC16F8X
8.7 Time-out Sequence and Power-down 8.8 Reset on Brown-Out
Status Bits (TO/PD) A brown-out is a condition where device power (VDD)
On power-up (Figure 8-10, Figure 8-11, Figure 8-12 dips below its minimum value, but not to zero, and then
and Figure 8-13) the time-out sequence is as follows: recovers. The device should be reset in the event of a
First PWRT time-out is invoked after a POR has brown-out.
expired. Then the OST is activated. The total time-out To reset a PIC16F8X device when a brown-out occurs,
will vary based on oscillator configuration and PWRTE external brown-out protection circuits may be built, as
configuration bit status. For example, in RC mode with shown in Figure 8-14 and Figure 8-15.
the PWRT disabled, there will be no time-out at all.
TABLE 8-5 TIME-OUT IN VARIOUS FIGURE 8-14: BROWN-OUT PROTECTION
SITUATIONS CIRCUIT 1
Oscillator Power-up Wake-up VDD
Configuration PWRT PWRT from VDD
Enabled Disabled SLEEP 33k
XT, HS, LP 72 ms + 1024TOSC 1024TOSC
1024TOSC 10k MCLR
RC 72 ms — —
Since the time-outs occur from the POR reset pulse, if 40k PIC16F8X
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high, execution will begin
immediately (Figure 8-10). This is useful for testing
purposes or to synchronize more than one PIC16F8X
device when operating in parallel. This circuit will activate reset when VDD goes below
Table 8-6 shows the significance of the TO and PD bits. (Vz + 0.7V) where Vz = Zener voltage.
Table 8-3 lists the reset conditions for some special
registers, while Table 8-4 lists the reset conditions for FIGURE 8-15: BROWN-OUT PROTECTION
all the registers. CIRCUIT 2
TABLE 8-6 STATUS BITS AND THEIR VDD
SIGNIFICANCE VDD
TO PD Condition R1
1 1 Power-on Reset Q1
MCLR
0 x Illegal, TO is set on POR R2
x 0 Illegal, PD is set on POR 40k PIC16F8X
0 1 WDT Reset (during normal operation)
0 0 WDT Wake-up
1 1 MCLR Reset during normal operation
1 0 MCLR Reset during SLEEP or interrupt This brown-out circuit is less expensive, although less
wake-up from SLEEP accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
VDD • R1 = 0.7V
R1 + R2
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PIC16F8X
8.9 Interrupts The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
The PIC16F8X has 4 sources of interrupt: the INTCON register.
• External interrupt RB0/INT pin When an interrupt is responded to; the GIE bit is
• TMR0 overflow interrupt cleared to disable any further interrupt, the return
• PORTB change interrupts (pins RB7:RB4) address is pushed onto the stack and the PC is loaded
• Data EEPROM write complete interrupt with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
The interrupt control register (INTCON) records latency will be three to four instruction cycles. The
individual interrupt requests in flag bits. It also contains exact latency depends when the interrupt event occurs
the individual and global interrupt enable bits. (Figure 8-17). The latency is the same for both one and
The global interrupt enable bit, GIE (INTCON) two cycle instructions. Once in the interrupt service
enables (if set) all un-masked interrupts or disables (if routine the source(s) of the interrupt can be determined
cleared) all interrupts. Individual interrupts can be by polling the interrupt flag bits. The interrupt flag bit(s)
disabled through their corresponding enable bits in must be cleared in software before re-enabling
INTCON register. Bit GIE is cleared on reset. interrupts to avoid infinite interrupt requests.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which Note 1: Individual interrupt flag bits are set
re-enable interrupts. regardless of the status of their
FIGURE 8-16: INTERRUPT LOGIC corresponding mask bit or the GIE bit.
T0IF Wake-up
T0IE (If in SLEEP mode)
INTF
INTE Interrupt to CPU
RBIF
RBIE
EEIF
EEIE
GIE
DS30430D-page 48 1996-2013 Microchip Technology Inc.
PIC16F8X
FIGURE 8-17: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT 3
4
INT pin
1 1
INTF flag 5 Interrupt Latency 2
(INTCON)
GIE bit
(INTCON)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction Inst (PC) Inst (PC+1) — Inst (0004h)
fetched Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h)
executed
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
8.9.1 INT INTERRUPT 8.9.3 PORT RB INTERRUPT
External interrupt on RB0/INT pin is edge triggered: An input change on PORTB sets flag bit RBIF
either rising if INTEDG bit (OPTION_REG) is set, (INTCON). The interrupt can be enabled/disabled
or falling, if INTEDG bit is clear. When a valid edge by setting/clearing enable bit RBIE (INTCON)
appears on the RB0/INT pin, the INTF bit (Section 5.2).
(INTCON) is set. This interrupt can be disabled by Note 1: For a change on the I/O pin to be
clearing control bit INTE (INTCON). Flag bit INTF recognized, the pulse width must be at
must be cleared in software via the interrupt service least TCY wide.
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.12) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.9.2 TMR0 INTERRUPT
An overflow (FFh 00h) in TMR0 will set flag bit T0IF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON)
(Section 6.0).
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PIC16F8X
8.10 Context Saving During Interrupts Example 8-1 does the following:
During an interrupt, only the return PC value is saved a) Stores the W register.
on the stack. Typically, users wish to save key register b) Stores the STATUS register in STATUS_TEMP.
values during an interrupt (e.g., W register and c) Executes the Interrupt Service Routine code.
STATUS register). This is implemented in software. d) Restores the STATUS (and bank select bit)
Example 8-1 stores and restores the STATUS and W register.
register’s values. The User defined registers, W_TEMP e) Restores the W register.
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
SWAPF STATUS, W ; Swap status to be saved into W
MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
ISR : :
: ; Interrupt Service Routine
: ; should configure Bank as required
: ;
POP SWAPF STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF STATUS ; Move W into STATUS register
; (sets bank to original state)
SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W
DS30430D-page 50 1996-2013 Microchip Technology Inc.
PIC16F8X
8.11 Watchdog Timer (WDT) part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
The Watchdog Timer is a free running on-chip RC can be assigned to the WDT under software control by
oscillator which does not require any external writing to the OPTION_REG register. Thus, time-out
components. This RC oscillator is separate from the periods up to 2.3 seconds can be realized.
RC oscillator of the OSC1/CLKIN pin. That means that The CLRWDT and SLEEP instructions clear the WDT
the WDT will run even if the clock on the OSC1/CLKIN and the postscaler (if assigned to the WDT) and pre-
and OSC2/CLKOUT pins of the device has been vent it from timing out and generating a device
stopped, for example, by execution of a SLEEP RESET condition.
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP The TO bit in the STATUS register will be cleared upon
mode, a WDT Wake-up causes the device to wake-up a WDT time-out.
and continue with normal operation. The WDT can be 8.11.2 WDT PROGRAMMING CONSIDERATIONS
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1). It should also be taken into account that under worst
8.11.1 WDT PERIOD case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
The WDT has a nominal time-out period of 18 ms, (with WDT time-out occurs.
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
1 M Postscaler
WDT Timer • U
X 8
8 - to -1 MUX PS2:PS0
WDT PSA
Enable Bit
• To TMR0 (Figure 6-6)
0 1
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 8-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets
Reset
2007h Config. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2)
81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
REG
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.
2: See Figure 8-1, Figure 8-2 and Section 8.13 for operation of the Code and Data protection bits.
1996-2013 Microchip Technology Inc. DS30430D-page 51
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8.12 Power-down Mode (SLEEP) 8.12.2 WAKE-UP FROM SLEEP
A device may be powered down (SLEEP) and later The device can wake-up from SLEEP through one of
powered up (Wake-up from SLEEP). the following events:
8.12.1 SLEEP 1. External reset input on MCLR pin.
2. WDT Wake-up (if WDT was enabled).
The Power-down mode is entered by executing the 3. Interrupt from RB0/INT pin, RB port change, or
SLEEP instruction. data EEPROM write complete.
If enabled, the Watchdog Timer is cleared (but keeps Peripherals cannot generate interrupts during SLEEP,
running), the PD bit (STATUS) is cleared, the TO bit since no on-chip Q clocks are present.
(STATUS) is set, and the oscillator driver is turned The first event (MCLR reset) will cause a device reset.
off. The I/O ports maintain the status they had before The two latter events are considered a continuation of
the SLEEP instruction was executed (driving high, low, program execution. The TO and PD bits can be used to
or hi-impedance). determine the cause of a device reset. The PD bit,
For the lowest current consumption in SLEEP mode, which is set on power-up, is cleared when SLEEP is
place all I/O pins at either at VDD or VSS, with no invoked. The TO bit is cleared if a WDT time-out
external circuitry drawing current from the I/O pins, and occurred (and caused wake-up).
disable external clocks. I/O pins that are hi-impedance While the SLEEP instruction is being executed, the next
inputs should be pulled high or low externally to avoid instruction (PC + 1) is pre-fetched. For the device to
switching currents caused by floating inputs. The wake-up through an interrupt event, the corresponding
T0CKI input should also be at VDD or VSS. The interrupt enable bit must be set (enabled). Wake-up
contribution from on-chip pull-ups on PORTB should be occurs regardless of the state of the GIE bit. If the GIE
considered. bit is clear (disabled), the device continues execution at
The MCLR pin must be at a logic high level (VIHMC). the instruction after the SLEEP instruction. If the GIE bit
It should be noted that a RESET generated by a WDT is set (enabled), the device executes the instruction
time-out does not drive the MCLR pin low. after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the
SLEEP instruction.
FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag Interrupt Latency
(INTCON)
(Note 2)
GIE bit Processor in
(INTCON)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
fetched
Instruction Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h)
executed
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30430D-page 52 1996-2013 Microchip Technology Inc.
PIC16F8X
8.12.3 WAKE-UP USING INTERRUPTS 8.15 In-Circuit Serial Programming
When global interrupts are disabled (GIE cleared) and PIC16F8X microcontrollers can be serially
any interrupt source has both its interrupt enable bit programmed while in the end application circuit. This is
and interrupt flag bit set, one of the following will occur: simply done with two lines for clock and data, and three
• If the interrupt occurs before the execution of a other lines for power, ground, and the programming
SLEEP instruction, the SLEEP instruction will com- voltage. Customers can manufacture boards with
plete as a NOP. Therefore, the WDT and WDT unprogrammed devices, and then program the
postscaler will not be cleared, the TO bit will not microcontroller just before shipping the product,
be set and PD bits will not be cleared. allowing the most recent firmware or custom firmware
• If the interrupt occurs during or after the execu- to be programmed.
tion of a SLEEP instruction, the device will imme- The device is placed into a program/verify mode by
diately wake up from sleep. The SLEEP instruction holding the RB6 and RB7 pins low, while raising the
will be completely executed before the wake-up. MCLR pin from VIL to VIHH (see programming
Therefore, the WDT and WDT postscaler will be specification). RB6 becomes the programming clock
cleared, the TO bit will be set and the PD bit will and RB7 becomes the programming data. Both RB6
be cleared. and RB7 are Schmitt Trigger inputs in this mode.
Even if the flag bits were checked before executing a After reset, to place the device into programming/verify
SLEEP instruction, it may be possible for flag bits to mode, the program counter (PC) points to location 00h.
become set before the SLEEP instruction completes. To A 6-bit command is then supplied to the device, 14-bits
determine whether a SLEEP instruction executed, test of program data is then supplied to or from the device,
the PD bit. If the PD bit is set, the SLEEP instruction using load or read-type instructions. For complete
was executed as a NOP. details of serial programming, please refer to the
To ensure that the WDT is cleared, a CLRWDT instruc- PIC16CXX Programming Specifications (Literature
tion should be executed before a SLEEP instruction. #DS30189).
8.13 Program Verification/Code Protection FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL
PROGRAMMING
If the code protection bit(s) have not been CONNECTION
programmed, the on-chip program memory can be
read out for verification purposes.
Note: Microchip does not recommend code pro- To Normal
External Connections
tecting widowed devices. Connector PIC16FXX
Signals
8.14 ID Locations +5V VDD
Four memory locations (2000h - 2003h) are designated 0V VSS
as ID locations to store checksum or other code VPP MCLR/VPP
identification numbers. These locations are not
accessible during normal execution but are readable CLK RB6
and writable only during program/verify. Only the Data I/O RB7
4 least significant bits of ID location are usable.
For ROM devices, these values are submitted along
with the ROM code. VDD
To Normal
Connections
For ROM devices, both the program memory and Data
EEPROM memory may be read, but only the Data
EEPROM memory may be programmed.
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9.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
Each PIC16CXX instruction is a 14-bit word divided into three basic categories:
into an OPCODE which specifies the instruction type • Byte-oriented operations
and one or more operands which further specify the • Bit-oriented operations
operation of the instruction. The PIC16CXX instruction • Literal and control operations
set summary in Table 9-2 lists byte-oriented, bit-ori- All instructions are executed within one single instruc-
ented, and literal and control operations. Table 9-1 tion cycle, unless a conditional test is true or the pro-
shows the opcode field descriptions. gram counter is changed as a result of an instruction.
For byte-oriented instructions, 'f' represents a file reg- In this case, the execution takes two instruction cycles
ister designator and 'd' represents a destination desig- with the second cycle executed as a NOP. One instruc-
nator. The file register designator specifies which file tion cycle consists of four oscillator periods. Thus, for
register is to be used by the instruction. an oscillator frequency of 4 MHz, the normal instruction
The destination designator specifies where the result of execution time is 1 s. If a conditional test is true or the
the operation is to be placed. If 'd' is zero, the result is program counter is changed as a result of an instruc-
placed in the W register. If 'd' is one, the result is placed tion, the instruction execution time is 2 s.
in the file register specified in the instruction. Table 9-2 lists the instructions recognized by the
For bit-oriented instructions, 'b' represents a bit field MPASM assembler.
designator which selects the number of the bit affected Figure 9-1 shows the general formats that the instruc-
by the operation, while 'f' represents the number of the tions can have.
file in which the bit is located. Note: To maintain upward compatibility with
For literal and control operations, 'k' represents an future PIC16CXX products, do not use the
eight or eleven bit constant or literal value. OPTION and TRIS instructions.
TABLE 9-1 OPCODE FIELD All examples use the following format to represent a
DESCRIPTIONS hexadecimal number:
Field Description 0xhh
f Register file address (0x00 to 0x7F) where h signifies a hexadecimal digit.
W Working register (accumulator)
b Bit address within an 8-bit file register FIGURE 9-1: GENERAL FORMAT FOR
k Literal field, constant data or label INSTRUCTIONS
x Don't care location (= 0 or 1) Byte-oriented file register operations
The assembler will generate code with x = 0. It is the 13 8 7 6 0
recommended form of use for compatibility with all OPCODE d f (FILE #)
Microchip software tools. d = 0 for destination W
d Destination select; d = 0: store result in W, d = 1 for destination f
d = 1: store result in file register f. f = 7-bit file register address
Default is d = 1
label Label name Bit-oriented file register operations
TOS Top of Stack 13 10 9 7 6 0
PC Program Counter OPCODE b (BIT #) f (FILE #)
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit b = 3-bit bit address
WDT Watchdog Timer/Counter f = 7-bit file register address
TO Time-out bit Literal and control operations
PD Power-down bit
dest Destination either the W register or the specified General
register file location 13 8 7 0
[ ] Options OPCODE k (literal)
( ) Contents
Assigned to k = 8-bit immediate value
Register bit field
In the set of CALL and GOTO instructions only
italics User defined term (font is courier) 13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
1996-2013 Microchip Technology Inc. DS30430D-page 55
PIC16F8X
TABLE 9-2 PIC16FXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30430D-page 56 1996-2013 Microchip Technology Inc.
PIC16F8X
9.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW AND Literal with W
Syntax: [label] ADDLW k Syntax: [label] ANDLW k
Operands: 0 k 255 Operands: 0 k 255
Operation: (W) + k (W) Operation: (W) .AND. (k) (W)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
literal 'k' data W literal "k" data W
Example: ADDLW 0x15 Example ANDLW 0x5F
Before Instruction Before Instruction
W = 0x10 W = 0xA3
After Instruction After Instruction
W = 0x25 W = 0x03
ADDWF Add W and f ANDWF AND W with f
Syntax: [label] ADDWF f,d Syntax: [label] ANDWF f,d
Operands: 0 f 127 Operands: 0 f 127
d d
Operation: (W) + (f) (destination) Operation: (W) .AND. (f) (destination)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff
Description: Add the contents of the W register with Description: AND the W register with register 'f'. If 'd'
register 'f'. If 'd' is 0 the result is stored is 0 the result is stored in the W regis-
in the W register. If 'd' is 1 the result is ter. If 'd' is 1 the result is stored back in
stored back in register 'f'. register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register data destination register data destination
'f' 'f'
Example ADDWF FSR, 0 Example ANDWF FSR, 1
Before Instruction Before Instruction
W = 0x17 W = 0x17
FSR = 0xC2 FSR = 0xC2
After Instruction After Instruction
W = 0xD9 W = 0x17
FSR = 0xC2 FSR = 0x02
1996-2013 Microchip Technology Inc. DS30430D-page 57
PIC16F8X
BCF Bit Clear f BTFSC Bit Test, Skip if Clear
Syntax: [label] BCF f,b Syntax: [label] BTFSC f,b
Operands: 0 f 127 Operands: 0 f 127
0b7 0b7
Operation: 0 (f) Operation: skip if (f) = 0
Status Affected: None Status Affected: None
Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff
Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '1' then the next
Words: 1 instruction is executed.
If bit 'b', in register 'f', is '0' then the next
Cycles: 1 instruction is discarded, and a NOP is
Q Cycle Activity: Q1 Q2 Q3 Q4 executed instead, making this a 2TCY
instruction.
Decode Read Process Write Words: 1
register data register 'f'
'f' Cycles: 1(2)
Example BCF FLAG_REG, 7 Q Cycle Activity: Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No-Operat
register 'f' data ion
FLAG_REG = 0xC7
After Instruction If Skip: (2nd Cycle)
FLAG_REG = 0x47 Q1 Q2 Q3 Q4
No-Operati No-Opera No-Operat
No-Operat on tion ion
ion
Example HERE BTFSC FLAG,1
FALSE GOTO PROCESS_CODE
TRUE •
•
•
Before Instruction
PC = address HERE
After Instruction
BSF Bit Set f if FLAG = 0,
Syntax: [label] BSF f,b PC = address TRUE
if FLAG=1,
Operands: 0 f 127 PC = address FALSE
0b7
Operation: 1 (f)
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit 'b' in register 'f' is set.
Words: 1
Cycles: 1
Q Cycle Activity: Q1 Q2 Q3 Q4
Decode Read Process Write
register data register 'f'
'f'
Example BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30430D-page 58 1996-2013 Microchip Technology Inc.
PIC16F8X
BTFSS Bit Test f, Skip if Set CALL Call Subroutine
Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k
Operands: 0 f 127 Operands: 0 k 2047
0b
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