PIC16F688
Data Sheet
14-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
2007 Microchip Technology Inc. DS41203D
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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DS41203D-page ii 2007 Microchip Technology Inc.
PIC16F688
14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU: Low-Power Features:
Only 35 instructions to learn: Standby Current:
- All single-cycle instructions except branches - 50 nA @ 2.0V, typical
Operating speed: Operating Current:
- DC 20 MHz oscillator/clock input - 11 A @ 32 kHz, 2.0V, typical
- DC 200 ns instruction cycle - 220 A @ 4 MHz, 2.0V, typical
Interrupt capability Watchdog Timer Current:
8-level deep hardware stack - 1 A @ 2.0V, typical
Direct, Indirect and Relative Addressing modes
Peripheral Features:
Special Microcontroller Features:
12 I/O pins with individual direction control:
Precision Internal Oscillator: - High-current source/sink for direct LED drive
- Factory calibrated to 1% - Interrupt-on-change pin
- Software selectable frequency range of - Individually programmable weak pull-ups
8 MHz to 125 kHz - Ultra Low-Power Wake-up
- Software tunable
- Two-Speed Start-Up mode Analog Comparator module with:
- Crystal fail detect for critical applications - Two analog comparators
- Clock mode switching during operation for - Programmable On-chip Voltage Reference
power savings (CVREF) module (% of VDD)
- Comparator inputs and outputs externally
Power-Saving Sleep mode accessible
Wide operating voltage range (2.0V-5.5V)
Industrial and Extended temperature range A/D Converter:
Power-on Reset (POR) - 10-bit resolution and 8 channels
Power-up Timer (PWRT) and Oscillator Start-up
Timer0: 8-bit timer/counter with 8-bit
Timer (OST) programmable prescaler
Brown-out Reset (BOR) with software control
Enhanced Timer1:
option - 16-bit timer/counter with prescaler
Enhanced Low-Current Watchdog Timer (WDT) - External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode as
with on-chip oscillator (software selectable nomi- Timer1 oscillator if INTOSC mode selected
nal 268 seconds with full prescaler) with software
enable Enhanced USART Module:
Multiplexed Master Clear with weak pull-up or - Supports RS-485, RS-232, and LIN 1.2
input only pin - Auto-Baud Detect
Programmable code protection - Auto-wake-up on Start bit
High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance In-Circuit Serial ProgrammingTM (ICSPTM) via two
- 1,000,000 write EEPROM endurance pins
- Flash/Data EEPROM retention: > 40 years
Program Data Memory
Memory
Device I/O 10-bit A/D Comparators Timers
PIC16F688 Flash (ch) 8/16-bit
(words) SRAM EEPROM
1/1
4096 (bytes) (bytes)
256 256 12 8 2
2007 Microchip Technology Inc. DS41203D-page 1
PIC16F688
Pin Diagram (PDIP, SOIC, TSSOP)
14-pin PDIP, SOIC, TSSOP
VDD 1 14 VSS
RA5/T1CKI/OSC1/CLKIN RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 2 13 RA1/AN1/C1IN-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RA3/MCLR/VPP 3 PIC16F688 12 RC0/AN4/C2IN+
RC5/RX/DT RC1/AN5/C2IN-
4 11 RC2/AN6
RC4/C2OUT/TX/CK
RC3/AN7 5 10
6 9
7 8
TABLE 1: PIC16F688 14-PIN SUMMARY (PDIP, SOIC, TSSOP)
I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic
RA0 13 AN0/ULPWU C1IN+ -- -- IOC Y ICSPDAT
Y VREF/ICSPCLK
RA1 12 AN1 C1IN- -- -- IOC Y
Y(1) --
RA2 11 AN2 C1OUT T0CKI -- IOC/INT Y MCLR/VPP
Y OSC2/CLKOUT
RA3 4 -- -- -- -- IOC -- OSC1/CLKIN
--
RA4 3 AN3 -- T1G -- IOC -- --
-- --
RA5 2 -- -- T1CKI -- IOC -- --
-- --
RC0 10 AN4 C2IN+ -- -- -- -- --
-- --
RC1 9 AN5 C2IN- -- -- -- VDD
VSS
RC2 8 AN6 -- -- -- --
RC3 7 AN7 -- -- -- --
C2OUT
RC4 6 -- -- TX/CK --
--
RC5 5 -- -- -- RX/DT --
--
--1 -- -- -- --
-- 14 -- -- -- --
Note 1: Pull-up activated only with external MCLR configuration.
DS41203D-page 2 2007 Microchip Technology Inc.
PIC16F688
Pin Diagram (QFN)
16-pin QFN
VDD NC NC VSS
RA5/T1CKI/OSC1/CLKIN 16 15 14 13 RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA4/AN3/T1G/OSC2/CLKOUT 12 RA1/AN1/C1IN-/VREF/ICSPCLK
1 RA2/AN2/T0CKI/INT/C1OUT
RA3/MCLR/VPP RC0/AN4/C2IN+
RC5/RX/DT 2 PIC16F688 11
3 10
4 9
5 6 7 8
RC4/C2OUT/TX/CK RC3/AN7 RC2/AN6 RC1/AN5/C2IN-
TABLE 2: PIC16F688 16-PIN SUMMARY (QFN)
I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic
RA0 12 AN0/ULPWU C1IN+ -- -- IOC Y ICSPDAT
IOC Y VREF/ICSPCLK
RA1 11 AN1 C1IN- -- -- IOC/INT Y
IOC Y(1) --
RA2 10 AN2 C1OUT T0CKI -- IOC Y MCLR/VPP
IOC Y OSC2/CLKOUT
RA3 3 -- -- -- -- -- -- OSC1/CLKIN
-- --
RA4 2 AN3 -- T1G -- -- -- --
-- -- --
RA5 1 -- -- T1CKI -- -- -- --
-- -- --
RC0 9 AN4 C2IN+ -- -- -- -- --
C2IN- -- -- --
RC1 8 AN5 -- -- -- -- VDD
-- -- -- VSS
RC2 7 AN6 -- -- -- NC
C2OUT NC
RC3 6 AN7 -- -- --
--
RC4 5 -- -- -- TX/CK
--
RC5 4 -- -- RX/DT
-- 16 -- -- --
-- 13 -- -- --
-- 14 -- -- --
-- 15 -- -- -- --
Note 1: Pull-up activated only with external MCLR configuration.
2007 Microchip Technology Inc. DS41203D-page 3
PIC16F688
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization .................................................................................................................................................................. 7
3.0 Clock Sources ........................................................................................................................................................................... 21
4.0 I/O Ports .................................................................................................................................................................................... 33
5.0 Timer0 Module .......................................................................................................................................................................... 45
6.0 Timer1 Module with Gate Control.............................................................................................................................................. 49
7.0 Comparator Module................................................................................................................................................................... 55
8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 65
9.0 Data EEPROM and Flash Program Memory Control ................................................................................................................ 77
10.0 Enhanced Universal Asynchronous Receiver Transmitter (EUSART) ...................................................................................... 83
11.0 Special Features of the CPU ................................................................................................................................................... 109
12.0 Instruction Set Summary ......................................................................................................................................................... 129
13.0 Development Support .............................................................................................................................................................. 139
14.0 Electrical Specifications........................................................................................................................................................... 143
15.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 163
16.0 Packaging Information............................................................................................................................................................. 185
Appendix A: Data Sheet Revision History......................................................................................................................................... 191
Appendix B: Migrating from other PIC Devices .............................................................................................................................. 191
Index ................................................................................................................................................................................................. 193
On-line Support ................................................................................................................................................................................. 197
Systems Information and Upgrade Hot Line ..................................................................................................................................... 197
Reader Response ............................................................................................................................................................................. 198
Product Identification System............................................................................................................................................................ 199
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DS41203D-page 4 2007 Microchip Technology Inc.
PIC16F688
1.0 DEVICE OVERVIEW
The PIC16F688 is covered by this data sheet. It is
available in 14-pin PDIP, SOIC, TSSOP and QFN
packages. Figure 1-1 shows a block diagram of the
PIC16F688 device. Table 1-1 shows the pinout
description.
FIGURE 1-1: PIC16F688 BLOCK DIAGRAM
Configuration INT 8 PORTA
Data Bus
Flash 13 RA0
4k x 14 Program Counter RA1
Program RA2
Memory 8-Level Stack RAM RA3
(13 bit) 256 bytes RA4
Program 14 RA5
Bus File
Instruction Reg Registers
RAM Addr 9
Addr MUX
Indirect PORTC
Direct Addr 7 8
Addr RC0
RC1
FSR Reg RC2
RC3
STATUS Reg RC4
8 RC5
3 MUX
Instruction Power-up ALU
Decode & Timer 8
Control Oscillator W Reg
Start-up Timer
OSC1/CLKIN Timing
Generation Power-on
Reset
OSC2/CLKOUT
Watchdog
Timer
Brown-out
Reset
Internal RX/DT TX/CK
Oscillator
Block
T1G MCLR VDD VSS
T1CKI Timer0 Timer1 EUSART
T0CKI
Analog-to-Digital Converter 2 EEDAT
Analog Comparators 8 256 bytes
and Reference DATA
EEPROM
EEADDR
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
2007 Microchip Technology Inc. DS41203D-page 5
PIC16F688
TABLE 1-1: PIC16F688 PINOUT DESCRIPTION
Name Function Input Output Description
Type Type
RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
AN0 AN -- A/D Channel 0 input
C1IN+ AN -- Comparator 1 input
ICSPDAT TTL CMOS Serial Programming Data I/O
ULPWU AN -- Ultra Low-Power Wake-up input
RA1/AN1/C1IN-/VREF/ICSPCLK RA1 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
AN1 AN -- A/D Channel 1 input
C1IN- AN -- Comparator 1 input
VREF AN -- External Voltage Reference for A/D
ICSPCLK ST -- Serial Programming Clock
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS PORTA I/O w/prog pull-up and interrupt-on-change
AN2 AN -- A/D Channel 2 input
T0CKI ST -- Timer0 clock input
INT ST -- External Interrupt
C1OUT -- CMOS Comparator 1 output
RA3/MCLR/VPP RA3 TTL -- PORTA input with interrupt-on-change
MCLR ST -- Master Clear w/internal pull-up
VPP HV -- Programming voltage
RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
AN3 AN -- A/D Channel 3 input
T1G ST -- Timer1 gate
OSC2 -- XTAL Crystal/Resonator
CLKOUT -- CMOS FOSC/4 output
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS PORTA I/O w/prog pull-up and interrupt-on-change
T1CKI ST -- Timer1 clock
OSC1 XTAL -- Crystal/Resonator
CLKIN ST -- External clock input/RC oscillator connection
RC0/AN4/C2IN+ RC0 TTL CMOS PORTC I/O
AN4 AN -- A/D Channel 4 input
C2IN+ AN Comparator 2 input
RC1/AN5/C2IN- RC1 TTL CMOS PORTC I/O
AN5 AN -- A/D Channel 5 input
C2IN- AN Comparator 2 input
RC2/AN6 RC2 TTL CMOS PORTC I/O
AN6 AN -- A/D Channel 6 input
RC3/AN7 RC3 TTL CMOS PORTC I/O
AN7 AN -- A/D Channel 7 input
RC4/C2OUT/TX/CK RC4 TTL CMOS PORTC I/O
C2OUT -- CMOS Comparator 2 output
TX -- CMOS USART asynchronous output
CK ST CMOS USART asynchronous clock
RC5/RX/DT RC5 TTL CMOS Port C I/O
RX ST CMOS USART asynchronous input
DT ST CMOS USART asynchronous data
VSS VSS Power -- Ground reference
VDD VDD Power -- Positive supply
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OC = Open collector output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HV = High Voltage XTAL = Crystal
DS41203D-page 6 2007 Microchip Technology Inc.
PIC16F688
2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization
2.1 Program Memory Organization The data memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
The PIC16F688 has a 13-bit program counter capable and the Special Function Registers (SFR). Bits RP0
of addressing a 4K x 14 program memory space. Only and RP1 are bank select bits.
the first 4K x 14 (0000h-01FFF) for the PIC16F688 is
physically implemented. Accessing a location above RP1 RP0
these boundaries will cause a wraparound within the
first 4K x 14 space. The Reset vector is at 0000h and 0 0 Bank 0 is selected
the interrupt vector is at 0004h (see Figure 2-1).
0 1 Bank 1 is selected
1 0 Bank 2 is selected
FIGURE 2-1: PROGRAM MEMORY MAP 1 1 Bank 3 is selected
AND STACK FOR THE
CALL, RETURN PIC16F688 Each bank extends up to 7Fh (128 bytes). The lower
RETFIE, RETLW locations of each bank are reserved for the Special
PC<12:0> Function Registers. Above the Special Function Regis-
ters are the General Purpose Registers, implemented
13 as static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Stack Level 1 Function Registers from one bank are mirrored in
Stack Level 2 another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER
FILE
Stack Level 8 0000h The register file is organized as 256 x 8 in the
Reset Vector PIC16F688. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see Section 2.4 "Indirect Addressing, INDF and
FSR Registers").
Interrupt Vector 0004h 2.2.2 SPECIAL FUNCTION REGISTERS
On-chip Program 0005h
The Special Function Registers are registers used by
Memory 01FFh the CPU and peripheral functions for controlling the
02000h desired operation of the device (see Tables 2-1, 2-2,
Wraps to 0000h-07FFh 2-3 and 2-4). These registers are static RAM.
1FFFh
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the "core" are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
2007 Microchip Technology Inc. DS41203D-page 7
PIC16F688
FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 180h
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
06h 86h 106h 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
BAUDCTL 11h ANSEL 91h 111h 191h
SPBRGH 12h 92h 112h 192h
SPBRG 13h 93h 113h 193h
RCREG 14h 94h 114h 194h
TXREG 15h WPUA 95h 115h 195h
TXSTA 16h IOCA 96h 116h 196h
RCSTA 17h EEDATH 97h 117h 197h
WDTCON 18h EEADRH 98h 118h 198h
CMCON0 19h VRCON 99h 119h 199h
CMCON1 1Ah EEDAT 9Ah 11Ah 19Ah
1Bh EEADR 9Bh 11Bh 19Bh
1Ch EECON1 9Ch 11Ch 19Ch
11Dh
1Dh EECON2(1) 9Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General General
Purpose Purpose Purpose
Register Register Register
96 Bytes 80 Bytes 80 Bytes
7Fh EFh accesses 16Fh 1EFh
Bank 0 Bank 0 170h 1F0h
accesses F0h Bank 2 17Fh accesses 1FFh
Bank 0
Bank 0 FFh
Bank 3
Bank 1
Unimplemented data memory locations, read as `0'.
Note 1: Not a physical register.
DS41203D-page 8 2007 Microchip Technology Inc.
PIC16F688
TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Page
POR/BOR
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
01h TMR0 Timer0 Module's register xxxx xxxx 45, 117
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 19, 117
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 13, 117
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
05h PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 117
06h -- Unimplemented -- --
07h PORTC -- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
08h -- Unimplemented -- --
09h -- Unimplemented -- --
---0 0000 19, 117
0Ah PCLATH -- -- -- Write Buffer for upper 5 bits of Program Counter 0000 000x 15, 117
T0IE
0Bh INTCON GIE PEIE INTE RAIE T0IF INTF RAIF(2)
0Ch PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 17, 117
0Dh -- Unimplemented -- --
Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 48, 117
0Eh TMR1L Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 48, 117
0Fh TMR1H
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 51, 117
11h BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 94, 117
12h SPBRGH USART Baud Rate High Generator 0000 0000 95, 117
13h SPBRG USART Baud Rate Generator 0000 0000 95, 117
14h RCREG USART Receive Register 0000 0000 87, 117
15h TXREG USART Transmit Register 0000 0000 87, 117
16h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 92, 117
17h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 93, 117
18h WDTCON -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 124, 117
19h CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61, 117
1Ah CMCON1 -- -- -- -- -- -- T1GSS C2SYNC ---- --10 62, 117
1Bh -- Unimplemented -- --
1Ch -- Unimplemented -- --
1Dh -- Unimplemented -- --
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 72, 117
1Fh ADCON0 ADFM VCFG -- CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 71, 117
Legend: = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
2: mismatched exists.
2007 Microchip Technology Inc. DS41203D-page 9
PIC16F688
TABLE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Page
POR/BOR
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 19, 117
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 13, 117
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
85h TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117
86h -- Unimplemented -- --
87h TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117
88h -- Unimplemented -- --
89h -- Unimplemented -- --
8Ah PCLATH -- -- -- Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117
8Bh INTCON
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF(3) 0000 000x 15, 117
8Ch PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 16, 117
8Dh -- Unimplemented -- --
8Eh PCON -- -- ULPWUE SBOREN -- -- POR BOR --01 --qq 18, 117
8Fh OSCCON -- IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 22, 118
90h OSCTUNE -- -- -- TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 26, 118
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 34, 118
92h -- Unimplemented -- --
93h -- Unimplemented -- --
94h -- Unimplemented -- --
95h WPUA(2) -- -- WPUA5 WPUA4 -- WPUA2 WPUA1 WPUA0 --11 -111 35, 118
96h IOCA -- -- IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 35, 118
97h EEDATH -- -- EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 78, 118
98h EEADRH -- -- -- -- EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 78, 118
99h VRCON VREN -- VRR -- VR3 VR2 VR1 VR0 0-0- 0000 63, 118
9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 78, 118
9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 78, 118
9Ch EECON1 EEPGD -- -- -- WRERR WREN WR RD x--- x000 79, 118
9Dh EECON2 EEPROM Control 2 Register (not a physical register) ---- ---- 77, 118
9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 72, 118
9Fh ADCON1 -- ADCS2 ADCS1 ADCS0 -- -- -- -- -000 ---- 71, 118
Legend: = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
2: MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
3: mismatched exists.
DS41203D-page 10 2007 Microchip Technology Inc.
PIC16F688
TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Page
POR/BOR
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
101h TMR0 Timer0 Module's register xxxx xxxx 45, 117
102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 19, 117
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 13, 117
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
105h PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 117
106h -- Unimplemented -- --
107h PORTC -- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
108h -- Unimplemented -- --
109h -- Unimplemented -- --
10Ah PCLATH -- -- -- Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117
10Bh INTCON
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF(2) 0000 000x 15, 117
10Ch -- Unimplemented -- --
10Dh -- Unimplemented -- --
10Eh -- Unimplemented -- --
10Fh -- Unimplemented -- --
110h -- Unimplemented -- --
111h -- Unimplemented -- --
112h -- Unimplemented -- --
113h -- Unimplemented -- --
114h -- Unimplemented -- --
115h -- Unimplemented -- --
116h -- Unimplemented -- --
117h -- Unimplemented -- --
118h -- Unimplemented -- --
119h -- Unimplemented -- --
11Ah -- Unimplemented -- --
11Bh -- Unimplemented -- --
11Ch -- Unimplemented -- --
11Dh -- Unimplemented -- --
11Eh -- Unimplemented -- --
11Fh -- Unimplemented -- --
Legend: = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
2: mismatched exists.
2007 Microchip Technology Inc. DS41203D-page 11
PIC16F688
TABLE 2-4: PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Page
POR/BOR
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14, 117
182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 19, 117
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 13, 117
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
185h TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 33, 117
186h -- Unimplemented -- --
187h TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 42, 117
188h -- Unimplemented -- --
189h -- Unimplemented -- --
18Ah PCLATH -- -- -- Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117
18Bh INTCON
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF(2) 0000 000x 15, 117
18Ch -- Unimplemented -- --
18Dh -- Unimplemented -- --
190h -- Unimplemented -- --
191h -- Unimplemented -- --
192h -- Unimplemented -- --
193h -- Unimplemented -- --
194h -- Unimplemented -- --
195h -- Unimplemented -- --
196h -- Unimplemented -- --
19Ah -- Unimplemented -- --
19Bh -- Unimplemented -- --
199h -- Unimplemented -- --
19Ah -- Unimplemented -- --
19Bh -- Unimplemented -- --
19Ch -- Unimplemented -- --
19Dh -- Unimplemented -- --
19Eh -- Unimplemented -- --
19Fh -- Unimplemented -- --
Legend: = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
DS41203D-page 12 2007 Microchip Technology Inc.
PIC16F688
2.2.2.1 STATUS Register It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The STATUS register, shown in Register 2-1, contains: STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
the arithmetic status of the ALU ing any Status bits (see Section 12.0 "Instruction Set
the Reset status Summary").
the bank select bits for data memory (SRAM)
Note 1: Bits IRP and RP1 of the STATUS register
The STATUS register can be the destination for any are not used by the PIC16F688 and
instruction, like any other register. If the STATUS should be maintained as clear. Use of
register is the destination for an instruction that affects these bits is not recommended, since this
the Z, DC or C bits, then the write to these three bits is may affect upward compatibility with
disabled. These bits are set or cleared according to the future products.
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the 2: The C and DC bits operate as a Borrow
STATUS register as destination may be different than and Digit Borrow out bit, respectively, in
intended. subtraction.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as `000u u1uu' (where u = unchanged).
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC(1) C(1)
bit 7 bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
bit 6-5 1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 4
bit 3 RP<1:0>: Register Bank Select bits (used for direct addressing)
bit 2 00 = Bank 0 (00h-7Fh)
bit 1 01 = Bank 1 (80h-FFh)
bit 0 10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
2007 Microchip Technology Inc. DS41203D-page 13
PIC16F688
2.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
The OPTION register is a readable and writable by setting PSA bit of the OPTION register
register, which contains various control bits to to `1'. See Section 5.1.3 "Software
configure: Programmable Prescaler".
Timer0/WDT prescaler
External RA2/INT interrupt
Timer0
Weak pull-ups on PORTA
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 RAPU: PORTA Pull-up Enable bit
bit 6 1 = PORTA pull-ups are disabled
bit 5 0 = PORTA pull-ups are enabled by individual PORT latch values
bit 4
bit 3 INTEDG: Interrupt Edge Select bit
bit 2-0 1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
T0CS: Timer0 Clock Source Select bit
1 = Transition on RA2/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
DS41203D-page 14 2007 Microchip Technology Inc.
PIC16F688
2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
The INTCON register is a readable and writable its corresponding enable bit or the global
register, which contains the various enable and flag bits enable bit, GIE of the INTCON register.
for TMR0 register overflow, PORTA change and User software should ensure the appropri-
external RA2/INT pin interrupts. ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF
bit 7 bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 RAIE: PORTA Change Interrupt Enable bit(1)
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0 = None of the PORTA <5:0> pins have changed state
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
2007 Microchip Technology Inc. DS41203D-page 15
PIC16F688
2.2.2.4 PIE1 Register Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 3 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 2 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
bit 1 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
DS41203D-page 16 2007 Microchip Technology Inc.
PIC16F688
2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
The PIR1 register contains the interrupt flag bits, as its corresponding enable bit or the global
shown in Register 2-5. enable bit, GIE bit of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 3 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 2 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 1 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
2007 Microchip Technology Inc. DS41203D-page 17
PIC16F688
2.2.2.6 PCON Register
The Power Control (PCON) register (see Register 2-6)
contains flag bits to differentiate between a:
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
REGISTER 2-6: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
--
bit 7 -- ULPWUE SBOREN(1) -- -- POR BOR
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5
ULPWUE: Ultra Low-Power Wake-up Enable bit
bit 4 1 = Ultra low-power wake-up enabled
0 = Ultra low-power wake-up disabled
bit 3-2 SBOREN: Software BOR Enable bit(1)
bit 1 1 = BOR enabled
0 = BOR disabled
bit 0
Unimplemented: Read as `0'
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
DS41203D-page 18 2007 Microchip Technology Inc.
2.3 PCL and PCLATH PIC16F688
The Program Counter (PC) is 13 bits wide. The low byte 2.3.2 STACK
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not The PIC16F688 family has an 8-level x 13-bit wide
directly readable or writable and comes from PCLATH. hardware stack (see Figure 2-1). The stack space is
On any Reset, the PC is cleared. Figure 2-3 shows the not part of either program or data space and the Stack
two situations for the loading of the PC. The upper Pointer is not readable or writable. The PC is PUSHed
example in Figure 2-3 shows how the PC is loaded on a onto the stack when a CALL instruction is executed or
write to PCL (PCLATH<4:0> PCH). The lower exam- an interrupt causes a branch. The stack is POPed in
ple in Figure 2-3 shows how the PC is loaded during a the event of a RETURN, RETLW or a RETFIE
CALL or GOTO instruction (PCLATH<4:3> PCH). instruction execution. PCLATH is not affected by a
PUSH or POP operation.
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PCH PCL push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
12 87 0 Instruction with so on).
PC 8 PCL as
Note 1: There are no Status bits to indicate stack
PCLATH<4:0> Destination overflow or stack underflow conditions.
5
ALU Result 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
PCLATH that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
PCH PCL instructions or the vectoring to an
12 11 10 0 interrupt address.
PC GOTO, CALL
87
11
2 PCLATH<4:3> OPCODE<10:0>
PCLATH
2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, "Implementing a Table Read"
(DS00556).
2007 Microchip Technology Inc. DS41203D-page 19
PIC16F688
2.4 Indirect Addressing, INDF and A simple program to clear RAM location 20h-2Fh using
FSR Registers indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing EXAMPLE 2-1: INDIRECT ADDRESSING
the INDF register will cause indirect addressing.
MOVLW 0x20 ;initialize pointer
Indirect addressing is possible by using the INDF MOVWF FSR ;to RAM
register. Any instruction using the INDF register NEXT CLRF INDF ;clear INDF register
actually accesses data pointed to by the File Select INCF FSR ;inc pointer
Register (FSR). Reading INDF itself indirectly will BTFSS FSR,4 ;all done?
produce 00h. Writing to the INDF register indirectly GOTO NEXT ;no clear next
results in a no operation (although Status bits may be CONTINUE ;yes continue
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-4.
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F688
Direct Addressing Indirect Addressing
RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0
Bank Select Location Select Bank Select Location Select
00 01 10 11
00h 180h
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figure 2-2.
DS41203D-page 20 2007 Microchip Technology Inc.
PIC16F688
3.0 OSCILLATOR MODULE (WITH The Oscillator module can be configured in one of eight
FAIL-SAFE CLOCK MONITOR) clock modes.
3.1 Overview 1. EC External clock with I/O on OSC2/CLKOUT.
2. LP 32 kHz Low-Power Crystal mode.
The Oscillator module has a wide variety of clock 3. XT Medium Gain Crystal or Ceramic
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor- Resonator Oscillator mode.
mance and minimizing power consumption. Figure 3-1 4. HS High Gain Crystal or Ceramic Resonator
illustrates a block diagram of the Oscillator module.
mode.
Clock sources can be configured from external 5. RC External Resistor-Capacitor (RC) with
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the FOSC/4 output on OSC2/CLKOUT.
system clock source can be configured from one of two 6. RCIO External Resistor-Capacitor (RC) with
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include: I/O on OSC2/CLKOUT.
7. INTOSC Internal oscillator with FOSC/4 output
Selectable system clock source between external
or internal via software. on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO Internal oscillator with I/O on
Two-Speed Start-Up mode, which minimizes
latency between external oscillator start-up and OSC1/CLKIN and OSC2/CLKOUT.
code execution.
Clock Source modes are configured by the FOSC<2:0>
Fail-Safe Clock Monitor (FSCM) designed to bits in the Configuration Word register (CONFIG). The
detect a failure of the external clock source (LP, internal clock can be generated from two internal
XT, HS, EC or RC modes) and switch oscillators. The HFINTOSC is a calibrated high-
automatically to the internal oscillator. frequency oscillator. The LFINTOSC is an uncalibrated
low-frequency oscillator.
FIGURE 3-1: PIC MCU CLOCK SOURCE BLOCK DIAGRAM
External Oscillator FOSC<2:0>
Sleep (Configuration Word Register)
SCS<0>
(OSCCON Register)
OSC2 LP, XT, HS, RC, RCIO, EC
OSC1
Postscaler IRCF<2:0> System Clock
MUX(OSCCON Register) (CPU and Peripherals)
MUX
8 MHz INTOSC
111
Internal Oscillator
4 MHz
HFINTOSC 110
8 MHz
2 MHz
LFINTOSC 101
31 kHz
1 MHz
100
500 kHz
011
250 kHz
010
125 kHz
001
31 kHz
000
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
2007 Microchip Technology Inc. DS41203D-page 21
PIC16F688
3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
Frequency selection bits (IRCF)
Frequency Status bits (HTS, LTS)
System clock control bits (OSTS, SCS)
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
-- IRCF2 IRCF1 IRCF0 OSTS(1) HTS
bit 7 LTS SCS
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as `0'
bit 6-4
IRCF<2:0>: Internal Oscillator Frequency Select bits
bit 3 111 = 8 MHz
bit 2 110 = 4 MHz (default)
bit 1 101 = 2 MHz
bit 0 100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
HTS: HFINTOSC Status bit (High Frequency 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
LTS: LFINTOSC Stable bit (Low Frequency 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the Configuration Word
Note 1: Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
DS41203D-page 22 2007 Microchip Technology Inc.
PIC16F688
3.3 Clock Source Modes 3.4 External Clock Modes
Clock Source modes can be classified as external or 3.4.1 OSCILLATOR START-UP TIMER (OST)
internal.
If the Oscillator module is configured for LP, XT or HS
External Clock modes rely on external circuitry for modes, the Oscillator Start-up Timer (OST) counts
the clock source. Examples are: Oscillator mod- 1024 oscillations from OSC1. This occurs following a
ules (EC mode), quartz crystal resonators or Power-on Reset (POR) and when the Power-up Timer
ceramic resonators (LP, XT and HS modes) and (PWRT) has expired (if configured), or a wake-up from
Resistor-Capacitor (RC) mode circuits. Sleep. During this time, the program counter does not
increment and program execution is suspended. The
Internal clock sources are contained internally OST ensures that the oscillator circuit, using a quartz
within the Oscillator module. The Oscillator crystal resonator or ceramic resonator, has started and
module has two internal oscillators: the 8 MHz is providing a stable system clock to the Oscillator
High-Frequency Internal Oscillator (HFINTOSC) module. When switching between clock sources, a
and the 31 kHz Low-Frequency Internal Oscillator delay is required to allow the new clock to stabilize.
(LFINTOSC). These oscillator delays are shown in Table 3-1.
The system clock can be selected between external or In order to minimize latency between external oscillator
internal clock sources via the System Clock Select start-up and code execution, the Two-Speed Clock
(SCS) bit of the OSCCON register. See Section 3.6 Start-up mode can be selected (see Section 3.7 "Two-
"Clock Switching" for additional information. Speed Clock Start-up Mode").
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
Switch From Switch To Frequency Oscillator Delay
Sleep/POR LFINTOSC 31 kHz Oscillator Warm-Up Delay (TWARM)
HFINTOSC 125 kHz to 8 MHz
Sleep/POR 2 instruction cycles
LFINTOSC (31 kHz) EC, RC DC 20 MHz 1 cycle of each
EC, RC DC 20 MHz 1024 Clock Cycles (OST)
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1 s (approx.)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz
3.4.2 EC MODE FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When Clock from OSC1/CLKIN
operating in this mode, an external clock source is Ext. System PIC MCU
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin I/O OSC2/CLKOUT(1)
connections for EC mode.
Note 1: Alternate pin functions are listed in
The Oscillator Start-up Timer (OST) is disabled when Section 1.0 "Device Overview".
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
2007 Microchip Technology Inc. DS41203D-page 23
PIC16F688
3.4.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
The LP, XT and HS modes support the use of quartz user should consult the manufacturer data
crystal resonators or ceramic resonators connected to sheets for specifications and recommended
OSC1 and OSC2 (Figure 3-3). The mode selects a low, application.
medium or high gain setting of the internal inverter-
amplifier to support various resonator types and speed. 2: Always verify oscillator performance over
the VDD and temperature range that is
LP Oscillator mode selects the lowest gain setting of expected for the application.
the internal inverter-amplifier. LP mode current con-
sumption is the least of the three modes. This mode is 3: For oscillator design assistance, reference
best suited to drive resonators with a low drive level the following Microchip Applications Notes:
specification, for example, tuning fork type crystals.
This mode is designed to drive only 32.768 kHz tuning- AN826, "Crystal Oscillator Basics and
fork type crystals (watch crystals). Crystal Selection for rfPIC and PIC
Devices" (DS00826)
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode AN849, "Basic PIC Oscillator Design"
current consumption is the medium of the three modes. (DS00849)
This mode is best suited to drive resonators with a
medium drive level specification. AN943, "Practical PIC Oscillator
Analysis and Design" (DS00943)
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption AN949, "Making Your Oscillator Work"
is the highest of the three modes. This mode is best (DS00949)
suited for resonators that require a high drive setting.
FIGURE 3-4: CERAMIC RESONATOR
Figure 3-3 and Figure 3-4 show typical circuits for OPERATION
quartz crystal and ceramic resonators, respectively. (XT OR HS MODE)
FIGURE 3-3: QUARTZ CRYSTAL PIC MCU
OPERATION (LP, XT OR
HS MODE) OSC1/CLKIN
C1 To Internal
PIC MCU Logic
RP(3) RF(2) Sleep
C1 OSC1/CLKIN To Internal C2 Ceramic RS(1) OSC2/CLKOUT
RF(2) Logic Resonator
Quartz
Crystal Sleep
C2 RS(1) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M).
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
DS41203D-page 24 2007 Microchip Technology Inc.
3.4.4 EXTERNAL RC MODES PIC16F688
The external Resistor-Capacitor (RC) modes support 3.5 Internal Clock Modes
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while The Oscillator module has two independent, internal
keeping costs to a minimum when clock accuracy is not oscillators that can be configured or selected as the
required. There are two modes: RC and RCIO. system clock source.
In RC mode, the RC circuit connects to OSC1. OSC2/ 1. The HFINTOSC (High-Frequency Internal
CLKOUT outputs the RC oscillator frequency divided Oscillator) is factory calibrated and operates at
by 4. This signal may be used to provide a clock for 8 MHz. The frequency of the HFINTOSC can be
external circuitry, synchronization, calibration, test or user-adjusted via software using the OSCTUNE
other application requirements. Figure 3-5 shows the register (Register 3-2).
external RC mode connections.
2. The LFINTOSC (Low-Frequency Internal
FIGURE 3-5: EXTERNAL RC MODES Oscillator) is uncalibrated and operates at 31 kHz.
VDD PIC MCU Internal The system clock speed can be selected via software
REXT OSC1/CLKIN Clock using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
CEXT OSC2/CLKOUT(1)
VSS The system clock can be selected between external or
internal clock sources via the System Clock Selection
FOSC/4 or (SCS) bit of the OSCCON register. See Section 3.6
I/O(2) "Clock Switching" for more information.
Recommended values: 10 k REXT 100 k, <3V 3.5.1 INTOSC AND INTOSCIO MODES
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
Note 1: Alternate pin functions are listed in the device is programmed using the oscillator selection
2: Section 1.0 "Device Overview". or the FOSC<2:0> bits in the Configuration Word
Output depends upon RC or RCIO clock mode. register (CONFIG). See Section 11.0 "Special
Features of the CPU" for more information.
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin. In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
The RC oscillator frequency is a function of the supply internal oscillator frequency divided by 4. The CLKOUT
voltage, the resistor (REXT) and capacitor (CEXT) values signal may be used to provide a clock for external
and the operating temperature. Other factors affecting circuitry, synchronization, calibration, test or other
the oscillator frequency are: application requirements.
threshold voltage variation In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
component tolerances are available for general purpose I/O.
packaging variations in capacitance
3.5.2 HFINTOSC
The user also needs to take into account variation due
to tolerance of external RC components used. The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 8 MHz internal clock source. The
2007 Microchip Technology Inc. frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 "Frequency Select Bits (IRCF)" for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by setting the IRCF<2:0>
bits of the OSCCON register 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to `1' or enable Two-Speed Start-up by setting
the IESO bit in the Configuration Word register
(CONFIG) to `1'.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
DS41203D-page 25
PIC16F688
3.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
The HFINTOSC is factory calibrated but can be frequency. Code execution continues during this shift.
adjusted in software by writing to the OSCTUNE There is no indication that the shift has occurred.
register (Register 3-2).
OSCTUNE does not affect the LFINTOSC frequency.
The default value of the OSCTUNE register is `0'. The Operation of features that depend on the LFINTOSC
value is a 5-bit two's complement number. clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
-- TUN1 TUN0
bit 7 -- -- TUN4 TUN3 TUN2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as `0'
bit 4-0
TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
10000 = Minimum frequency
DS41203D-page 26 2007 Microchip Technology Inc.
PIC16F688
3.5.3 LFINTOSC 3.5.5 HF AND LF INTOSC CLOCK
SWITCH TIMING
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source. When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
The output of the LFINTOSC connects to a postscaler down to save power (see Figure 3-6). If this is the case,
and multiplexer (see Figure 3-1). Select 31 kHz, via there is a delay after the IRCF<2:0> bits of the
software, using the IRCF<2:0> bits of the OSCCON OSCCON register are modified before the frequency
register. See Section 3.5.4 "Frequency Select Bits selection takes place. The LTS and HTS bits of the
(IRCF)" for more information. The LFINTOSC is also the OSCCON register will reflect the current active status
frequency for the Power-up Timer (PWRT), Watchdog of the LFINTOSC and HFINTOSC oscillators. The
Timer (WDT) and Fail-Safe Clock Monitor (FSCM). timing of a frequency selection is as follows:
The LFINTOSC is enabled by selecting 31 kHz 1. IRCF<2:0> bits of the OSCCON register are
(IRCF<2:0> bits of the OSCCON register = 000) as the modified.
system clock source (SCS bit of the OSCCON
register = 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up
delay is started.
Two-Speed Start-up IESO bit of the Configuration
Word register = 1 and IRCF<2:0> bits of the 3. Clock switch circuitry waits for a falling edge of
OSCCON register = 000 the current clock.
Power-up Timer (PWRT) 4. CLKOUT is held low and the clock switch
Watchdog Timer (WDT) circuitry waits for a rising edge in the new clock.
Fail-Safe Clock Monitor (FSCM)
5. CLKOUT is now connected with the new clock.
The LF Internal Oscillator (LTS) bit of the OSCCON LTS and HTS bits of the OSCCON register are
register indicates whether the LFINTOSC is stable or updated as required.
not.
6. Clock switch is complete.
See Figure 3-1 for more details.
3.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
The output of the 8 MHz HFINTOSC and 31 kHz the new frequency is selected. This is because the old
LFINTOSC connects to a postscaler and multiplexer and new frequencies are derived from the HFINTOSC
(see Figure 3-1). The Internal Oscillator Frequency via the postscaler and multiplexer.
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of Start-up delay specifications are located in the
eight frequencies can be selected via software: Section 14.0 "Electrical Specifications", under the
AC Specifications (Oscillator Module).
8 MHz
4 MHz (Default after Reset)
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz (LFINTOSC)
Note: Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to `110' and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.
2007 Microchip Technology Inc. DS41203D-page 27
PIC16F688
FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING
HF LF(1)
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <2:0> 0 =0
System Clock
Note 1: When going from LF to HF.
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC 2-cycle Sync Running
LFINTOSC 0 =0
IRCF <2:0>
System Clock
LFINTOSC HFINTOSC
LFINTOSC Start-up Time 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled
HFINTOSC Running
IRCF <2:0> =0 0
System Clock
DS41203D-page 28 2007 Microchip Technology Inc.
PIC16F688
3.6 Clock Switching When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
The system clock source can be switched between enabled (see Section 3.4.1 "Oscillator Start-up Timer
external and internal clock sources via software using (OST)"). The OST will suspend program execution until
the System Clock Select (SCS) bit of the OSCCON 1024 oscillations are counted. Two-Speed Start-up
register. mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
3.6.1 SYSTEM CLOCK SELECT (SCS) BIT counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
The System Clock Select (SCS) bit of the OSCCON execution switches to the external oscillator.
register selects the system clock source that is used for
the CPU and peripherals.
When the SCS bit of the OSCCON register = 0, 3.7.1 TWO-SPEED START-UP MODE
the system clock source is determined by CONFIGURATION
configuration of the FOSC<2:0> bits in the
Configuration Word register (CONFIG). Two-Speed Start-up mode is configured by the
following settings:
When the SCS bit of the OSCCON register = 1, IESO (of the Configuration Word register) = 1;
the system clock source is chosen by the internal Internal/External Switchover bit (Two-Speed Start-
oscillator frequency selected by the IRCF<2:0> up mode enabled).
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always SCS (of the OSCCON register) = 0.
cleared.
FOSC<2:0> bits in the Configuration Word
Note: Any automatic clock switch, which may register (CONFIG) configured for LP, XT or HS
occur from Two-Speed Start-up or Fail-Safe mode.
Clock Monitor, does not update the SCS bit
of the OSCCON register. The user can Two-Speed Start-up mode is entered after:
monitor the OSTS bit of the OSCCON
register to determine the current system Power-on Reset (POR) and, if enabled, after
clock source. Power-up Timer (PWRT) has expired, or
Wake-up from Sleep.
3.6.2 OSCILLATOR START-UP TIME-OUT If the external clock oscillator is configured to be
STATUS (OSTS) BIT anything other than LP, XT or HS mode, then Two-
Speed Start-up is disabled. This is because the external
The Oscillator Start-up Time-out Status (OSTS) bit of clock oscillator does not require any stabilization time
the OSCCON register indicates whether the system after POR or an exit from Sleep.
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration 3.7.2 TWO-SPEED START-UP
Word register (CONFIG), or from the internal clock SEQUENCE
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS 1. Wake-up from Power-on Reset or Sleep.
modes. 2. Instructions begin execution by the internal
3.7 Two-Speed Clock Start-up Mode oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external 3. OST enabled to count 1024 clock cycles.
oscillator start-up and code execution. In applications 4. OST timed out, wait for falling edge of the
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up internal oscillator.
time from the time spent awake and can reduce the 5. OSTS is set.
overall power consumption of the device. 6. System clock held low until the next falling edge
This mode allows the application to wake-up from of new clock (LP, XT or HS mode).
Sleep, perform a few instructions using the INTOSC 7. System clock is switched to external clock
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable. source.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
2007 Microchip Technology Inc. DS41203D-page 29
PIC16F688
3.7.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
HFINTOSC
TOST
OSC1 0 1 1022 1023
OSC2
Program Counter PC - N PC PC + 1
System Clock
DS41203D-page 30 2007 Microchip Technology Inc.
PIC16F688
3.8 Fail-Safe Clock Monitor 3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled,
the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the
FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected
Configuration Word register (CONFIG). The FSCM is in OSCCON. When the OST times out, the Fail-Safe
applicable to all external oscillator modes (LP, XT, HS, condition is cleared and the device will be operating
EC, RC and RCIO). from the external clock source. The Fail-Safe condition
must be cleared before the OSFIF flag can be cleared.
FIGURE 3-8: FSCM BLOCK DIAGRAM 3.8.4 RESET OR WAKE-UP FROM SLEEP
External Clock Monitor The FSCM is designed to detect an oscillator failure
Clock Latch after the Oscillator Start-up Timer (OST) has expired.
SQ The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
LFINTOSC 64 RQ RC Clock modes so that the FSCM will be active as
Oscillator soon as the Reset or wake-up has completed. When
488 Hz Clock the FSCM is enabled, the Two-Speed Start-up is also
31 kHz (~2 ms) Failure enabled. Therefore, the device will always be executing
(~32 s) Detected code while the OST is operating.
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
Sample Clock during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
3.8.1 FAIL-SAFE DETECTION amount of time, the user should check the
OSTS bit of the OSCCON register to verify
The FSCM module detects a failed oscillator by the oscillator start-up and that the system
comparing the external oscillator to the FSCM sample clock switchover has successfully
clock. The sample clock is generated by dividing the completed.
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
3.8.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
2007 Microchip Technology Inc. DS41203D-page 31
PIC16F688
FIGURE 3-9: FSCM TIMING DIAGRAM
Sample Clock Oscillator
Failure
System
Clock Failure
Detected
Output
Clock Monitor Output
(Q)
OSCFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR
all other
Resets(1)
CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 -- --
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
OSCCON -- IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
OSCTUNE -- -- -- TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, = unimplemented locations read as `0'. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (CONFIG) for operation of all register bits.
2:
DS41203D-page 32 2007 Microchip Technology Inc.
PIC16F688
4.0 I/O PORTS Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the
There are as many as twelve general purpose I/O pins PORT data latch. RA3 reads `0' when MCLRE = 1.
available. Depending on which peripherals are enabled,
some or all of the pins may not be available as general The TRISA register controls the direction of the
purpose I/O. In general, when a peripheral is enabled, PORTA pins, even when they are being used as analog
the associated pin may not be used as a general inputs. The user must ensure the bits in the TRISA
purpose I/O pin. register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
4.1 PORTA and the TRISA Registers `0'.
PORTA is a 6-bit wide, bidirectional port. The Note: The ANSEL and CMCON0 registers must
corresponding data direction register is TRISA. Setting be initialized to configure an analog
a TRISA bit (= 1) will make the corresponding PORTA channel as a digital input. Pins configured
pin an input (i.e., put the corresponding output driver in as analog inputs will read `0'.
a High-Impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e., EXAMPLE 4-1: INITIALIZING PORTA
put the contents of the output latch on the selected pin).
The exception is RA3, which is input only and its TRISA BANKSEL PORTA ;
bit will always read as `1'. Example 4-1 shows how to CLRF PORTA ;Init PORTA
initialize PORTA. MOVLW 07h ;Set RA<2:0> to
MOVWF CMCON0 ;digital I/O
Reading the PORTA register reads the status of the BANKSEL ANSEL ;
pins, whereas writing to it will write to the PORT latch. CLRF ANSEL ;digital I/O
All write operations are read-modify-write operations. MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<5:4,1:0>
;as outputs
REGISTER 4-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0
--
bit 7 -- RA5 RA4 RA3 RA2 RA1 RA0
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0
RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
-- TRISA2 TRISA1 TRISA0
bit 7 -- TRISA5 TRISA4 TRISA3
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0
TRISA<5:0>: PORTA Tri-State Control bits
Note 1: 1 = PORTA pin configured as an input (tri-stated)
2: 0 = PORTA pin configured as an output
TRISA<3> always reads `1'.
TRISA<5:4> always reads `1' in XT, HS and LP Oscillator modes.
2007 Microchip Technology Inc. DS41203C-page 33
PIC16F688
4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE
Every PORTA pin on the PIC16F688 has an interrupt- Each of the PORTA pins is individually configurable as
on-change option and a weak pull-up option. PORTA an interrupt-on-change pin. Control bits IOCAx enable
also provides an Ultra Low-Power Wake-up option. The or disable the interrupt function for each pin. Refer to
next three sections describe these functions. Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
4.2.1 ANSEL REGISTER
For enabled interrupt-on-change pins, the values are
The ANSEL register is used to configure the Input compared with the old value latched on the last read of
mode of an I/O pin to analog. Refer to Register 4-3. PORTA. The `mismatch' outputs of the last read are
Setting the appropriate ANSEL bit high will cause all OR'd together to set the PORTA Change Interrupt Flag
digital reads on the pin to be read as `0' and allow bit (RAIF) in the INTCON register.
analog functions on the pin to operate correctly.
This interrupt can wake the device from Sleep. The user,
The state of the ANSEL bits has no affect on digital in the Interrupt Service Routine, clears the interrupt by:
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode a) Any read or write of PORTA. This will end the
will be analog. This can cause unexpected behavior mismatch condition, then
when executing read-modify-write instructions on the
affected port. b) Clear the flag bit RAIF.
4.2.2 WEAK PULL-UPS A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
Each of the PORTA pins, except RA3, has an allow flag bit RAIF to be cleared. The latch holding the
individually configurable internal weak pull-up. Control last read value is not affected by a MCLR nor BOR
bits WPUAx enable or disable each pull-up. Refer to Reset. After these Resets, the RAIF flag will continue
Register 4-4. Each weak pull-up is automatically turned to be set if a mismatch is present.
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the Note: If a change on the I/O pin should occur
RAPU bit of the OPTION register. A weak pull-up is when the read operation is being executed
automatically enabled for RA3 when configured as (start of the Q2 cycle), then the RAIF
MCLR and disabled when RA3 is an I/O. There is no interrupt flag may not get set.
software control of the MCLR pull-up.
REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-0 ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
DS41203C-page 34 2007 Microchip Technology Inc.
PIC16F688
REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
-- WPUA1 WPUA0
bit 7 -- WPUA5 WPUA4 -- WPUA2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-4
WPUA<5:4>: Weak Pull-up Control bits
bit 3 1 = Pull-up enabled
bit 2-0 0 = Pull-up disabled
Unimplemented: Read as `0'
WPUA<2:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads `1' in XT, HS and LP OSC modes.
REGISTER 4-5: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
-- IOCA1 IOCA0
bit 7 -- IOCA5 IOCA4 IOCA3 IOCA2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0
IOCA<5:0>: Interrupt-on-change PORTA Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads `1' in XT, HS and LP OSC modes.
2007 Microchip Technology Inc. DS41203C-page 35
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4.2.4 ULTRA LOW-POWER WAKE-UP EXAMPLE 4-2: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
The Ultra Low-Power Wake-up (ULPWU) on RA0
allows a slow falling voltage to generate an interrupt- BANKSEL PORTA ;
on-change on RA0 without excess current consump- BSF
tion. The mode is selected by setting the ULPWUE bit MOVLW PORTA,0 ;Set RA0 data latch
of the PCON register. This enables a small current sink MOVWF
which can be used to discharge a capacitor on RA0. BANKSEL H'7' ;Turn off
BCF
To use this feature, the RA0 pin is configured to output BANKSEL CMCON0 ; comparators
`1' to charge the capacitor, interrupt-on-change for RA0 BCF
is enabled, and RA0 is configured as an input. The CALL ANSEL ;
ULPWUE bit is set to begin the discharge and a SLEEP BSF
instruction is performed. When the voltage on RA0 BSF ANSEL,0 ;RA0 to digital I/O
drops below VIL, an interrupt will be generated which BSF
will cause the device to wake-up. Depending on the MOVLW TRISA ;
state of the GIE bit of the INTCON register, the device MOVWF
will either jump to the interrupt vector (0004h) or SLEEP TRISA,0 ;Output high to
execute the next instruction when the interrupt event NOP
occurs. See Section 4.2.3 "INTERRUPT-ON- CapDelay ; charge capacitor
CHANGE" and Section 11.3.3 "PORTA Interrupt" for
more information. PCON,ULPWUE ;Enable ULP Wake-up
This feature provides a low-power technique for IOCA,0 ;Select RA0 IOC
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC TRISA,0 ;RA0 to input
circuit on RA0. See Example 4-2 for initializing the
Ultra Low-Power Wake-up module. B'10001000' ;Enable interrupt
The series resistor provides overcurrent protection for INTCON ; and clear flag
the RA0 pin and can allow for software calibration of the
time-out. (see Figure 4-1). A timer can be used to ;Wait for IOC
measure the charge time and discharge time of the
capacitor. The charge time can then be adjusted to ;
provide the desired interrupt delay. This technique will
compensate for the affects of temperature, voltage and
component accuracy. The Ultra Low-Power Wake-up
peripheral can also be configured as a simple
programmable low voltage detect or temperature sensor.
Note: For more information, refer to Application
Note AN879, "Using the Microchip Ultra
Low-Power Wake-up Module"
(DS00879).
DS41203C-page 36 2007 Microchip Technology Inc.
PIC16F688
4.2.5 PIN DESCRIPTIONS AND 4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
DIAGRAMS
Figure 4-1 shows the diagram for this pin. The RA0 pin
Each PORTA pin is multiplexed with other functions. is configurable to function as one of the following:
The pins and their combined functions are briefly
described here. For specific information about individ- a general purpose I/O
ual functions such as the comparator or the A/D, refer an analog input for the A/D
to the appropriate section in this data sheet. an analog input to the comparator
an analog input to the Ultra Low-Power Wake-up
In-Circuit Serial ProgrammingTM data
FIGURE 4-1: BLOCK DIAGRAM OF RA0
Data Bus DQ Analog(1) VDD
CK Q Input Mode Weak
WR
WPUDA RAPU
RD
WPUDA VDD
WR DQ I/O PIN
PORTA CK Q VSS
-
+ VT
WR DQ IULP
TRISA CK Q
Vss
01 ULPWUE
RD Analog(1)
TRISA Input Mode
RD DQ QD
PORTA CK Q
WR
IOCA
EN Q3
RD QD
IOCA EN
Interrupt-on-
Change
RD PORTA
To Comparator
To A/D Converter
Note 1: Comparator mode and ANSEL determines analog Input mode.
2007 Microchip Technology Inc. DS41203C-page 37
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4.2.5.2 RA1/AN1/C1IN-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following: is configurable to function as one of the following:
a general purpose I/O a general purpose I/O
an analog input for the A/D an analog input for the A/D
an analog input to the comparator the clock input for Timer0
a voltage reference input for the A/D an external edge triggered interrupt
In-Circuit Serial ProgrammingTM clock a digital output from the comparator
FIGURE 4-2: BLOCK DIAGRAM OF RA1 FIGURE 4-3: BLOCK DIAGRAM OF RA2
Data Bus Analog(1) VDD Data Bus Analog(1)
DQ Input Mode Weak DQ Input Mode
WR CK Q RAPU WR CK Q VDD
WPUA WPUA
Weak
RD RD
WPUA WPUA RAPU
DQ VDD DQ C1OUT
CK Q Enable
I/O pin
VDD
VSS
WR CK Q Analog(1) WR C1OUT 1
PORTA Input Mode PORTA 0
I/O pin
WR DQ WR DQ VSS
TRISA CK Q TRISA CK Q Analog(1)
Input Mode
RD RD
TRISA TRISA
RD RD
PORTA PORTA
DQ DQ
WR CK Q QD WR CK Q QD
IOCA IOCA
EN Q3 EN Q3
RD QD RD QD
IOCA IOCA EN
EN Interrupt-on-
Interrupt-on- change
change
RD PORTA RD PORTA
To Comparator
To A/D Converter To Timer0
To INT
Note 1: Comparator mode and ANSEL determines analog To A/D Converter
Input mode.
Note 1: Analog Input mode is based upon ANSEL.
DS41203C-page 38 2007 Microchip Technology Inc.
PIC16F688
4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-4 shows the diagram for this pin. The RA3 pin Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following: is configurable to function as one of the following:
a general purpose input a general purpose I/O
as Master Clear Reset with weak pull-up an analog input for the A/D
a Timer1 gate input
FIGURE 4-4: BLOCK DIAGRAM OF RA3 a crystal/resonator connection
a clock output
VDD
MCLRE Weak FIGURE 4-5: BLOCK DIAGRAM OF RA4
Data Bus Reset MCLRE Analog(3)
Input Mode CLK(1)
RD VSS MCLRE Input Data Bus
pin DQ Modes
TRISA QD VSS VDD
EN
RD Q3 WR CK Q Weak
PORTA QD WPUA
EN
DQ RD RAPU
RD PORTA WPUA Oscillator
WR CK Q Circuit
IOCA
OSC1
RD CLKOUT VDD
IOCA Enable
I/O pin
Interrupt-on- WR DQ Fosc/4 1 VSS
change PORTA CK Q
0
WR DQ
TRISA CK Q CLKOUT
Enable
RD
TRISA INTOSC/
RC/EC(2)
CLKOUT
Enable
Analog(3)
Input Mode
RD
PORTA
DQ
WR CK Q QD
IOCA
EN Q3
RD QD
IOCA
Interrupt-on- EN
change RD PORTA
To T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: Analog Input mode is ANSEL.
2007 Microchip Technology Inc. DS41203C-page 39
PIC16F688 FIGURE 4-6: BLOCK DIAGRAM OF RA5
4.2.5.6 RA5/T1CKI/OSC1/CLKIN Data Bus INTOSC
Figure 4-6 shows the diagram for this pin. The RA5 pin DQ Mode
is configurable to function as one of the following: TMR1LPEN(1)
a general purpose I/O WR CK Q VDD
a Timer1 clock input WPUA
a crystal/resonator connection Weak
a clock input
RAPU
RD
WPUA
Oscillator
Circuit
OSC2 VDD
WR DQ
PORTA CK Q
WR DQ I/O pin
TRISA CK Q VSS
RD INTOSC
TRISA Mode
RD (2)
PORTA
DQ
WR CK Q QD
IOCA
EN Q3
RD
IOCA
QD
EN
Interrupt-on-
change
RD PORTA
To Timer1 or CLKGEN
Note 1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
DS41203C-page 40 2007 Microchip Technology Inc.
PIC16F688
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111
1111 1111
CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
--0u --uu
PCON -- -- ULPWUE SBOREN -- -- POR BOR --01 --qq 0000 000x
--00 0000
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x
1111 1111
IOCA -- -- IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000
--x0 x000
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 --11 1111
--11 -111
PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000
TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
WPUA -- -- WPUA5 WPUA4 -- WPUA2 WPUA1 WPUA0 --11 -111
Legend: x = unknown, u = unchanged, = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
2007 Microchip Technology Inc. DS41203C-page 41
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4.3 PORTC EXAMPLE 4-3: INITIALIZING PORTC
PORTC is a general purpose I/O port consisting of 6 BANKSEL PORTC ;
bidirectional pins. The pins can be configured for either CLRF PORTC ;Init PORTC
digital I/O or analog input to A/D converter or compara- MOVLW 07h ;Set RC<4,1:0> to
tor. For specific information about individual functions MOVWF CMCON0 ;digital I/O
such as the EUSART or the A/D converter, refer to the BANKSEL ANSEL ;
appropriate section in this data sheet. CLRF ANSEL ;digital I/O
MOVLW 0Ch ;Set RC<3:2> as inputs
Note: The ANSEL and CMCON0 registers must MOVWF TRISC ;and set RC<5:4,1:0>
be initialized to configure an analog ;as outputs
channel as a digital input. Pins configured
as analog inputs will read `0'.
REGISTER 4-6: PORTC: PORTC REGISTER
U-0 U-0 R/W-x R/W-x R/W-0 R/W-0 R/W-0 R/W-0
-- RC3 RC2 RC1 RC0
bit 7 -- RC5 RC4
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0
RC<5:0>: PORTC I/O Pin bit
1 = PORTC pin is > VIH
0 = PORTC pin is < VIL
REGISTER 4-7: TRISC: PORTC TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
-- TRISC2 TRISC1 TRISC0
bit 7 -- TRISC5 TRISC4 TRISC3
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0
TRISC<5:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
DS41203C-page 42 2007 Microchip Technology Inc.
PIC16F688
4.3.1 RC0/AN4/C2IN+ 4.3.3 RC2/AN6
Figure 4-8 shows the diagram for this pin. The RC2 is
Figure 4-7 shows the diagram for this pin. The RC0 is configurable to function as one of the following:
configurable to function as one of the following: a general purpose I/O
an analog input for the A/D Converter
a general purpose I/O
an analog input for the A/D Converter 4.3.4 RC3/AN7
an analog input to the comparator Figure 4-8 shows the diagram for this pin. The RC3 is
configurable to function as one of the following:
4.3.2 RC1/AN5/C2IN- a general purpose I/O
an analog input for the A/D Converter
Figure 4-7 shows the diagram for this pin. The RC1 is
configurable to function as one of the following:
a general purpose I/O
an analog input for the A/D Converter FIGURE 4-8: BLOCK DIAGRAM OF RC2
an analog input to the comparator AND RC3
Data Bus
FIGURE 4-7: BLOCK DIAGRAM OF RC0
AND RC1
Data Bus
DQ VDD
DQ VDD WR CK Q
CK Q I/O Pin PORTC I/O Pin
VSS
WR VSS DQ
PORTC CK Q
DQ WR
CK Q TRISC
WR RD Analog Input
TRISC TRISC Mode(1)
RD Analog Input RD
TRISC Mode(1) PORTC
RD To A/D Converter
PORTC
To Comparators Note 1: Analog Input mode comes from ANSEL.
To A/D Converter
Note 1: Analog Input mode is based upon Comparator mode
and ANSEL.
2007 Microchip Technology Inc. DS41203C-page 43
PIC16F688
4.3.5 RC4/C2OUT/TX/CK 4.3.6 RC5/RX/DT
Figure 4-9 shows the diagram for this pin. The RC4 is The RC5 is configurable to function as one of the
configurable to function as one of the following: following:
a general purpose I/O a general purpose I/O
a digital output from the comparator a digital I/O for the EUSART
a digital I/O for the EUSART
FIGURE 4-10: BLOCK DIAGRAM OF RC5
PIN
FIGURE 4-9: BLOCK DIAGRAM OF RC4
USART Select(1) Data Bus EUSART Out VDD
C2OUT EN D Enable I/O Pin
Q VSS
VDD WR CK Q EUSART 1
PORTC DT Out
EUSART I/O Pin
VSS 0
TX/CLKOUT 0
Data Bus 0 DQ
CK Q
C2OUT 1
1 WR
TRISC
DQ
WR CK Q RD
PORTC TRISC
WR DQ RD
TRISC CK Q PORTC
To EUSART RX/DT In
RD
TRISC
RD
PORTC
To EUSART CLK Input
Note 1: USART Select signals selects between port
data and peripheral output.
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
PORTC -- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 --xx 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
DS41203C-page 44 2007 Microchip Technology Inc.
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5.0 TIMER0 MODULE 5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer) 5.1.1 8-BIT TIMER MODE
Programmable internal or external clock source
Programmable external clock edge selection When used as a timer, the Timer0 module will
Interrupt on overflow increment every instruction cycle (without prescaler).
Figure 5-1 is a block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit of the
OPTION register to `0'.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
5.1.2 8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to `1'.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4 Data Bus
0 8
T0CKI 1 8-bit 1 TMR0
pin Prescaler Sync
0 2 Tcy Set Flag bit T0IF
T0SE T0CS on Overflow
0
1
PSA
WDTE 8
SWDTEN PSA
31 kHz PS<2:0> 1
INTOSC WDT
16-bit
Prescaler 16 Time-out
0
Watchdog
Timer PSA
WDTPS<3:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
2007 Microchip Technology Inc. DS41203D-page 45
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5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the
PRESCALER WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer EXAMPLE 5-2: CHANGING PRESCALER
(WDT), but not both simultaneously. The prescaler (WDT TIMER0)
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and
must be cleared to a `0'.
;prescaler
There are 8 prescaler options for the Timer0 module BANKSEL OPTION_REG ;
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register. MOVLW b'11110000' ;Mask TMR0 select and
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT ANDWF OPTION_REG,W ;prescaler bits
module.
IORLW b'00000011' ;Set prescale to 1:16
MOVWF OPTION_REG ;
The prescaler is not readable or writable. When 5.1.4 TIMER0 INTERRUPT
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler. Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
When the prescaler is assigned to WDT, a CLRWDT flag bit of the INTCON register is set every time the
instruction will clear the prescaler along with the WDT. TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
5.1.3.1 Switching Prescaler Between cleared in software. The Timer0 interrupt enable is the
Timer0 and WDT Modules T0IE bit of the INTCON register.
As a result of having the prescaler assigned to either Note: The Timer0 interrupt cannot wake the
Timer0 or the WDT, it is possible to generate an processor from Sleep since the timer is
unintended device Reset when switching prescaler frozen during Sleep.
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence 5.1.5 USING TIMER0 WITH AN
shown in Example 5-1, must be executed. EXTERNAL CLOCK
EXAMPLE 5-1: CHANGING PRESCALER When Timer0 is in Counter mode, the synchronization
(TIMER0 WDT) of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
BANKSEL TMR0 ; Q4 cycles of the internal phase clocks. Therefore, the
CLRWDT ;Clear WDT high and low periods of the external clock source must
CLRF TMR0 ;Clear TMR0 and meet the timing requirements as shown in
;prescaler Section 14.0 "Electrical Specifications".
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
b'11111000' ;
MOVLW OPTION_REG,W ;Mask prescaler
ANDWF b'00000101' ;bits
IORLW OPTION_REG ;Set WDT prescaler
MOVWF ;to 1:32
DS41203D-page 46 2007 Microchip Technology Inc.
PIC16F688
REGISTER 5-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 RAPU: PORTA Pull-up Enable bit
bit 6 1 = PORTA pull-ups are disabled
bit 5 0 = PORTA pull-ups are enabled by individual PORT latch values
bit 4
bit 3 INTEDG: Interrupt Edge Select bit
bit 2-0 1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 11.5 "Watchdog Timer (WDT)" for more
information.
TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
TMR0 Timer0 Module Register INTE RAIE T0IF INTF xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE RAIF 0000 000x 0000 000x
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
2007 Microchip Technology Inc. DS41203D-page 47
PIC16F688
6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation
CONTROL
The Timer1 module is a 16-bit incrementing counter
The Timer1 module is a 16-bit timer/counter with the which is accessed through the TMR1H:TMR1L register
following features: pair. Writes to TMR1H or TMR1L directly update the
counter.
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source When used with an internal clock source, the module is
3-bit prescaler a timer. When used with an external clock source, the
Optional LP oscillator module can be used as either a timer or counter.
Synchronous or asynchronous operation
Timer1 gate (count enable) via comparator or 6.2 Clock Source Selection
T1G pin The TMR1CS bit of the T1CON register is used to select
Interrupt on overflow the clock source. When TMR1CS = 0, the clock source
Wake-up on overflow (external clock, is FOSC/4. When TMR1CS = 1, the clock source is
supplied externally.
Asynchronous mode only)
Clock Source TMR1CS Clock Source
Figure 6-1 is a block diagram of the Timer1 module. FOSC/4 0 FOSC/4
T1CKI pin 1 T1CKI pin
FIGURE 6-1: TIMER1 BLOCK DIAGRAM
TMR1GE T1GINV
TMR1ON
Set flag bit To C2 Comparator Module
TMR1IF on
Overflow TMR1(2) Timer1 Clock
0 Synchronized
TMR1H EN clock input
TMR1L
1
Oscillator (1) T1SYNC
1
OSC1/T1CKI FOSC/4 Synchronize(3)
OSC2/T1G Internal Prescaler det
1, 2, 4, 8
Clock 0 1
2
T1CKPS<1:0>
TMR1CS
INTOSC C2OUT 0
Without CLKOUT
T1OSCEN
T1GSS
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
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6.2.1 INTERNAL CLOCK SOURCE 6.5 Timer1 Operation in
Asynchronous Counter Mode
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples If control bit T1SYNC of the T1CON register is set, the
of TCY as determined by the Timer1 prescaler. external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
6.2.2 EXTERNAL CLOCK SOURCE phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
When the external clock source is selected, the Timer1 which will wake-up the processor. However, special
module may work as a timer or a counter. precautions in software are needed to read/write the
timer (see Section 6.5.1 "Reading and Writing
When counting, Timer1 is incremented on the rising Timer1 in Asynchronous Counter Mode").
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the Note: When switching from synchronous to
microcontroller system clock or run asynchronously. asynchronous operation, it is possible to
skip an increment. When switching from
If an external clock oscillator is needed (and the asynchronous to synchronous operation,
microcontroller is using the INTOSC without CLKOUT), it is possible to produce a single spurious
Timer1 can use the LP oscillator as a clock source. increment.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge. 6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
6.3 Timer1 Prescaler MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8 Reading TMR1H or TMR1L while the timer is running
divisions of the clock input. The T1CKPS bits of the from an external asynchronous clock will ensure a valid
T1CON register control the prescale counter. The read (taken care of in hardware). However, the user
prescale counter is not directly readable or writable; should keep in mind that reading the 16-bit timer in two
however, the prescaler counter is cleared upon a write to 8-bit values itself, poses certain problems, since the
TMR1H or TMR1L. timer may overflow between the reads.
6.4 Timer1 Oscillator For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
A low-power 32.768 kHz crystal oscillator is built-in contention may occur by writing to the timer registers,
between pins OSC1 (input) and OSC2 (amplifier while the register is incrementing. This may produce an
output). The oscillator is enabled by setting the unpredictable value in the TMR1H:TTMR1L register
T1OSCEN control bit of the T1CON register. The pair.
oscillator will continue to run during Sleep.
6.6 Timer1 Gate
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when Timer1 gate source is software configurable to be the
the primary system clock is derived from the internal T1G pin or the output of Comparator 2. This allows the
oscillator or when in LP oscillator mode. The user must device to directly time external events using T1G or
provide a software time delay to ensure proper oscilla- analog events using Comparator 2. See the CMCON1
tor start-up. register (Register 7-2) for selecting the Timer1 gate
source. This feature can simplify the software for a
TRISA5 and TRISA4 bits are set when the Timer1 Delta-Sigma A/D converter and many other applications.
oscillator is enabled. RA5 and RA4 bits read as `0' and For more information on Delta-Sigma A/D converters,
TRISA5 and TRISA4 bits read as `1'. see the Microchip web site (www.microchip.com).
Note: The oscillator requires a start-up and Note: TMR1GE bit of the T1CON register must
stabilization time before use. Thus, be set to use either T1G or C2OUT as the
T1OSCEN should be set and a suitable Timer1 gate source. See Register 7-2 for
delay observed prior to enabling Timer1. more information on selecting the Timer1
gate source.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
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6.7 Timer1 Interrupt 6.8 Timer1 Operation During Sleep
The Timer1 register pair (TMR1H:TMR1L) increments Timer1 can only operate during Sleep when setup in
to FFFFh and rolls over to 0000h. When Timer1 rolls Asynchronous Counter mode. In this mode, an external
over, the Timer1 interrupt flag bit of the PIR1 register is crystal or clock source can be used to increment the
set. To enable the interrupt on rollover, you must set counter. To set up the timer to wake the device:
these bits:
TMR1ON bit of the T1CON register must be set
Timer1 interrupt enable bit of the PIE1 register TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register PEIE bit of the INTCON register must be set
GIE bit of the INTCON register
The device will wake-up on an overflow and execute
The interrupt is cleared by clearing the TMR1IF bit in the next instruction. If the GIE bit of the INTCON
the Interrupt Service Routine. register is set, the device will call the Interrupt Service
Routine (0004h).
Note: The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
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6.9 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 T1GINV: Timer1 Gate Invert bit(1)
bit 6
1 = Timer1 gate is active high (Timer1 counts when gate is high)
bit 5-4 0 = Timer1 gate is active low (Timer1 counts when gate is low)
bit 3 TMR1GE: Timer1 Gate Enable bit(2)
bit 2 If TMR1ON = 0:
This bit is ignored
bit 1 If TMR1ON = 1:
bit 0 1 = Timer1 is on if Timer1 gate is active
0 = Timer1 is on
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored. LP oscillator is disabled.
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1
register, as a Timer1 gate source.
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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
CMCON1 -- -- -- -- -- -- T1GSS C2SYNC ---- --10
INTCON 00-- --10
PIE1 GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIR1 0000 0000
TMR1H EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
TMR1L uuuu uuuu
T1CON EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 uuuu uuuu
Legend: uuuu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
x = unknown, u = unchanged, = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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7.0 COMPARATOR MODULE 7.1 Comparator Overview
Comparators are used to interface analog circuits to a A comparator is shown in Figure 7-1 along with the
digital circuit by comparing two analog voltages and relationship between the analog input levels and the
providing a digital indication of their relative magnitudes. digital output. When the analog voltage at VIN+ is less
The comparators are very useful mixed signal building than the analog voltage at VIN-, the output of the
blocks because they provide analog functionality comparator is a digital low level. When the analog
independent of the program execution. The Analog voltage at VIN+ is greater than the analog voltage at
Comparator module includes the following features: VIN-, the output of the comparator is a digital high level.
Dual comparators FIGURE 7-1: SINGLE COMPARATOR
Multiple comparator configurations
Comparator outputs are available internally/exter- VIN+ +
nally Output
Programmable output polarity
Interrupt-on-change VIN-
Wake-up from Sleep
Timer1 gate (count enable) VIN-
Output synchronization to Timer1 clock input VIN+
Programmable voltage reference
Note: Only Comparator C2 can be linked to
Timer1.
Output
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
This device contains two comparators as shown in
Figure 7-2 and Figure 7-3. The comparators are not
independently configurable.
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FIGURE 7-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
MULTIPLEX C1INV To C1OUT pin
Port Pins C1
DQ To Data Bus
Set C1IF bit
Q1 EN RD CMCON0
DQ
Q3*RD CMCON0 EN
CL
Reset
Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).
2: Q1 is held high during Sleep mode.
FIGURE 7-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM
MULTIPLEX C2INV C2SYNC To Timer1 Gate
Port Pins C2 0 To C2OUT pin
1
DQ
Timer1
clock source(1)
DQ To Data Bus
Q1 EN RD CMCON0
Set C2IF bit
DQ
Q3*RD CMCON0 EN
CL
Reset
Note 1: Comparator output is latched on falling edge of Timer1 clock source.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
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7.1.1 ANALOG INPUT CONNECTION
CONSIDERATIONS
Note 1: When reading a PORT register, all pins
A simplified circuit for an analog input is shown in configured as analog inputs will read as a
Figure 7-4. Since the analog input pins share their con- `0'. Pins configured as digital inputs will
nection with a digital input, they have reverse biased convert as an analog input, according to
ESD protection diodes to VDD and VSS. The analog the input specification.
input, therefore, must be between VSS and VDD. If the
input voltage deviates from this range by more than 2: Analog levels on any pin defined as a
0.6V in either direction, one of the diodes is forward digital input, may cause the input buffer to
biased and a latch-up may occur. consume more current than is specified.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 7-4: ANALOG INPUT MODEL
VDD
Rs < 10K VT 0.6V RIC
AIN ILEAKAGE To ADC Input
500 nA
VA CPIN VT 0.6V
5 pF
Vss
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
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7.2 Comparator Configuration
There are eight modes of operation for the comparator.
The CM<2:0> bits of the CMCON0 register are used to
select these modes as shown in Figure 7-5. I/O lines
change as a function of the mode and are designated
as follows:
Analog function (A): digital input buffer is disabled
Digital function (D): comparator digital output,
overrides port function
Normal port function (I/O): independent of
comparator
The port pins denoted as "A" will read as a `0'
regardless of the state of the I/O pin or the I/O control
TRIS bit. Pins used as analog inputs should also have
the corresponding TRIS bit set to `1' to disable the
digital output driver. Pins denoted as "D" should have
the corresponding TRIS bit set to `0' to enable the
digital output driver.
Note: Comparator interrupts should be disabled
during a Comparator mode change to
prevent unintended interrupts.
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FIGURE 7-5: COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value) Two Independent Comparators
CM<2:0> = 000 CM<2:0> = 100
C1IN- A VIN- Off(1) C1IN- A VIN- C1OUT
C1IN+ A VIN+ C1 C1IN+ A VIN+ C1 C2OUT
Off(1)
C2IN- A VIN- Off(1) C2IN- A VIN-
C2IN+ A VIN+ C2 C2IN+ A VIN+ C2
Three Inputs Multiplexed to Two Comparators One Independent Comparator
CM<2:0> = 001 CM<2:0> = 101
C1IN- A CIS = 0 VIN- C1OUT C1IN- I/O VIN-
C1IN+ A CIS = 1 VIN+ C1 C1IN+ I/O VIN+ C1
C2IN- A VIN- C2OUT C2IN- A VIN- C2OUT
C2IN+ A VIN+ C2 C2IN+ A VIN+ C2
Four Inputs Multiplexed to Two Comparators Two Common Reference Comparators with Outputs
CM<2:0> = 010 CM<2:0> = 110
C1IN- A CIS = 0 VIN- C1IN- A VIN-
C1IN+ A CIS = 1 VIN+ C1 VIN+ C1
C1OUT
C1OUT
C1OUT(pin) D
C2IN- A CIS = 0 VIN- C2OUT C2IN- A VIN- C2OUT
C2IN+ A CIS = 1 VIN+ C2 C2IN+ A VIN+ C2
From CVREF Module C2OUT(pin) D
Two Common Reference Comparators Comparators Off (Lowest Power)
CM<2:0> = 011 CM<2:0> = 111
C1IN- A VIN- C1OUT C1IN- I/O VIN- Off(1)
C1IN+ I/O VIN+ C1 C1IN+ I/O VIN+ C1
C2IN- A VIN- C2OUT C2IN- I/O VIN- Off(1)
C2IN+ A VIN+ C2 C2IN+ I/O VIN+ C2
Legend: A = Analog Input, ports always reads `0' CIS = Comparator Input Switch (CMCON0<3>)
I/O = Normal port I/O D = Comparator Digital Output
Note 1: Reads as `0', unless CxINV = 1.
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7.3 Comparator Control
The CMCON0 register (Register 7-1) provides access
to the following comparator features:
Mode selection
Output state
Output polarity
Input switch
7.3.1 COMPARATOR OUTPUT STATE
Each comparator state can always be read internally
via the associated CxOUT bit of the CMCON0 register.
The comparator outputs are directed to the CxOUT
pins when CM<2:0> = 110. When this mode is
selected, the TRIS bits for the associated CxOUT pins
must be cleared to enable the output drivers.
7.3.2 COMPARATOR OUTPUT POLARITY
Inverting the output of a comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of a comparator output can be inverted by set-
ting the CxINV bits of the CMCON0 register. Clearing
CxINV results in a non-inverted output. A complete
table showing the output state versus input conditions
and the polarity bit is shown in Table 7-1.
TABLE 7-1: OUTPUT STATE VS. INPUT
CONDITIONS
Input Conditions CxINV CxOUT
VIN- > VIN+ 0 0
VIN- < VIN+ 0 1
VIN- > VIN+ 1 1
VIN- < VIN+ 1 0
Note: CxOUT refers to both the register bit and
output pin.
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7.3.3 COMPARATOR INPUT SWITCH 7.5 Comparator Interrupt Operation
The inverting input of the comparators may be switched The comparator interrupt flag is set whenever there is
between two analog pins in the following modes: a change in the output value of the comparator.
Changes are recognized by means of a mismatch
CM<2:0> = 001 (Comparator C1 only) circuit which consists of two latches and an exclusive-
CM<2:0> = 010 (Comparators C1 and C2) or gate (see Figure 7-2 and Figure 7-3). One latch is
updated with the comparator output level when the
In the above modes, both pins remain in analog mode CMCON0 register is read. This latch retains the value
regardless of which pin is selected as the input. The CIS until the next read of the CMCON0 register or the
bit of the CMCON0 register controls the comparator occurrence of a Reset. The other latch of the mismatch
input switch. circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
7.4 Comparator Response Time output change is clocked through the second latch on
the Q1 clock cycle. The mismatch condition will persist,
The comparator output is indeterminate for a period of holding the CxIF bit of the PIR1 register true, until either
time after the change of an input source or the selection the CMCON0 register is read or the comparator output
of a new reference voltage. This period is referred to as returns to the previous state.
the response time. The response time of the
comparator differs from the settling time of the voltage Note: A write operation to the CMCON0 register
reference. Therefore, both of these times must be will also clear the mismatch condition
considered when determining the total response time because all writes include a read
to a comparator input change. See the Comparator and operation at the beginning of the write
Voltage Reference specifications in Section 14.0 cycle.
"Electrical Specifications" for more details.
Software will need to maintain information about the
status of the comparator output to determine the actual
change that has occurred.
The CxIF bit of the PIR1 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to `0'. Since it is also possible to write a `1' to
this register, a simulated interrupt may be initiated.
The CxIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CxIF bit of the
PIR1 register will still be set if an interrupt condition
occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON0. This will end the
mismatch condition. See Figures 7-6 and 7-7
b) Clear the CxIF interrupt flag.
A persistent mismatch condition will preclude clearing
the CxIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CxIF bit to be
cleared.
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FIGURE 7-6: COMPARATOR 7.6 Operation During Sleep
INTERRUPT TIMING W/O
Q1 CMCON0 READ The comparator, if enabled before entering Sleep mode,
Q3 remains active during Sleep. The additional current
CIN+ TRT consumed by the comparator is shown separately in
COUT Section 14.0 "Electrical Specifications". If the
Set CMIF (level) reset by software comparator is not used to wake the device, power
CMIF consumption can be minimized while in Sleep mode by
turning off the comparator. The comparator is turned off
FIGURE 7-7: COMPARATOR by selecting mode CM<2:0> = 000 or CM<2:0> = 111
INTERRUPT TIMING WITH of the CMCON0 register.
CMCON0 READ
A change to the comparator output can wake-up the
Q1 device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE1 register
Q3 and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
CIN+ TRT executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
COUT execute the Interrupt Service Routine.
Set CMIF (level) 7.7 Effects of a Reset
CMIF reset by software A device Reset forces the CMCON0 and CMCON1
cleared by CMCON0 read registers to their Reset states. This forces the Compar-
ator module to be in the Comparator Reset mode
Note 1: If a change in the CM1CON0 register (CM<2:0> = 000). Thus, all comparator inputs are
(CxOUT) occurs when a read operation is analog inputs with the comparator disabled to consume
being executed (start of the Q2 cycle), the smallest current possible.
then the CxIF Interrupt Flag bit of the
PIR1 register may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 s for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
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REGISTER 7-1: CMCON0: COMPARATOR CONFIGURATION REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 C2OUT: Comparator 2 Output bit
bit 6
bit 5 When C2INV = 0:
bit 4 1 = C2 VIN+ > C2 VIN-
bit 3 0 = C2 VIN+ < C2 VIN-
bit 2-0 When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
CIS: Comparator Input Switch bit
When CM<2:0> = 010:
1 = C1IN+ connects to C1 VIN-
C2IN+ connects to C2 VIN-
0 = C1IN- connects to C1 VIN-
C2IN- connects to C2 VIN-
When CM<2:0> = 001:
1 = C1IN+ connects to C1 VIN-
0 = C1IN- connects to C1 VIN-
CM<2:0>: Comparator Mode bits (See Figure 7-5)
000 = Comparators off. CxIN pins are configured as analog
001 = Three inputs multiplexed to two comparators
010 = Four inputs multiplexed to two comparators
011 = Two common reference comparators
100 = Two independent comparators
101 = One independent comparator
110 = Two common reference comparators with outputs
111 = Comparators off. CxIN pins are configured as digital I/O
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7.8 Comparator C2 Gating Timer1 7.9 Synchronizing Comparator C2
Output to Timer1
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the The output of Comparator C2 can be synchronized with
CMCON1 register will enable Timer1 to increment Timer1 by setting the C2SYNC bit of the CMCON1
based on the output of Comparator C2. This requires register. When enabled, the comparator output is
that Timer1 is on and gating is enabled. See latched on the falling edge of the Timer1 clock source.
Section 6.0 "Timer1 Module with Gate Control" for If a prescaler is used with Timer1, the comparator
details. output is latched after the prescaling function. To
prevent a race condition, the comparator output is
It is recommended to synchronize Comparator C2 with latched on the falling edge of the Timer1 clock source
Timer1 by setting the C2SYNC bit when the comparator and Timer1 increments on the rising edge of its clock
is used as the Timer1 gate source. This ensures Timer1 source. Reference the comparator block diagrams
does not miss an increment if the comparator changes (Figure 7-2 and Figure 7-3) and the Timer1 Block
during an increment. Diagram (Figure 6-1) for more information.
REGISTER 7-2: CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
-- C2SYNC
bit 7 -- -- -- -- -- T1GSS
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as `0'
bit 1 T1GSS: Timer1 Gate Source Select bit(1)
bit 0 1 = Timer1 gate source is T1G pin (pin should be configured as digital input)
0 = Timer1 gate source is Comparator C2 output
C2SYNC: Comparator C2 Output Synchronization bit(2)
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
Note 1: Refer to Section 6.6 "Timer1 Gate".
2: Refer to Figure 7-3.
DS41203D-page 62 2007 Microchip Technology Inc.
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7.10 Comparator Voltage Reference EQUATION 7-1: CVREF OUTPUT VOLTAGE
The Comparator Voltage Reference module provides VRR = 1 (low range):
an internally generated voltage reference for the com- CVREF = (VR<3:0>/24) VDD
parators. The following features are available:
VRR = 0 (high range):
Independent from Comparator operation CVREF = (VDD/4) + (VR<3:0> VDD/32)
Two 16-level voltage ranges
Output clamped to VSS The full range of VSS to VDD cannot be realized due to
Ratiometric with VDD the construction of the module. See Figure 7-8.
The VRCON register (Figure 7-3) controls the Voltage 7.10.3 OUTPUT CLAMPED TO VSS
Reference module shown in Figure 7-8. The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
7.10.1 INDEPENDENT OPERATION VREN = 0
VRR = 1
The comparator voltage reference is independent of VR<3:0> = 0000
the comparator configuration. Setting the VREN bit of This allows the comparator to detect a zero-crossing
the VRCON register will enable the voltage reference. while not consuming additional CVREF module current.
7.10.2 OUTPUT VOLTAGE SELECTION 7.10.4 OUTPUT RATIOMETRIC TO VDD
The CVREF voltage reference has 2 ranges with 16 The comparator voltage reference is VDD derived and
voltage levels in each range. Range selection is therefore, the CVREF output changes with fluctuations in
controlled by the VRR bit of the VRCON register. The VDD. The tested absolute accuracy of the Comparator
16 levels are set with the VR<3:0> bits of the VRCON Voltage Reference can be found in Section 14.0
register. "Electrical Specifications".
The CVREF output voltage is determined by the following
equations:
REGISTER 7-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VR1 VR0
bit 7 -- VRR -- VR3 VR2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 VREN: CVREF Enable bit
1 = CVREF circuit powered on
bit 6 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 5
Unimplemented: Read as `0'
bit 4
bit 3-0 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
Unimplemented: Read as `0'
VR<3:0>: CVREF Value Selection bits (0 VR<3:0> 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
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FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R R R R R
VDD 8R VRR
VREN 16-1 Analog
CVREF to MUX
Comparator
15
Input 14
2
1
0
VR<3:0>(1)
VREN
VR<3:0> = 0000
VRR
Note 1: Care should be taken to ensure VREF remains
within the comparator common mode input
range. See Section 14.0 "Electrical Specifica-
tions" for more detail.
TABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CMCON0
CMCON1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
INTCON
PIE1 -- -- -- -- -- -- T1GSS C2SYNC ---- --10 ---- --10
PIR1
PORTA GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PORTC
TRISA EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
TRISC
VRCON EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
Legend:
-- -- RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000
-- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 --xx 0000
-- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
-- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
VREN -- VRR -- VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
x = unknown, u = unchanged, = unimplemented, read as `0'. Shaded cells are not used for comparator.
DS41203D-page 64 2007 Microchip Technology Inc.
PIC16F688
8.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 8-1 shows the block diagram of the ADC.
FIGURE 8-1: ADC BLOCK DIAGRAM
VDD
VREF VCFG = 0
VCFG = 1
RA0/AN0 000 A/D 10
RA1/AN1/VREF 001 GO/DONE
010 ADFM 0 = Left Justify
RA2/AN2 011 ADON 1 = Right Justify
RA4/AN3 100 VSS
RC0/AN4 101 10
RC1/AN5 110
RC2/AN6 111
RC3/AN7
CHS
ADRESH ADRESL
2007 Microchip Technology Inc. DS41203D-page 65
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8.1 ADC Configuration For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
When configuring and using the ADC the following Section 14.0 "Electrical Specifications" for more
functions must be considered: information. Table 8-1 gives examples of appropriate
ADC clock selections.
Port configuration
Channel selection Note: Unless using the FRC, any changes in the
ADC voltage reference selection system clock frequency will change the
ADC conversion clock source ADC clock frequency, which may
Interrupt control adversely affect the ADC result.
Results formatting
8.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding Port
section for more information.
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
8.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 8.2
"ADC Operation" for more information.
8.1.3 ADC VOLTAGE REFERENCE
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
8.1.4 CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 8-3.
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TABLE 8-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4
FOSC/8 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s
FOSC/16
FOSC/32 001 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3)
FOSC/64
101 800 ns(2) 2.0 s 4.0 s 16.0 s(3)
FRC
010 1.6 s 4.0 s 8.0 s(3) 32.0 s(3)
110 3.2 s 8.0 s(3) 16.0 s(3) 64.0 s(3)
x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 8-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
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8.1.5 INTERRUPTS 8.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit A/D Conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
Conversion. The ADC interrupt flag is the ADIF bit in of the ADCON0 register controls the output format.
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared in Figure 8-4 shows the two output formats.
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 8.1.5 "Interrupts" for more
information.
FIGURE 8-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as `0'
(ADFM = 1) MSB LSB
bit 7 bit 0
bit 7 bit 0
Unimplemented: Read as `0' 10-bit A/D Result
DS41203D-page 68 2007 Microchip Technology Inc.
8.2 ADC Operation PIC16F688
8.2.1 STARTING A CONVERSION 8.2.5 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
To enable the ADC module, the ADON bit of the perform an Analog-to-Digital Conversion:
ADCON0 register must be set to a `1'. Setting the GO/ 1. Configure Port:
DONE bit of the ADCON0 register to a `1' will start the
Analog-to-Digital Conversion. Disable pin output driver (See TRIS register)
Configure pin as analog
Note: The GO/DONE bit should not be set in the 2. Configure the ADC module:
same instruction that turns on the ADC. Select ADC conversion clock
Refer to Section 8.2.5 "A/D Conversion Configure voltage reference
Procedure". Select ADC input channel
Select result format
8.2.2 COMPLETION OF A CONVERSION Turn on ADC module
3. Configure ADC interrupt (optional):
When the conversion is complete, the ADC module will: Clear ADC interrupt flag
Enable ADC interrupt
Clear the GO/DONE bit Enable peripheral interrupt
Set the ADIF flag bit Enable global interrupt(1)
Update the ADRESH:ADRESL registers with new 4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
conversion result 6. Wait for ADC conversion to complete by one of
the following:
8.2.3 TERMINATING A CONVERSION Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The enabled)
ADRESH:ADRESL registers will not be updated with 7. Read ADC Result
the partially complete Analog-to-Digital Conversion 8. Clear the ADC interrupt flag (required if interrupt
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Addi- is enabled).
tionally, a 2 TAD delay is required before another acqui-
sition can be initiated. Following this delay, an input Note 1: The global interrupt can be disabled if the
acquisition is automatically started on the selected user is attempting to wake-up from Sleep
channel. and resume in-line code execution.
Note: A device Reset forces all registers to their 2: See Section 8.3 "A/D Acquisition
Reset state. Thus, the ADC module is Requirements".
turned off and any pending conversion is
terminated.
8.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
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EXAMPLE 8-1: A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B'01110000' ;ADC Frc clock
MOVWF ADCON1 ;
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
MOVLW B'10000001' ;Right justify,
MOVWF ADCON0 ;Vdd Vref, AN0, On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
DS41203D-page 70 2007 Microchip Technology Inc.
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8.2.6 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 8-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHS0 GO/DONE ADON
ADFM VCFG -- CHS2 CHS1
bit 0
bit 7
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
bit 6 1 = Right justified
bit 5 0 = Left justified
bit 4-2
VCFG: Voltage Reference bit
bit 1
bit 0 1 = VREF pin
0 = VDD
Unimplemented: Read as `0'
CHS<2:0>: Analog Channel Select bits
000 = AN0
001 = AN1
010 = AN2
011 = AN3
100 = AN4
101 = AN5
110 = AN6
111 = AN7
GO/DONE: A/D Conversion Status bit
1 = A/D Conversion cycle in progress. Setting this bit starts an A/D Conversion cycle.
This bit is automatically cleared by hardware when the A/D Conversion has completed.
0 = A/D Conversion completed/not in progress
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
REGISTER 8-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
-- ADCS2 ADCS1 ADCS0 -- -- -- --
bit 7 bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as `0'
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
bit 3-0 000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
Unimplemented: Read as `0'
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REGISTER 8-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 8-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 -- -- -- -- -- --
bit 7 bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
bit 5-0 Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
REGISTER 8-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
-- -- -- -- -- -- ADRES9 ADRES8
bit 7 bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 8-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41203D-page 72 2007 Microchip Technology Inc.
PIC16F688
8.3 A/D Acquisition Requirements can be started. To calculate the minimum acquisition
time, Equation 8-1 may be used. This equation
For the ADC to meet its specified accuracy, the charge assumes that 1/2 LSb error is used (1024 steps for the
holding capacitor (CHOLD) must be allowed to fully ADC). The 1/2 LSb error is the maximum error allowed
charge to the input channel voltage level. The Analog for the ADC to meet its specified resolution.
Input model is shown in Figure 8-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 8-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
EQUATION 8-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2s + TC + [(Temperature - 25C)(0.05s/C)]
The value for TC can be approximated with the following equations:
V A P P L IE D 1 2----0-1--4---7- = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
e-R---T--C-C-- = VCHOLD
VAPPLIED1
e -R---T-C--c- = V A P P L IE D 1 2---0--1-4---7-- ;combining [1] and [2]
VAPPLIED1
Solving for TC:
TC = CHOLD(RIC + RSS + RS) ln(1/2047)
= 10pF(1k + 7k + 10k) ln(0.0004885)
= 1.37s
Therefore:
TACQ = 2S + 1.37S + [(50C- 25C)(0.05S/C)]
= 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2007 Microchip Technology Inc. DS41203D-page 73
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FIGURE 8-4: ANALOG INPUT MODEL
Rs ANx VDD RIC 1k Sampling
VT = 0.6V Switch
SS Rss
VA CPIN VT = 0.6V I LEAKAGE CHOLD = 10 pF
500 nA VSS/VREF-
5 pF
6V
5V RSS
VDD 4V
Legend: CPIN = Input Capacitance
3V
VT = Threshold Voltage
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
Sampling Switch
SS = Sampling Switch
(k)
CHOLD = Sample/Hold Capacitance
FIGURE 8-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFhADC Output Code 1 LSB ideal
3FEh Full-Scale
3FDh 1 LSB ideal Transition
3FCh
3FBh Zero-Scale Analog Input Voltage
Transition VDD/VREF+
004h
003h
002h
001h
000h
VSS/VREF-
DS41203D-page 74 2007 Microchip Technology Inc.
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TABLE 8-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
ADCON0 ADFM VCFG -- CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000
ADCON1 -- ADCS2 ADCS1 ADCS0 -- -- -- -- -000 ---- -000 ----
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 --x0 x000
PORTC -- -- RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 --xx 0000
TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for ADC module.
2007 Microchip Technology Inc. DS41203D-page 75
PIC16F688
NOTES:
DS41203D-page 76 2007 Microchip Technology Inc.
9.0 DATA EEPROM AND FLASH PIC16F688
PROGRAM MEMORY
CONTROL 9.1 EEADR and EEADRH Registers
Data EEPROM memory is readable and writable and The EEADR and EEADRH registers can address up to
the Flash program memory is readable during normal a maximum of 256 bytes of data EEPROM or up to a
operation (full VDD range). These memories are not maximum of 4K words of program EEPROM.
directly mapped in the register file space. Instead, they
are indirectly addressed through the Special Function When selecting a program address value, the MSB of
Registers. There are six SFRs used to access these the address is written to the EEADRH register and the
memories: LSB is written to the EEADR register. When selecting a
data address value, only the LSB of the address is
EECON1 written to the EEADR register.
EECON2 9.1.1 EECON1 AND EECON2 REGISTERS
EEDAT EECON1 is the control register for EE memory
accesses.
EEDATH
Control bit EEPGD determines if the access will be a
EEADR program or data memory access. When clear, as it is
when reset, any subsequent operations will operate on
EEADRH the data memory. When set, any subsequent operations
will operate on the program memory. Program memory
When interfacing the data memory block, EEDAT holds can only be read.
the 8-bit data for read/write, and EEADR holds the
address of the EE data location being accessed. This Control bits RD and WR initiate read and write,
device has 256 bytes of data EEPROM with an address respectively. These bits cannot be cleared, only set, in
range from 0h to 0FFh. software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
When interfacing the program memory block, the WR bit in software prevents the accidental, premature
EEDAT and EEDATH registers form a 2-byte word that termination of a write operation.
holds the 14-bit data for read/write, and the EEADR
and EEADRH registers form a 2-byte word that holds The WREN bit, when set, will allow a write operation to
the 12-bit address of the EEPROM location being data EEPROM. On power-up, the WREN bit is clear.
accessed. This device has 4K words of program The WRERR bit is set when a write operation is inter-
EEPROM with an address range from 0h to 0FFFh. rupted by a MCLR or a WDT Time-out Reset during
The program memory allows one word reads. normal operation. In these situations, following Reset,
the user can check the WRERR bit and rewrite the
The EEPROM data memory allows byte read and write. location. The data and address will be unchanged in
A byte write automatically erases the location and the EEDAT and EEADR registers.
writes the new data (erase before write).
Interrupt flag bit EEIF of the PIR1 register is set when
The write time is controlled by an on-chip timer. The write is complete. It must be cleared in the software.
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of EECON2 is not a physical register. Reading EECON2
the device for byte or word operations. will read all `0's. The EECON2 register is used
exclusively in the data EEPROM write sequence.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory
and read the program memory. When code-protected,
the device programmer can no longer access data or
program memory.
2007 Microchip Technology Inc. DS41203D-page 77
PIC16F688
REGISTER 9-1: EEDAT: EEPROM DATA REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-0 EEDATn: Byte Value to Write to or Read from Data EEPROM bits
REGISTER 9-2: EEADR: EEPROM ADDRESS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-0 EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program memory
REGISTER 9-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
-- EEDATH1 EEDATH0
bit 7 -- EEDATH5 EEDATH4 EEDATH3 EEDATH2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as `0'
bit 5-0 EEDATH<5:0>: 6 Most Significant Data bits from program memory
REGISTER 9-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
-- EEADRH1 EEADRH0
bit 7 -- -- -- EEADRH3 EEADRH2
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as `0'
bit 3-0 EEADRH<3:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads
DS41203D-page 78 2007 Microchip Technology Inc.
PIC16F688
REGISTER 9-5: EECON1: EEPROM CONTROL REGISTER
R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
WREN WR RD
EEPGD -- -- -- WRERR bit 0
bit 7
Legend: W = Writable bit U = Unimplemented bit, read as `0'
S = Bit can only be set `1' = Bit is set
R = Readable bit `0' = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7 EEPGD: Program/Data EEPROM Select bit
bit 6-4 1 = Accesses program memory
bit 3 0 = Accesses data memory
bit 2
bit 1 Unimplemented: Read as `0'
bit 0 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
EEPGD = 1:
This bit is ignored
EEPGD = 0:
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in
software.)
0 = Does not initiate a memory read
2007 Microchip Technology Inc. DS41203D-page 79
PIC16F688
9.1.2 READING THE DATA EEPROM 9.1.3 WRITING TO THE DATA EEPROM
MEMORY MEMORY
To read a data memory location, the user must write the To write an EEPROM data location, the user must first
address to the EEADR register, clear the EEPGD write the address to the EEADR register and the data
control bit of the EECON1 register, and then set control to the EEDAT register. Then the user must follow a
bit RD of the EECON1 register. The data is available in specific sequence to initiate the write for each byte.
the very next cycle, in the EEDAT register; therefore, it
can be read in the next instruction. EEDAT will hold this The write will not initiate if the above sequence is not
value until another read or until it is written to by the followed exactly (write 55h to EECON2, write AAh to
user (during a write operation). EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
EXAMPLE 9-1: DATA EEPROM READ Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
BANKSEL EEADR ; writes to data EEPROM due to errant (unexpected)
MOVLW DATA_EE_ADDR ; code execution (i.e., lost programs). The user should
MOVWF EEADR ;Data Memory keep the WREN bit clear at all times, except when
;Address to read updating EEPROM. The WREN bit is not cleared
BCF EECON1, EEPGD ;Point to DATA by hardware.
;memory
BSF EECON1, RD ;EE Read After a write sequence has been initiated, clearing the
MOVF EEDAT, W ;W = EEDAT WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 9-2: DATA EEPROM WRITE
BANKSEL EEADR ;
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ;Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDAT ;Data Memory Value to write
BANKSEL EECON1 ;
BCF EECON1, EEPGD ;Point to DATA memory
BSF EECON1, WREN ;Enable writes
Required BCF INTCON, GIE ;Disable INTs.
Sequence BTFSC INTCON, GIE ;SEE AN576
GOTO $-2
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable INTs.
SLEEP EECON1, WREN ;Wait for interrupt to signal write complete
BCF ;Disable writes
DS41203D-page 80 2007 Microchip Technology Inc.
PIC16F688
9.1.4 READING THE FLASH PROGRAM EEDAT and EEDATH registers will hold this value until
MEMORY another read or until it is written to by the user (during
a write operation).
To read a program memory location, the user must
write two bytes of the address to the EEADR and Note 1: The two instructions following a program
EEADRH registers, set the EEPGD control bit of the memory read are required to be NOP's.
EECON1 register, and then set control bit RD of the This prevents the user from executing a
EECON1 register. Once the read control bit is set, the two-cycle instruction on the next
program memory Flash controller will use the second instruction after the RD bit is set.
instruction cycle to read the data. This causes the sec-
ond instruction immediately following the "BSF 2: If the WR bit is set when EEPGD = 1, it
EECON1,RD" instruction to be ignored. The data is will be immediately reset to `0' and no
available in the very next cycle, in the EEDAT and operation will take place.
EEDATH registers; therefore, it can be read as two
bytes in the following instructions.
EXAMPLE 9-3: FLASH PROGRAM READ
Required BANKSEL EEADR ;
Sequence MOVLW MS_PROG_EE_ADDR ;
MOVWF EEADRH ;MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR ;
MOVWF EEADR ;LS Byte of Program Address to read
BANKSEL EECON1 ;
BSF EECON1, EEPGD ;Point to PROGRAM memory
BSF EECON1, RD ;EE Read
;
EEDAT ;First instruction after BSF EECON1,RD executes normally
NOP EEDAT, W
NOP LOWPMBYTE ;Any instructions here are ignored as program
EEDATH, W ;memory is read in second cycle after BSF EECON1,RD
; HIGHPMBYTE
BANKSEL STATUS, RP1 ;
MOVF ;W = LS Byte of Program Memory
MOVWF ;
MOVF ;W = MS Byte of Program EEDAT
MOVWF ;
BCF ;Bank 0
2007 Microchip Technology Inc. DS41203D-page 81
PIC16F688
FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 EEADRH,EEADR PPCC++33 PC + 4 PC + 5
Flash Data
INSTR (PC) INSTR (PC + 1) EEDATH,EEDAT INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4)
executed here executed here executed here executed here executed here executed here
RD bit
EEDATH
EEDAT
Register
EERHLT
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
EECON1 Resets
EECON2 EEPGD -- -- -- WRERR WREN WR RD x--- x000
EEADR 0--- q000
EEADRH EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
EEDAT 0000 0000
EEDATH EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 ---- 0000
INTCON 0000 0000
PIE1 -- -- -- -- EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 --00 0000
PIR1 0000 000x
Legend: EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
-- -- EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 0000 0000
GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000
x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
DS41203D-page 82 2007 Microchip Technology Inc.
PIC16F688
10.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS
ASYNCHRONOUS RECEIVER Full-duplex asynchronous transmit and receive
TRANSMITTER (EUSART) Two-character input buffer
One-character output buffer
The Enhanced Universal Synchronous Asynchronous Programmable 8-bit or 9-bit character length
Receiver Transmitter (EUSART) module is a serial I/O Address detection in 9-bit mode
communications peripheral. It contains all the clock Input buffer overrun error detection
generators, shift registers and data buffers necessary Received character framing error detection
to perform an input or output serial data transfer Half-duplex synchronous master
independent of device program execution. The Half-duplex synchronous slave
EUSART, also known as a Serial Communications Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous modes
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers. Automatic detection and calibration of the baud rate
These devices typically do not have internal clocks for Wake-up on Break reception
baud rate generation and require the external clock 13-bit Break character transmit
signal provided by a master synchronous device.
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 10-1 and Figure 10-2.
FIGURE 10-1: EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE
TXIF
TXREG Register Interrupt
Pin Buffer TX/CK pin
MSb 8 and Control
LSb
(8) 0
Transmit Shift Register (TSR)
TXEN
Baud Rate Generator TRMT SPEN
BRG16 FOSC TX9
+1 n TX9D
SPBRGH SPBRG n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
2007 Microchip Technology Inc. DS41203D-page 83
PIC16F688
FIGURE 10-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin MSb RSR Register LSb
Stop (8) 0 START
Pin Buffer Data 7 1
and Control Recovery
Baud Rate Generator FOSC RX9
n
BRG16 FERR RX9D RCREG Register FIFO
+1 Multiplier x4 x16 x64 n
SYNC 1 X 0 0 0
SPBRGH SPBRG BRGH X 1 1 0 0
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
The operation of the EUSART module is controlled
through three registers:
Transmit Status and Control (TXSTA)
Receive Status and Control (RCSTA)
Baud Rate Control (BAUDCTL)
These registers are detailed in Register 10-1,
Register 10-2 and Register 10-3, respectively.
DS41203D-page 84 2007 Microchip Technology Inc.
10.1 EUSART Asynchronous Mode PIC16F688
The EUSART transmits and receives data using the Note 1: When the SPEN bit is set, the RX/DT I/O
standard non-return-to-zero (NRZ) format. NRZ is pin is automatically configured as an input,
implemented with two levels: a VOH mark state which regardless of the state of the corresponding
represents a `1' data bit, and a VOL space state which TRIS bit and whether or not the EUSART
represents a `0' data bit. NRZ refers to the fact that receiver is enabled. The RX/DT pin data
consecutively transmitted data bits of the same value can be read via a normal PORT read but
stay at the output level of that bit without returning to a PORT latch data output is precluded.
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character 2: The TXIF transmitter interrupt flag is set
transmission consists of one Start bit followed by eight when the TXEN enable bit is set.
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the 10.1.1.2 Transmitting Data
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period A transmission is initiated by writing a character to the
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud TXREG register. If this is the first character, or the
Rate Generator is used to derive standard baud rate previous character has been completely flushed from
frequencies from the system oscillator. See Table 10-5 the TSR, the data in the TXREG is immediately
for examples of baud rate configurations. transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
The EUSART transmits and receives the LSb first. The data is held in the TXREG until the Stop bit of the
EUSART's transmitter and receiver are functionally previous character has been transmitted. The pending
independent, but share the same data format and baud character in the TXREG is then transferred to the TSR
rate. Parity is not supported by the hardware, but can in one TCY immediately following the Stop bit
be implemented in software and stored as the ninth transmission. The transmission of the Start bit, data bits
data bit. and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
10.1.1 EUSART ASYNCHRONOUS TXREG.
TRANSMITTER
10.1.1.3 Transmit Interrupt Flag
The EUSART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the serial The TXIF interrupt flag bit of the PIR1 register is set
Transmit Shift Register (TSR), which is not directly whenever the EUSART transmitter is enabled and no
accessible by software. The TSR obtains its data from character is being held for transmission in the TXREG.
the transmit buffer, which is the TXREG register. In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
10.1.1.1 Enabling the Transmitter queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
The EUSART transmitter is enabled for asynchronous becomes valid in the second instruction cycle following
operations by configuring the following three control the write execution. Polling TXIF immediately following
bits: the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
TXEN = 1
SYNC = 0 The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in
their default state. To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
Setting the TXEN bit of the TXSTA register enables the TXIE interrupt enable bit upon writing the last character
transmitter circuitry of the EUSART. Clearing the SYNC of the transmission to the TXREG.
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
2007 Microchip Technology Inc. DS41203D-page 85
PIC16F688
10.1.1.4 TSR Status 10.1.1.6 Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRG register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 10.3 "EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)").
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register. 2. Enable the asynchronous serial port by clearing
No interrupt logic is tied to this bit, so the user has to the SYNC bit and setting the SPEN bit.
poll this bit to determine the TSR status.
3. If 9-bit transmission is desired, set the TX9 con-
Note: The TSR register is not mapped in data trol bit. A set ninth data bit will indicate that the 8
memory, so it is not available to the user. Least Significant data bits are an address when
the receiver is set for address detection.
10.1.1.5 Transmitting 9-Bit Characters
4. Enable the transmission by setting the TXEN
The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit
When the TX9 bit of the TXSTA register is set the to be set.
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth, 5. If interrupts are desired, set the TXIE interrupt
and Most Significant, data bit. When transmitting 9-bit enable bit. An interrupt will occur immediately
data, the TX9D data bit must be written before writing provided that the GIE and PEIE bits of the
the 8 Least Significant bits into the TXREG. All nine bits INTCON register are also set.
of data will be transferred to the TSR shift register
immediately after the TXREG is written. 6. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 10.1.2.7 "Address 7. Load 8-bit data into the TXREG register. This
Detection" for more information on the Address mode. will start the transmission.
FIGURE 10-3: ASYNCHRONOUS TRANSMISSION
Write to TXREG Word 1
BRG Output Start bit bit 0 bit 1 bit 7/8 Stop bit
(Shift Clock) Word 1
RC4/C2OUT/TX/CK 1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit Word 1
(Transmit Shift Transmit Shift Reg
Reg. Empty Flag)
FIGURE 10-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG Word 1 Word 2
BRG Output Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
(Shift Clock) 1 TCY Word 1
RC4/C2OUT/TX/CK 1 TCY Word 2
pin Word 1 Word 2
TXIF bit Transmit Shift Reg. Transmit Shift Reg.
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
DS41203D-page 86 2007 Microchip Technology Inc.
PIC16F688
TABLE 10-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Asynchronous Transmission.
2007 Microchip Technology Inc. DS41203D-page 87
PIC16F688
10.1.2 EUSART ASYNCHRONOUS 10.1.2.2 Receiving Data
RECEIVER
The receiver data recovery circuit initiates character
The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit,
RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data
in Figure 10-2. The data is received on the RX/DT pin recovery circuit counts one-half bit time to the center of
and drives the data recovery block. The data recovery the Start bit and verifies that the bit is still a zero. If it is
block is actually a high-speed shifter operating at 16 not a zero then the data recovery circuit aborts
times the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all 8 or 9 resumes looking for the falling edge of the Start bit. If
bits of the character have been shifted in, they are the Start bit zero verification succeeds then the data
immediately transferred to a two character First-In- recovery circuit counts a full bit time to the center of the
First-Out (FIFO) memory. The FIFO buffering allows next bit. The bit is then sampled by a majority detect
reception of two complete characters and the start of a circuit and the resulting `0' or `1' is shifted into the RSR.
third character before software must start servicing the This repeats until all data bits have been sampled and
EUSART receiver. The FIFO and RSR registers are not shifted into the RSR. One final bit time is measured and
directly accessible by software. Access to the received the level sampled. This is the Stop bit, which is always
data is via the RCREG register. a `1'. If the data recovery circuit samples a `0' in the
Stop bit position then a framing error is set for this
10.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
character. See Section 10.1.2.4 "Receive Framing
The EUSART receiver is enabled for asynchronous Error" for more information on framing errors.
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
CREN = 1 been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
SYNC = 0 flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
SPEN = 1 RCREG register.
All other EUSART control bits are assumed to be in Note: If the receive FIFO is overrun, no additional
their default state. characters will be received until the overrun
condition is cleared. See Section 10.1.2.5
Setting the CREN bit of the RCSTA register enables the "Receive Overrun Error" for more
receiver circuitry of the EUSART. Clearing the SYNC bit information on overrun errors.
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the 10.1.2.3 Receive Interrupts
RCSTA register enables the EUSART and automatically
configures the RX/DT I/O pin as an input. If the RX/DT The RCIF interrupt flag bit of the PIR1 register is set
pin is shared with an analog peripheral the analog I/O whenever the EUSART receiver is enabled and there is
function must be disabled by clearing the corresponding an unread character in the receive FIFO. The RCIF
ANSEL bit. interrupt flag bit is read-only, it cannot be set or cleared
by software.
Note: When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an RCIF interrupts are enabled by setting the following
output, regardless of the state of the bits:
corresponding TRIS bit and whether or not
the EUSART transmitter is enabled. The RCIE interrupt enable bit of the PIE1 register
PORT latch is disconnected from the PEIE peripheral interrupt enable bit of the
output driver so it is not possible to use the
TX/CK pin as a general purpose output. INTCON register
GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
DS41203D-page 88 2007 Microchip Technology Inc.
10.1.2.4 Receive Framing Error PIC16F688
Each character in the receive FIFO buffer has a 10.1.2.7 Address Detection
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected A special Address Detection mode is available for use
time. The framing error status is accessed via the when multiple receivers share the same transmission
FERR bit of the RCSTA register. The FERR bit line, such as in RS-485 systems. Address detection is
represents the status of the top unread character in the enabled by setting the ADDEN bit of the RCSTA
receive FIFO. Therefore, the FERR bit must be read register.
before reading the RCREG.
Address detection requires 9-bit character reception.
The FERR bit is read-only and only applies to the top When address detection is enabled, only characters
unread character in the receive FIFO. A framing error with the ninth data bit set will be transferred to the
(FERR = 1) does not preclude reception of additional receive FIFO buffer, thereby setting the RCIF interrupt
characters. It is not necessary to clear the FERR bit. bit. All other characters will be ignored.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next Upon receiving an address character, user software
corresponding framing error. determines if the address matches its own. Upon
address match, user software must disable address
The FERR bit can be forced clear by clearing the SPEN detection by clearing the ADDEN bit before the next
bit of the RCSTA register which resets the EUSART. Stop bit occurs. When user software detects the end of
Clearing the CREN bit of the RCSTA register does not the message, determined by the message protocol
affect the FERR bit. A framing error by itself does not used, software places the receiver back into the
generate an interrupt. Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
10.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated If a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
10.1.2.6 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
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10.1.2.8 Asynchronous Reception Set-up: 10.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRG register pair and This mode would typically be used in RS-485 systems.
the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 10.3 "EUSART Detect Enable:
Baud Rate Generator (BRG)").
1. Initialize the SPBRGH, SPBRG register pair and
2. Enable the serial port by setting the SPEN bit. the BRGH and BRG16 bits to achieve the
The SYNC bit must be clear for asynchronous desired baud rate (see Section 10.3 "EUSART
operation. Baud Rate Generator (BRG)").
3. If interrupts are desired, set the RCIE interrupt 2. Enable the serial port by setting the SPEN bit.
enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
4. If 9-bit reception is desired, set the RX9 bit. 3. If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
5. Enable reception by setting the CREN bit. INTCON register.
6. The RCIF interrupt flag bit will be set when a 4. Enable 9-bit reception by setting the RX9 bit.
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if 5. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
7. Read the RCSTA register to get the error flags 6. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth
data bit. 7. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
8. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
9. If an overrun occurred, clear the OERR flag by 8. Read the RCSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device's address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 10-5: ASYNCHRONOUS RECEPTION
RX/DT pin Start Start Start bit 7/8 Stop
bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit
Rcv Shift
Reg bit bit
Rcv Buffer Reg
Word 1 Word 2
RCIDL RCREG RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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TABLE 10-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
0000 000x
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 0000
0000 0000
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
0000 000x
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
0000 0000
RCREG EUSART Receive Data Register 0000 0000 --11 1111
0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 0010
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111
TXREG EUSART Transmit Data Register 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Asynchronous Reception.
2007 Microchip Technology Inc. DS41203D-page 91
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10.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE
Asynchronous Operation register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
The factory calibrates the internal oscillator block out- changes to the system clock source. See Section 3.5
put (INTOSC). However, the INTOSC frequency may "Internal Clock Modes" for more information.
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may The other method adjusts the value in the Baud Rate
be used to adjust the baud rate clock, but both require Generator. This can be done automatically with the
a reference clock source of some kind. Auto-Baud Detect feature (see Section 10.3.1 "Auto-
Baud Detect"). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don't care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don't care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
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REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7
bit 0
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don't care
Synchronous mode Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode Slave
Don't care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don't care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2007 Microchip Technology Inc. DS41203D-page 93
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REGISTER 10-3: BAUDCTL: BAUD RATE CONTROL REGISTER
R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
WUE ABDEN
ABDOVF RCIDL -- SCKP BRG16 --
bit 0
bit 7
Legend: W = Writable bit U = Unimplemented bit, read as `0'
R = Readable bit `1' = Bit is set
-n = Value at POR `0' = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don't care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don't care
bit 5 Unimplemented: Read as `0'
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the RB7/TX/CK pin
0 = Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as `0'
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don't care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don't care
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10.3 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 10-1: CALCULATING BAUD
BRG16 bit of the BAUDCTL register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPBRGH, SPBRG register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = ----------------------------F----O----S---C-----------------------------
period is determined by both the BRGH bit of the TXSTA 64([SPBRGH:SPBRG] + 1)
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored. Solving for SPBRGH:SPBRG:
Table 10-3 contains the formulas for determining the ----------------F----O----S---C------------------
baud rate. Example 10-1 provides a sample calculation X = -D----e---s--i--r--e---d----B----a---u---d----R----a---t--e- 1
for determining the baud rate and baud rate error.
64
Typical baud rates and error values for various
asynchronous modes have been computed for your 1---6---0----0--0---0---0---0--
convenience and are shown in Table 10-3. It may be ------9----6---0--0--------
advantageous to use the high baud rate (BRGH = 1), = 64 1
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow = [25.042] = 25
baud rates for fast oscillator frequencies.
Calculated Baud Rate = --1---6---0---0---0---0---0---0---
Writing a new value to the SPBRGH, SPBRG register 64(25 + 1)
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow = 9615
before outputting the new baud rate.
Error = C-----a--l--c---.---B---a---u----d----R----a---t-e---------D----e---s--i--r--e---d-----B---a---u---d-----R---a---t--e---
Desired Baud Rate
= (---9---6---1---5---------9---6---0---0---)- = 0.16%
9600
TABLE 10-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
FOSC/[64 (n+1)]
SYNC BRG16 BRGH FOSC/[16 (n+1)]
0 0 0 8-bit/Asynchronous FOSC/[4 (n+1)]
0
0 0 1 8-bit/Asynchronous
0
1 1 0 16-bit/Asynchronous
1
Legend: 1 1 16-bit/Asynchronous
0 x 8-bit/Synchronous
1 x 16-bit/Synchronous
x = Don't care, n = value of SPBRGH, SPBRG register pair
TABLE 10-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
0000 000x
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 0000
0000 0000
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0010
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator.
2007 Microchip Technology Inc. DS41203D-page 95
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
Rate Error value Rate Error value Rate Error value Rate Error value
(decimal)
(decimal) (decimal) (decimal)
300 -- -- -- -- -- -- -- -- -- -- -- --
1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103
2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51
9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12
10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 -- -- --
57.6k -- -- -- 57.60k 0.00 7 57.60k 0.00 2 -- -- --
115.2k -- -- -- -- -- -- -- -- -- -- -- --
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51
19.2k
57.6k 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12
115.2k
2404 0.16 25 2400 0.00 23 2404 0.16 12 -- -- --
-- -- -- 9600 0.00 5 -- -- -- -- -- --
10417 0.00 5 -- -- -- 10417 0.00 2 -- -- --
-- -- -- 19.20k 0.00 2 -- -- -- -- -- --
-- -- -- 57.60k 0.00 0 -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 -- -- -- -- -- -- -- -- -- -- -- --
19.2k
57.6k -- -- -- -- -- -- -- -- -- -- -- --
115.2k
-- -- -- -- -- -- -- -- -- 2404 0.16 207
9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25
56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 -- -- --
DS41203D-page 96 2007 Microchip Technology Inc.
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 -- -- -- -- -- -- -- -- -- 300 0.16 207
19.2k
57.6k 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
115.2k
2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9615 0.16 25 9600 0.00 23 9615 0.16 12 -- -- --
10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.23k 0.16 12 19.2k 0.00 11 -- -- -- -- -- --
-- -- -- 57.60k 0.00 3 -- -- -- -- -- --
-- -- -- 115.2k 0.00 1 -- -- -- -- -- --
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666
19.2k 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416
57.6k
115.2k 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207
9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25
56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 -- -- --
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207
19.2k
57.6k 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
115.2k
2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9615 0.16 25 9600 0.00 23 9615 0.16 12 -- -- --
10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.23k 0.16 12 19.20k 0.00 11 -- -- -- -- -- --
-- -- -- 57.60k 0.00 3 -- -- -- -- -- --
-- -- -- 115.2k 0.00 1 -- -- -- -- -- --
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TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666
19.2k 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666
57.6k
115.2k 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832
9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207
10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191
19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103
57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34
116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG
300 Rate Error value Rate Error value Rate Error value Rate Error value
1200 (decimal)
2400 (decimal) (decimal) (decimal)
9600
10417 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832
19.2k
57.6k 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207
115.2k
2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103
9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25
10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23
19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12
58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 -- -- --
111.1k -3.55 8 115.2k 0.00 7 -- -- -- -- -- --
DS41203D-page 98 2007 Microchip Technology Inc.
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10.3.1 AUTO-BAUD DETECT and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection average bit time when clocked at full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the following the Break character (see
incoming RX signal, the RX signal is timing the BRG. Section 10.3.2 "Auto-Wake-up on
The Baud Rate Generator is used to time the period of Break").
a received 55h (ASCII "U") which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUDCTL register starts Some combinations of oscillator frequency
the auto-boot sequence (Figure 10-6). While the ABD and EUSART baud rates are not possible
sequence takes place, the EUSART state machine is due to bit error rates. Overall system timing
held in Idle. On the first rising edge of the receive line, and communication baud rates must be
after the Start bit, the SPBRG begins counting up using taken into consideration when using the
the BRG counter clock as shown in Table 10-6. The Auto-Baud Detect feature.
fifth rising edge will occur on the RX pin at the end of
the eighth bit period. At that time, an accumulated 3: During the auto-baud process, the auto-
value totaling the proper BRG period is left in baud counter starts counting at 1. Upon
SPBRGH, SPBRG register pair, the ABDEN bit is completion of the auto-baud sequence, to
automatically cleared and the RCIF interrupt flag is set. achieve maximum accuracy, subtract 1
The value in the RCREG needs to be read to clear the from the SPBRGH:SPBRG register pair.
RCIF interrupt. RCREG content should be discarded.
When calibrating for modes that do not use the TABLE 10-6: BRG COUNTER CLOCK RATES
SPBRGH register the user can verify that the SPBRG
register did not overflow by checking for 00h in the BRG16 BRGH BRG Base BRG ABD
SPBRGH register. Clock Clock
The BRG auto-baud clock is determined by the BRG16 0 0 FOSC/64 FOSC/512
and BRGH bits as shown in Table 10-6. During ABD, 0
both the SPBRGH and SPBRG registers are used as a 1 1 FOSC/16 FOSC/128
16-bit counter, independent of the BRG16 bit setting. 1
While calibrating the baud rate period, the SPBRGH Note: 0 FOSC/16 FOSC/128
1 FOSC/4 FOSC/32
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 10-6: AUTOMATIC BAUD RATE CALCULATION
BRG Value XXXXh 0000h 001Ch
RX pin
Start Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared
ABDEN bit
1Ch
RCIDL 00h
RCIF bit
(Interrupt)
Read
RCREG
SPBRG XXh
SPBRGH XXh
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
2007 Microchip Technology Inc. DS41203D-page 99
PIC16F688
10.3.2 AUTO-WAKE-UP ON BREAK 10.3.2.1 Special Considerations
During Sleep mode, all clocks to the EUSART are Break Character
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be To avoid character errors or character fragments during
performed. The Auto-Wake-up feature allows the a wake-up event, the wake-up character must be all
controller to wake-up due to activity on the RX/DT line. zeros.
This feature is available only in Asynchronous mode.
When the wake-up is enabled the function works
The Auto-Wake-up feature is enabled by setting the independent of the low time on the data stream. If the
WUE bit of the BAUDCTL register. Once set, the normal WUE bit is set and a valid non-zero character is
receive sequence on RX/DT is disabled, and the received, the low time from the Start bit to the first rising
EUSART remains in an Idle state, monitoring for a wake- edge will be interpreted as the wake-up event. The
up event independent of the CPU mode. A wake-up remaining bits in the character will be received as a
event consists of a high-to-low transition on the RX/DT fragmented character and subsequent characters can
line. (This coincides with the start of a Sync Break or a result in framing or overrun errors.
wake-up signal character for the LIN protocol.)
Therefore, the initial character in the transmission must
The EUSART module generates an RCIF interrupt be all `0's. This must be 10 or more bit times, 13-bit
coincident with the wake-up event. The interrupt is times recommended for LIN bus, or any number of bit
generated synchronously to the Q clocks in normal CPU times for standard RS-232 devices.
operating modes (Figure 10-7), and asynchronously if
the device is in Sleep mode (Figure 10-8). The interrupt Oscillator Start-up Time
condition is cleared by reading the RCREG register.
Oscillator start-up time must be considered, especially
The WUE bit is automatically cleared by the low-to-high in applications using oscillators with longer start-up
transition on the RX line at the end of the Break. This intervals (i.e., LP, XT or HS mode). The Sync Break (or
signals to the user that the Break event is over. At this wake-up signal) character must be of sufficient length,
point, the EUSART module is in Idle mode waiting to and be followed by a sufficient interval, to allow enough
receive the next character. time for the selected oscillator to start and provide
proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
FIGURE 10-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1 Bit set by user Auto Cleared
WUE bit
RX/DT Line
RCIF Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
DS41203D-page 100 2007 Microchip Technology Inc.
PIC16F688
FIGURE 10-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Bit Set by User
WUE bit Note 1
Cleared due to User Read of RCREG
RX/DT Line
RCIF
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
10.3.3 BREAK CHARACTER SEQUENCE 10.3.4 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break
special Break character sequences that are required by character in two ways.
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 `0' bits and a Stop bit. The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is
bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud
mission is then initiated by a write to the TXREG. The rate.
value of data written to TXREG will be ignored and all
`0's will be transmitted. A Break character has been received when;
The SENDB bit is automatically reset by hardware after RCIF bit is set
the corresponding Stop bit is sent. This allows the user FERR bit is set
to preload the transmit FIFO with the next transmit byte RCREG = 00h
following the Break character (typically, the Sync
character in the LIN specification). The second method uses the Auto-Wake-up feature
described in Section 10.3.2 "Auto-Wake-up on
The TRMT bit of the TXSTA register indicates when the Break". By enabling this feature, the EUSART will
transmit operation is active or Idle, just as it does during sample the next two transitions on RX/DT, cause an
normal transmission. See Figure 10-9 for the timing of RCIF interrupt, and receive the next data byte followed
the Break character sequence. by another interrupt.
10.3.3.1 Break and Sync Transmit Sequence Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
The following sequence will start a message frame For both methods, the user can set the ABDEN bit of
header made up of a Break, followed by an auto-baud the BAUDCTL register before placing the EUSART in
Sync byte. This sequence is typical of a LIN bus Sleep mode.
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write `55h' to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
2007 Microchip Technology Inc. DS41203D-page 101
PIC16F688
FIGURE 10-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG Dummy Write
BRG Output Start bit bit 0 bit 1 bit 11 Stop bit
(Shift Clock) Break Auto Cleared
TX (pin) SENDB Sampled Here
TXIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(send Break
control bit)
DS41203D-page 102 2007 Microchip Technology Inc.
10.4 EUSART Synchronous Mode PIC16F688
Synchronous serial communications are typically used the clock Idle state as high. When the SCKP bit is set,
in systems with a single master and one or more the data changes on the falling edge of each clock.
slaves. The master device contains the necessary Clearing the SCKP bit sets the Idle state as low. When
circuitry for baud rate generation and supplies the clock the SCKP bit is cleared, the data changes on the rising
for all devices in the system. Slave devices can take edge of each clock.
advantage of the master clock by eliminating the
internal clock generation circuitry. 10.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
There are two signal lines in Synchronous mode: a The RX/DT and TX/CK pin output drivers are automat-
bidirectional data line and a clock line. Slaves use the ically enabled when the EUSART is configured for
external clock supplied by the master to shift the serial synchronous master transmit operation.
data into and out of their respective receive and trans- A transmission is initiated by writing a character to the
mit shift registers. Since the data line is bidirectional, TXREG register. If the TSR still contains all or part of a
synchronous operation is half-duplex only. Half-duplex previous character, the new character data is held in
refers to the fact that master and slave devices can the TXREG until the last bit of the previous character
receive and transmit data but not both simultaneously. has been transmitted. If this is the first character, or the
The EUSART can operate as either a master or slave previous character has been completely flushed from
device. the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
Start and Stop bits are not used in synchronous commences immediately following the transfer of the
transmissions. data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
10.4.1 SYNCHRONOUS MASTER MODE master clock and remains valid until the subsequent
leading clock edge.
The following bits are used to configure the EUSART
for Synchronous Master operation: Note: The TSR register is not mapped in data
memory, so it is not available to the user.
SYNC = 1
CSRC = 1 10.4.1.4 Synchronous Master Transmission
SREN = 0 (for transmit); SREN = 1 (for receive) Set-up:
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1 1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
Setting the SYNC bit of the TXSTA register configures desired baud rate (see Section 10.3 "EUSART
the device for synchronous operation. Setting the CSRC Baud Rate Generator (BRG)").
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA 2. Enable the synchronous master serial port by
register ensures that the device is in the Transmit mode, setting bits SYNC, SPEN and CSRC.
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the 3. Disable Receive mode by clearing bits SREN
EUSART. If the RX/DT or TX/CK pins are shared with an and CREN.
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits. 4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
10.4.1.1 Master Clock 6. If interrupts are desired, set the TXIE, GIE and
Synchronous data transfers use a separate clock line, PEIE interrupt enable bits.
which is synchronous with the data. A device config- 7. If 9-bit transmission is selected, the ninth bit
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin is automatically configured as an output should be loaded in the TX9D bit.
when the EUSART is configured for synchronous 8. Start transmission by loading data to the TXREG
transmit operation. Serial data bits change on the lead-
ing edge to ensure they are valid at the trailing edge of register.
each clock. One clock cycle is generated for each data
bit. Only as many clock cycles are generated as there DS41203D-page 103
are data bits.
10.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCTL register. Setting the SCKP bit sets
2007 Microchip Technology Inc.
PIC16F688
FIGURE 10-10: SYNCHRONOUS TRANSMISSION
RX/DT bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
pin
Word 1 Word 2 `1'
TX/CK pin bit 7
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to Write Word 1 Write Word 2
TXREG Reg
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit `1'
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 10-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Transmission.
DS41203D-page 104 2007 Microchip Technology Inc.
10.4.1.5 Synchronous Master Reception PIC16F688
Data is received at the RX/DT pin. The RX/DT and TX/ 10.4.1.8 Synchronous Master Reception Set-
CK pin output drivers are automatically disabled when up:
the EUSART is configured for synchronous master
receive operation. 1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
In Synchronous mode, reception is enabled by setting BRGH and BRG16 bits, as required, to achieve
either the Single Receive Enable bit (SREN of the the desired baud rate.
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register). 2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a 3. Ensure bits CREN and SREN are clear.
single character. The SREN bit is automatically cleared 4. If using interrupts, set the GIE and PEIE bits of
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is the INTCON register and set RCIE.
cleared. If CREN is cleared in the middle of a character 5. If 9-bit reception is desired, set bit RX9.
the CK clock stops immediately and the partial charac- 6. Start reception by setting the SREN bit or for
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character continuous reception, set the CREN bit.
and CREN takes precedence. 7. Interrupt flag bit RCIF will be set when reception
To initiate reception, set either SREN or CREN. Data is of a character is complete. An interrupt will be
sampled at the RX/DT pin on the trailing edge of the generated if the enable bit RCIE was set.
TX/CK clock pin and is shifted into the Receive Shift 8. Read the RCSTA register to get the ninth bit (if
Register (RSR). When a complete character is enabled) and determine if any error occurred
received into the RSR, the RCIF bit is set and the char- during reception.
acter is automatically transferred to the two character 9. Read the 8-bit received data by reading the
receive FIFO. The Least Significant eight bits of the top RCREG register.
character in the receive FIFO are available in RCREG. 10. If an overrun error occurs, clear the error by
The RCIF bit remains set as long as there are un-read either clearing the CREN bit of the RCSTA
characters in the receive FIFO. register or by clearing the SPEN bit which resets
the EUSART.
10.4.1.6 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
10.4.1.7 Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
2007 Microchip Technology Inc. DS41203D-page 105
PIC16F688
FIGURE 10-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
pin
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit `0' `0'
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Reception.
DS41203D-page 106 2007 Microchip Technology Inc.
PIC16F688
10.4.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for Synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
SYNC = 1
CSRC = 0 2. The second word will remain in TXREG register.
SREN = 0 (for transmit); SREN = 1 (for receive) 3. The TXIF bit will not be set.
CREN = 0 (for transmit); CREN = 1 (for receive) 4. After the first character has been shifted out of
SPEN = 1
TSR, the TXREG register will transfer the second
Setting the SYNC bit of the TXSTA register configures the character to the TSR and the TXIF bit will now be
device for synchronous operation. Clearing the CSRC bit set.
of the TXSTA register configures the device as a slave. 5. If the PEIE and TXIE bits are set, the interrupt
Clearing the SREN and CREN bits of the RCSTA register will wake the device from Sleep and execute the
ensures that the device is in the Transmit mode, next instruction. If the GIE bit is also set, the
otherwise the device will be configured to receive. Setting program will call the Interrupt Service Routine.
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an 10.4.2.2 Synchronous Slave Transmission
analog peripheral the analog I/O functions must be Set-up:
disabled by clearing the corresponding ANSEL bits.
1. Set the SYNC and SPEN bits and clear the
10.4.2.1 EUSART Synchronous Slave CSRC bit.
Transmit
2. Clear the CREN and SREN bits.
The operation of the Synchronous Master and Slave 3. If using interrupts, ensure that the GIE and PEIE
modes are identical (see Section 10.4.1.3
"Synchronous Master Transmission"), except in the bits of the INTCON register are set and set the
case of the Sleep mode. TXIE bit.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Transmission.
2007 Microchip Technology Inc. DS41203D-page 107
PIC16F688
10.4.2.3 EUSART Synchronous Slave 10.4.2.4 Synchronous Slave Reception Set-
Reception up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 10.4.1.5 "Synchronous CSRC bit.
Master Reception"), with the following exceptions:
2. If using interrupts, ensure that the GIE and PEIE
Sleep bits of the INTCON register are set and set the
CREN bit is always set, therefore the receiver is RCIE bit.
never Idle 3. If 9-bit reception is desired, set the RX9 bit.
SREN bit, which is a "don't care" in Slave mode
4. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. The RCIF bit will be set when reception is
word is received, the RSR register will transfer the data complete. An interrupt will be generated if the
to the RCREG register. If the RCIE enable bit is set, the RCIE bit was set.
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also 6. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets
BAUDCTL ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Reception.
DS41203D-page 108 2007 Microchip Technology Inc.
11.0 SPECIAL FEATURES OF THE PIC16F688
CPU
The PIC16F688 has two timers that offer necessary
The PIC16F688 has a host of features intended to delays on power-up. One is the Oscillator Start-up
maximize system reliability, minimize cost through Timer (OST), intended to keep the chip in Reset until
elimination of external components, provide the crystal oscillator is stable. The other is the
power-saving features and offer code protection. Power-up Timer (PWRT), which provides a fixed delay
of 64 ms (nominal) on power-up only, designed to
These features are: keep the part in Reset while the power supply
stabilizes. There is also circuitry to reset the device if
Reset a brown-out occurs, which can use the Power-up
- Power-on Reset (POR) Timer to provide at least a 64 ms Reset. With these
- Power-up Timer (PWRT) three functions-on-chip, most applications need no
- Oscillator Start-up Timer (OST) external Reset circuitry.
- Brown-out Reset (BOR)
The Sleep mode is designed to offer a very low-current
Interrupts Power-Down mode. The user can wake-up from Sleep
Watchdog Timer (WDT) through:
Oscillator Selection
Sleep External Reset
Code Protection Watchdog Timer Wake-up
ID Locations An interrupt
In-Circuit Serial ProgrammingTM
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 11-1).
2007 Microchip Technology Inc. DS41203D-page 109
PIC16F688
11.1 Configuration Bits
The Configuration bits can be programmed (read as
`0'), or left unprogrammed (read as `1') to select various
device configurations as shown in Register 11-1.
These bits are mapped in program memory location
2007h.
Note: Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
"PIC12F6XX/16F6XX Memory Program-
ming Specification" (DS41204) for more
information.
DS41203D-page 110 2007 Microchip Technology Inc.
PIC16F688
REGISTER 11-1: CONFIG: CONFIGURATION WORD REGISTER
Reserved Reserved Reserved Reserved FCMEN IESO BOREN1(1) BOREN0(1)
bit 15 bit 8
CPD(2) CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend: W = Writable bit P = Programmable' U = Unimplemented bit, read
R = Readable bit `1' = Bit is set `0' = Bit is cleared as `0'
-n = Value at POR x = Bit is unknown
bit 15-12 Reserved: Reserved bits. Do Not Use.
bit 11
bit 10 FCMEN: Fail-Safe Clock Monitor Enabled bit
bit 9-8 1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 7
bit 6 IESO: Internal External Switchover bit
bit 5 1 = Internal External Switchover mode is enabled
bit 4 0 = Internal External Switchover mode is disabled
bit 3 BOREN<1:0>: Brown-out Reset Selection bits(1)
bit 2-0 11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: MCLR Pin Function Select bit(3)
1 = MCLR pin function is MCLR
0 = MCLR pin function is digital input, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<2:0>: Oscillator Selection bits
111 = EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin
110 = EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin
101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on
RA5/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on
RA5/OSC1/CLKIN
011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
2007 Microchip Technology Inc. DS41203D-page 111
PIC16F688
11.2 Reset They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
The PIC16F688 differentiates between various kinds of PD bits are set or cleared differently in different Reset
Reset: situations, as indicated in Table 11-2. These bits are
used in software to determine the nature of the Reset.
a) Power-on Reset (POR) See Table 11-4 for a full description of Reset states of
b) WDT Reset during normal operation all registers.
c) WDT Reset during Sleep
d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit
e) MCLR Reset during Sleep is shown in Figure 11-1.
f) Brown-out Reset (BOR)
The MCLR Reset path has a noise filter to detect and
Some registers are not affected in any Reset condition; ignore small pulses. See Section 14.0 "Electrical
their status is unknown on POR and unchanged in any Specifications" for pulse width specifications.
other Reset. Most other registers are reset to a "Reset
state" on:
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
FIGURE 11-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin Sleep
VDD
WDT WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
Brown-out(1)
Reset BOREN
SBOREN S
OST/PWRT Chip_Reset
OST
10-bit Ripple Counter R Q
OSC1/
CLKI pin
PWRT
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: Refer to the Configuration Word register (Register 11-1).
DS41203D-page 112 2007 Microchip Technology Inc.
PIC16F688
11.2.1 POWER-ON RESET FIGURE 11-2: RECOMMENDED MCLR
CIRCUIT
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper VDD PIC16F688
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This R1
will eliminate external RC components usually needed 1 k (or greater)
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 14.0 "Electrical Specifi- MCLR
cations" for details. If the BOR is enabled, the maxi-
mum rise time specification does not apply. The BOR C1
circuitry will keep the device in Reset until VDD reaches 0.1 F
VBOD (see Section 11.2.4 "Brown-Out Reset (optional, not critical)
(BOR)").
Note: The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss 11.2.3 POWER-UP TIMER (PWRT)
for a minimum of 100 s.
The Power-up Timer provides a fixed 64 ms (nominal)
When the device starts normal operation (exits the time-out on power-up only, from POR or Brown-out
Reset condition), device operating parameters (i.e., Reset. The Power-up Timer operates from the 31 kHz
voltage, frequency, temperature, etc.) must be met to LFINTOSC oscillator. For more information, see
ensure operation. If these conditions are not met, the Section 3.5 "Internal Clock Modes". The chip is kept
device must be held in Reset until the operating in Reset as long as PWRT is active. The PWRT delay
conditions are met. allows the VDD to rise to an acceptable level. A Config-
uration bit, PWRTE, can disable (if set) or enable (if
For additional information, refer to Application Note cleared or programmed) the Power-up Timer. The
AN607, "Power-up Trouble Shooting" (DS00607). Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
11.2.2 MCLR
The Power-up Timer delay will vary from chip-to-chip
PIC16F688 has a noise filter in the MCLR Reset path. and vary due to:
The filter will detect and ignore small pulses.
VDD variation
It should be noted that a WDT Reset does not drive
MCLR pin low. Temperature variation
The behavior of the ESD protection on the MCLR pin Process variation
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification See DC parameters for details (Section 14.0
can result in both MCLR Resets and excessive current "Electrical Specifications").
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR Note: Voltage spikes below VSS at the MCLR
pin no longer be tied directly to VDD. The use of an RC pin, inducing currents greater than 80 mA,
network, as shown in Figure 11-2, is suggested. may cause latch-up. Thus, a series resis-
tor of 50-100 should be used when
An internal MCLR option is enabled by clearing the applying a "low" level to the MCLR pin,
MCLRE bit in the Configuration Word register. When rather than pulling this pin directly to VSS.
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD.
2007 Microchip Technology Inc. DS41203D-page 113
PIC16F688
11.2.4 BROWN-OUT RESET (BOR) This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOD for less
The BOREN0 and BOREN1 bits in the Configuration than parameter (TBOD).
Word register selects one of four BOR modes. Two
modes have been added to allow software or hardware On any Reset (Power-on, Brown-out Reset, Watchdog
control of the BOR enable. When BOREN<1:0> = 01, Timer, etc.), the chip will remain in Reset until VDD rises
the SBOREN bit of the PCON register enables/disables above VBOD (see Figure 11-3). The Power-up Timer
the BOR, allowing it to be controlled in software. By will now be invoked, if enabled and will keep the chip in
selecting BOREN<1:0>, the BOR is automatically Reset an additional 64 ms.
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled. Note: The Power-up Timer is enabled by the
See Register 11-1 for the Configuration Word PWRTE bit in the Configuration Word
definition. register.
If VDD falls below VBOD for greater than parameter If VDD drops below VBOD while the Power-up Timer is
(TBOD) (see Section 14.0 "Electrical Specifica- running, the chip will go back into a Brown-out Reset
tions"), the Brown-out situation will reset the device. and the Power-up Timer will be re-initialized. Once VDD
rises above VBOD, the Power-up Timer will execute a
64 ms Reset.
FIGURE 11-3: BROWN-OUT SITUATIONS
VDD VBOD
VBOD
Internal 64 ms(1) VBOD
Reset
VDD
Internal < 64 ms 64 ms(1)
Reset
VDD
Internal 64 ms(1)
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to `0'.
DS41203D-page 114 2007 Microchip Technology Inc.
PIC16F688
11.2.5 TIME-OUT SEQUENCE 11.2.6 POWER CONTROL (PCON)
REGISTER
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then The Power Control (PCON) register (address 8Eh) has
OST is activated after the PWRT time-out has expired. two Status bits to indicate what type of Reset that last
The total time-out will vary based on oscillator configu- occurred.
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit erased (PWRT disabled), there will be Bit 0 is BOR (Brown-out). BOR is unknown on
no time-out at all. Figure 11.2.1, Figure 11-5 and Power-on Reset. It must then be set by the user and
Figure 11-6 depict time-out sequences. The device can checked on subsequent Resets to see if BOR = 0,
execute code from the INTOSC while OST is active by indicating that a Brown-out has occurred. The BOR
enabling Two-Speed Start-up or Fail-Safe Monitor (see Status bit is a "don't care" and is not necessarily
Section 3.7.2 "Two-Speed Start-up Sequence" and predictable if the brown-out circuit is disabled
Section 3.8 "Fail-Safe Clock Monitor"). (BOREN<1:0> = 00 in the Configuration Word
register).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then, Bit 1 is POR (Power-on Reset). It is a `0' on Power-on
bringing MCLR high will begin execution immediately Reset and unaffected otherwise. The user must write a
(see Figure 11-5). This is useful for testing purposes or `1' to this bit following a Power-on Reset. On a
to synchronize more than one PIC16F688 device subsequent Reset, if POR is `0', it will indicate that a
operating in parallel. Power-on Reset has occurred (i.e., VDD may have
gone too low).
Table 11-5 shows the Reset conditions for some
special registers, while Table 11-4 shows the Reset For more information, see Section 4.2.4 "Ultra
conditions for all the registers. Low-Power Wake-up" and Section 11.2.4
"Brown-Out Reset (BOR)".
TABLE 11-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset Wake-up
PWRTE = 0 PWRTE = 1 from Sleep
Oscillator Configuration 1024 TOSC
XT, HS, LP TPWRT + 1024 1024 TOSC PWRTE = 0 PWRTE = 1 --
RC, EC, INTOSC TOSC -- 1024 TOSC
TPWRT + 1024
TPWRT TOSC --
TPWRT
TABLE 11-2: PCON BITS AND THEIR SIGNIFICANCE
POR BOR TO PD Condition
0 u 1 1 Power-on Reset
1 0 1 1 Brown-out Reset
u u 0 u WDT Reset
u u 0 0 WDT Wake-up
u u u u MCLR Reset during normal operation
u u 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Name Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Value on
POR, BOR all other
Resets(1)
CONFIG(2) BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 -- --
PCON -- -- ULPWUE SBOREN -- -- POR BOR --01 --qq --0u --uu
STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 11-1) for operation of all register bits.
2:
2007 Microchip Technology Inc. DS41203D-page 115
PIC16F688
FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD TPWRT
MCLR
Internal POR TOST
PWRT Time-out
OST Time-out
Internal Reset
FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD TPWRT
MCLR
Internal POR TOST
PWRT Time-out
OST Time-out
Internal Reset
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD TPWRT
MCLR
Internal POR TOST
PWRT Time-out
OST Time-out
Internal Reset
DS41203D-page 116 2007 Microchip Technology Inc.
PIC16F688
TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on MCLR Reset Wake-up from Sleep
Reset through Interrupt
WDT Reset
Brown-out Reset(1) Wake-up from Sleep
through WDT Time-out
W -- xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/100h/180h xxxx xxxx uuuu uuuu uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h/105h --x0 x000 --00 0000 --uu uuuu
PORTC 07h/107h --xx 0000 --00 0000 --uu uuuu
PCLATH 0Ah/8Ah/10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2)
PIR1 0000 0000 0000 0000 uuuu uuuu(2)
0Ch
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu
BAUDCTL 11h 01-0 0-00 01-0 0-00 uu-u u-uu
SPBRGH 12h -000 0000 -000 0000 -uuu uuuu
SPBRG 13h 0000 0000 0000 0000 uuuu uuuu
RCREG 14h 0000 0000 0000 0000 uuuu uuuu
TXREG 15h 0000 0000 0000 0000 uuuu uuuu
TXSTA 16h 0000 0010 0000 0010 uuuu uuuu
RCSTA 17h 000x 000x 000x 000x uuuu uuuu
WDTCON 18h ---0 1000 ---0 1000 ---u uuuu
CMCON0 19h 0000 0000 0000 0000 uuuu uuuu
CMCON1 1Ah ---- --10 ---- --10 ---- --uu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h/185h --11 1111 --11 1111 --uu uuuu
TRISC 87h/187h --11 1111 --11 1111 --uu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON --uu --uu
8Eh --01 --0x --0u --uu(1,5)
Legend: u = unchanged, x = unknown, = unimplemented bit, reads as `0', q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
3: vector (0004h).
See Table 11-5 for Reset value for specific condition.
4: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
5:
2007 Microchip Technology Inc. DS41203D-page 117
PIC16F688
TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on MCLR Reset Wake-up from Sleep
Reset through interrupt
WDT Reset
Brown-out Reset(1) Wake-up from Sleep
through WDT time-out
OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu
OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu
ANSEL 91h 1111 1111 1111 1111 uuuu uuuu
WPUA 95h --11 -111 --11 -111 uuuu uuuu
IOCA 96h --00 0000 --00 0000 --uu uuuu
EEDATH 97h --00 0000 --00 0000 --uu uuuu
EEADRH 98h ---- 0000 ---- 0000 ---- uuuu
VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu
EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu
EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu
EECON1 9Ch x--- x000 u--- q000 u--- uuuu
EECON2 9Dh ---- ---- ---- ---- ---- ----
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
Legend: u = unchanged, x = unknown, = unimplemented bit, reads as `0', q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
3: vector (0004h).
See Table 11-5 for Reset value for specific condition.
4: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
5:
TABLE 11-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Status PCON
Counter Register Register
Power-on Reset 000h 0001 1xxx --01 --0x
MCLR Reset during normal operation 000h 000u uuuu --0u --uu
MCLR Reset during Sleep 000h 0001 0uuu --0u --uu
WDT Reset 000h 0000 uuuu --0u --uu
WDT Wake-up PC + 1 uuu0 0uuu --uu --uu
Brown-out Reset 000h 0001 1uuu --01 --10
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu
Legend: u = unchanged, x = unknown, = unimplemented bit, reads as `0'.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
DS41203D-page 118 2007 Microchip Technology Inc.
11.3 Interrupts PIC16F688
The PIC16F688 has multiple sources of interrupt: For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
External Interrupt RA2/INT three or four instruction cycles. The exact latency
TMR0 Overflow Interrupt depends upon when the interrupt event occurs (see
PORTA Change Interrupts Figure 11-8). The latency is the same for one or
2 Comparator Interrupts two-cycle instructions. Once in the Interrupt Service
A/D Interrupt Routine, the source(s) of the interrupt can be
Timer1 Overflow Interrupt determined by polling the interrupt flag bits. The
EEPROM Data Write Interrupt interrupt flag bit(s) must be cleared in software before
Fail-Safe Clock Monitor Interrupt re-enabling interrupts to avoid multiple interrupt
EUSART Receive and Transmit interrupts requests.
The Interrupt Control (INTCON) register and Peripheral Note 1: Individual interrupt flag bits are set,
Interrupt Request 1 (PIR1) register record individual regardless of the status of their
interrupt requests in flag bits. The INTCON register corresponding mask bit or the GIE bit.
also has individual and global interrupt enable bits.
2: When an instruction that clears the GIE
A Global Interrupt Enable bit, GIE bit of the INTCON bit is executed, any interrupts that were
register, enables (if set) all unmasked interrupts, or dis- pending for execution in the next cycle
ables (if cleared) all interrupts. Individual interrupts can are ignored. The interrupts, which were
be disabled through their corresponding enable bits in ignored, are still pending to be serviced
the INTCON register and PIE1 register. GIE is cleared when the GIE bit is set again.
on Reset.
For additional information on Timer1, A/D or data
The Return from Interrupt instruction, RETFIE, exits EEPROM modules, refer to the respective peripheral
the interrupt routine, as well as sets the GIE bit, which section.
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
INT Pin Interrupt
PORTA Change Interrupt
TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
EEPROM Data Write Interrupt
A/D Interrupt
EUSART Receive and Transmit Interrupts
2 Comparator Interrupts
Timer1 Overflow Interrupt
Fail-Safe Clock Monitor Interrupt
When an interrupt is serviced:
The GIE is cleared to disable any further interrupt.
The return address is pushed onto the stack.
The PC is loaded with 0004h.
2007 Microchip Technology Inc. DS41203D-page 119
PIC16F688
11.3.1 RA2/INT INTERRUPT 11.3.2 TIMER0 INTERRUPT
External interrupt on RA2/INT pin is edge-triggered; An overflow (FFh 00h) in the TMR0 register will set
either rising if the INTEDG bit of the OPTION register is the T0IF of the INTCON register bit. The interrupt can
set, or falling if the INTEDG bit is clear. When a valid be enabled/disabled by setting/clearing T0IE bit of the
edge appears on the RA2/INT pin, the INTF bit of the INTCON register. See Section 5.0 "Timer0 Module"
INTCON register is set. This interrupt can be disabled for operation of the Timer0 module.
by clearing the INTE control bit of the INTCON register.
The INTF bit must be cleared in software in the Inter- 11.3.3 PORTA INTERRUPT
rupt Service Routine before re-enablin
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