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PI6C20400ALEX

器件型号:PI6C20400ALEX
器件类别:半导体    模拟混合信号IC   
厂商名称:Diodes
厂商官网:http://www.diodes.com/
标准:
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器件描述

IC CLOCK BUFFER 1:4 28TSSOP

参数
产品属性属性值
PLL:
主要用途:PCI Express(PCIe)
输入:HCSL
输出:HCSL
电路数:1
比率 - 输入:输出:1:4
差分 - 输入:输出:是/是
频率 - 最大值:400MHz
电压 - 电源:3.135 V ~ 3.465 V
工作温度:-40°C ~ 85°C
安装类型:表面贴装
封装/外壳:28-TSSOP(0.173",4.40mm 宽)
供应商器件封装:28-TSSOP

文档预览

PI6C20400A
1:4 Clock Driver for Intel PCIe® Chipsets
Features
• Phase jitter filter for PCIe® 2.0 application
• Four Pairs of Differential Clocks
• Low skew < 50ps
• Low jitter < 50ps cycle-to-cycle
• < 1 ps additive RMS phase jitter
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Programmable PLL Bandwidth
• 100 MHz PLL Mode operation
• 100 - 400 MHz Bypass Mode operation
• 3.3V Operation
• Packaging (Pb-free and Green):
→28-Pin SSOP (H28)
→28-Pin TSSOP (L28)
Description
Pericom Semiconductor's PI6C20400A is a PCIe® 2.0 compliant
high-speed, low-noise differential clock buffer designed to be
companion to PI6C410BS. The device distributes the differential
SRC clock from PI6C410BS to four differential pairs of clock
outputs either with or without PLL. The clock outputs are
controlled by input selection of SRC_STOP#, PWRDWN# and
SMBus, SCLK and SDA. When input of either SRC_STOP#
or PWRDWN# is low, the output clocks are Tristated. When
PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.
Block Diagram
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
Pin Configuration
V
DD
SRC
SRC#
V
SS
V
DD
OUT0
OUT0#
OE_0
OUT1
OUT1#
V
DD
PLL/BYPASS#
SCLK
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Output
Control
OUT0
OUT0#
SMBus
Controller
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
SCLK
SDA
PLL/BYPASS#
SRC
SRC#
PLL_BW#
DIV
PLL
V
DD_A
V
SS_A
I
REF
OE_INV
V
DD
OUT3
OUT3#
OE_3
OUT2
OUT2#
V
DD
PLL_BW#
SRC_STOP#
PWRDWN#
14-0195
1
www.pericom.com
03/27/13
1:4 Clock Driver for Intel PCIe® Chipsets
Pin Descriptions
Pin
Name
SRC & SRC#
OE_0 & OE_3
Type
Input
Input
2, 3
8, 21
Pin No
Description
0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active high.
OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted.
0.7V Differential outputs
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active low
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active low
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
PI6C20400A
OE_INV
Input
25
6, 7, 9, 10, 19, 20,
22, 23
12
13
14
26
16
17
15
1, 5, 11, 18, 24
4
27
28
OUT[0:3] & OUT[0:3]#
PLL/BYPASS#
SCLK
SDA
IREF
SRC_STOP#
PLL_BW#
PWRDWN#
V
DD
VSS
VSS_A
VDD_A
Output
Input
Input
I/O
Input
Input
Input
Input
Power
Ground
Ground
Power
Serial Data Interface (SMBus)
This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
W/R
0/1
Data Protocol
1 bit
Start
bit
7 bits
Slave
Addr
1
R/W
1
Ack
8 bits
1
8 bits
Byte
Count
= N
1
Ack
8 bits
Data
Byte 0
1
Ack
8 bits
Data
Byte N
- 1
1
Ack
1 bit
Stop
bit
Register
Ack
offset
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
14-0195
2
www.pericom.com
03/27/13
1:4 Clock Driver for Intel PCIe® Chipsets
Data Byte 0: Control Register
Bit
0
Descriptions
Outputs Mode
0 = Divide by 2
1 = Normal
PLL/BYPASS#
0 = Fanout
1 = PLL
PLL Bandwidth
0 = High Bandwidth,
1 = Low Bandwidth
Reserved
Reserved
Reserved
SRC_STOP#
0 = Driven when stopped
1 = Tristate
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
Type
RW
Power Up Condition
1 = Normal
Output(s) Affected
OUT[0:3], OUT[0:3]#
Source
Pin
NA
PI6C20400A
1
RW
1 = PLL
OUT[0:3], OUT[0:3]#
NA
2
3
4
5
6
RW
1 = Low
OUT[0:3], OUT[0:3]#
NA
NA
NA
NA
NA
7
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
NA
Data Byte 1: Control Register
Bit
0
1
2
3
4
5
6
7
Reserved
OUTPUTS enable
1 = Enabled
0 = Disabled
Reserved
Reserved
OUTPUTS enable
1 = Enabled
0 = Disabled
Reserved
RW
RW
1 = Enabled
1 = Enabled
OUT2, OUT2#
OUT3, OUT3#
RW
RW
1 = Enabled
1 = Enabled
OUT0, OUT0#
OUT1, OUT1#
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
NA
NA
NA
NA
NA
NA
NA
NA
14-0195
3
www.pericom.com
03/27/13
1:4 Clock Driver for Intel PCIe® Chipsets
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
7
Reserved
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
Reserved
Reserved
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
Reserved
RW
RW
0 = Free running
0 = Free running
OUT2, OUT2#
OUT3, OUT3#
RW
RW
0 = Free running
0 = Free running
OUT0, OUT0#
OUT1, OUT1#
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
NA
NA
NA
NA
NA
NA
NA
NA
PI6C20400A
Data Byte 3: Control Register
Bit
0
1
2
3
4
5
6
7
Reserved
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
Output(s) Affected
Source
Pin
Data Byte 4: Pericom ID Register
Bit
0
1
2
3
4
5
6
7
Pericom ID
Descriptions
Type
R
R
R
R
R
R
R
R
Power Up Condition
0
0
0
0
0
1
0
0
Output(s) Affected
NA
NA
NA
NA
NA
NA
NA
NA
Pin
NA
NA
NA
NA
NA
NA
NA
NA
14-0195
4
www.pericom.com
03/27/13
1:4 Clock Driver for Intel PCIe® Chipsets
Functionality
PWRDWN#
1
0
OUT
Normal
I
REF
× 2 or Float
OUT#
Normal
Low
SRC_Stop#
1
0
OUT
Normal
I
REF
× 6 or Float
OUT#
Normal
Low
PI6C20400A
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
14-0195
5
www.pericom.com
03/27/13
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