MC9S08RC8/16/32/60
MC9S08RD8/16/32/60
MC9S08RE8/16/32/60
MC9S08RG32/60
Data Sheet
HCS08
Microcontrollers
MC9S08RG60/D
Rev. 1.11
06/2005
freescale.com
MC9S08RG60 Data Sheet
Covers: MC9S08RC8/16/32/60
MC9S08RD8/16/32/60
MC9S08RE8/16/32/60
MC9S08RG32/60
MC9S08RG60/D
Rev. 1.11
06/2005
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Version Revision Description of Changes
Number Date
Added 48 QFN package and official mechanical drawings; suppled
1.11 06/2005 TBD values for IRO VOL; updated tRTI values; re-emphasized that
KBI2 will not wake the MCU from stop2 mode.
This product contains SuperFlash technology licensed from SST.
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc., 2005. All rights reserved.
List of Chapters
Chapter 1 Introduction............................................................................. 15
Chapter 2 Pins and Connections ............................................................ 19
Chapter 3 Modes of Operation ................................................................ 29
Chapter 4 Memory .................................................................................... 35
Chapter 5 Resets, Interrupts, and System Configuration .................... 57
Chapter 6 Parallel Input/Output .............................................................. 73
Chapter 7 Central Processor Unit (S08CPUV2) ..................................... 87
Chapter 8 Carrier Modulator Timer (S08CMTV1)................................. 107
Chapter 9 Keyboard Interrupt (S08KBIV1) ........................................... 123
Chapter 10 Timer/PWM Module (S08TPMV1)......................................... 129
Chapter 11 Serial Communications Interface (S08SCIV1).................... 145
Chapter 12 Serial Communications Interface (S08SCIV1).................... 147
Chapter 13 Serial Peripheral Interface (S08SPIV3) ............................... 163
Chapter 14 Analog Comparator (S08ACMPV1) ..................................... 179
Chapter 15 Development Support .......................................................... 183
Appendix A Electrical Characteristics..................................................... 205
Appendix B Ordering Information and Mechanical Drawings............... 219
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 5
Section Number Contents Page
Title
Chapter 1
Introduction
1.1 Overview .........................................................................................................................................15
1.2 Features ...........................................................................................................................................15
1.2.1 Devices in the MC9S08RC/RD/RE/RG Series ..............................................................16
1.3 MCU Block Diagram ......................................................................................................................17
1.4 System Clock Distribution ..............................................................................................................18
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................19
2.2 Device Pin Assignment ...................................................................................................................19
2.3 Recommended System Connections ...............................................................................................21
2.3.1 Power ..............................................................................................................................23
2.3.2 Oscillator ........................................................................................................................23
2.3.3 PTD1/RESET .................................................................................................................23
2.3.4 Background/Mode Select (PTD0/BKGD/MS) ...............................................................24
2.3.5 IRO Pin Description .......................................................................................................24
2.3.6 General-Purpose I/O and Peripheral Ports .....................................................................24
2.3.7 Signal Properties Summary ............................................................................................25
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................29
3.2 Features ...........................................................................................................................................29
3.3 Run Mode ........................................................................................................................................29
3.4 Active Background Mode ................................................................................................................29
3.5 Wait Mode .......................................................................................................................................30
3.6 Stop Modes ......................................................................................................................................31
3.6.1 Stop1 Mode ....................................................................................................................31
3.6.2 Stop2 Mode ....................................................................................................................31
3.6.3 Stop3 Mode ....................................................................................................................32
3.6.4 Active BDM Enabled in Stop Mode ...............................................................................33
3.6.5 LVD Reset Enabled ........................................................................................................33
3.6.6 On-Chip Peripheral Modules in Stop Mode ...................................................................33
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 7
Section Number Title Page
Chapter 4
Memory
4.1 MC9S08RC/RD/RE/RG Memory Map ..........................................................................................35
4.1.1 Reset and Interrupt Vector Assignments ........................................................................36
4.2 Register Addresses and Bit Assignments ........................................................................................38
4.3 RAM ................................................................................................................................................42
4.4 FLASH ............................................................................................................................................42
4.4.1 Features ...........................................................................................................................43
4.4.2 Program and Erase Times ...............................................................................................43
4.4.3 Program and Erase Command Execution .......................................................................44
4.4.4 Burst Program Execution ...............................................................................................45
4.4.5 Access Errors ..................................................................................................................46
4.4.6 FLASH Block Protection ...............................................................................................47
4.4.7 Vector Redirection ..........................................................................................................48
4.5 Security ............................................................................................................................................48
4.6 FLASH Registers and Control Bits .................................................................................................49
4.6.1 FLASH Clock Divider Register (FCDIV) ......................................................................49
4.6.2 FLASH Options Register (FOPT and NVOPT) .............................................................51
4.6.3 FLASH Configuration Register (FCNFG) .....................................................................51
4.6.4 FLASH Protection Register (FPROT and NVPROT) ....................................................52
4.6.5 FLASH Status Register (FSTAT) ...................................................................................54
4.6.6 FLASH Command Register (FCMD) ............................................................................55
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction .....................................................................................................................................57
5.2 Features ...........................................................................................................................................57
5.3 MCU Reset ......................................................................................................................................57
5.4 Computer Operating Properly (COP) Watchdog .............................................................................58
5.5 Interrupts .........................................................................................................................................58
5.5.1 Interrupt Stack Frame .....................................................................................................59
5.5.2 External Interrupt Request (IRQ) Pin .............................................................................60
5.5.2.1 Pin Configuration Options ..............................................................................60
5.5.2.2 Edge and Level Sensitivity ..............................................................................61
5.5.3 Interrupt Vectors, Sources, and Local Masks .................................................................61
5.6 Low-Voltage Detect (LVD) System ................................................................................................62
5.6.1 Power-On Reset Operation .............................................................................................63
5.6.2 LVD Reset Operation .....................................................................................................63
5.6.3 LVD Interrupt and Safe State Operation ........................................................................63
5.6.4 Low-Voltage Warning (LVW) ........................................................................................63
5.7 Real-Time Interrupt (RTI) ...............................................................................................................64
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
8 Freescale Semiconductor
Section Number Title Page
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................64
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) .........................................64
5.8.2 System Reset Status Register (SRS) ...............................................................................65
5.8.3 System Background Debug Force Reset Register (SBDFR) ..........................................67
5.8.4 System Options Register (SOPT) ...................................................................................68
5.8.5 System Device Identification Register (SDIDH, SDIDL) ..............................................69
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) .............................70
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) .........................71
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) .........................72
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................73
6.2 Features ...........................................................................................................................................73
6.3 Pin Descriptions ..............................................................................................................................74
6.3.1 Port A ..............................................................................................................................74
6.3.2 Port B ..............................................................................................................................74
6.3.3 Port C ..............................................................................................................................75
6.3.4 Port D ..............................................................................................................................75
6.3.5 Port E ..............................................................................................................................76
6.4 Parallel I/O Controls ........................................................................................................................76
6.4.1 Data Direction Control ...................................................................................................76
6.4.2 Internal Pullup Control ...................................................................................................77
6.5 Stop Modes ......................................................................................................................................77
6.6 Parallel I/O Registers and Control Bits ...........................................................................................77
6.6.1 Port A Registers (PTAD, PTAPE, and PTADD) ............................................................78
6.6.2 Port B Registers (PTBD, PTBPE, and PTBDD) ............................................................79
6.6.3 Port C Registers (PTCD, PTCPE, and PTCDD) ............................................................81
6.6.4 Port D Registers (PTDD, PTDPE, and PTDDD) ...........................................................82
6.6.5 Port E Registers (PTED, PTEPE, and PTEDD) .............................................................84
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction .....................................................................................................................................87
7.1.1 Features ...........................................................................................................................87
7.2 Programmer's Model and CPU Registers .......................................................................................88
7.2.1 Accumulator (A) .............................................................................................................88
7.2.2 Index Register (H:X) ......................................................................................................88
7.2.3 Stack Pointer (SP) ...........................................................................................................89
7.2.4 Program Counter (PC) ....................................................................................................89
7.2.5 Condition Code Register (CCR) .....................................................................................89
7.3 Addressing Modes ...........................................................................................................................90
7.3.1 Inherent Addressing Mode (INH) ..................................................................................91
7.3.2 Relative Addressing Mode (REL) ..................................................................................91
7.3.3 Immediate Addressing Mode (IMM) .............................................................................91
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 9
Section Number Title Page
7.3.4 Direct Addressing Mode (DIR) ......................................................................................91
7.3.5 Extended Addressing Mode (EXT) ................................................................................91
7.3.6 Indexed Addressing Mode ..............................................................................................91
7.3.6.1 Indexed, No Offset (IX) ..................................................................................92
7.3.6.2 Indexed, No Offset with Post Increment (IX+) ...............................................92
7.3.6.3 Indexed, 8-Bit Offset (IX1) .............................................................................92
7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+) .........................................92
7.3.6.5 Indexed, 16-Bit Offset (IX2) ...........................................................................92
7.3.6.6 SP-Relative, 8-Bit Offset (SP1) ......................................................................92
7.3.6.7 SP-Relative, 16-Bit Offset (SP2) ....................................................................92
7.4 Special Operations ...........................................................................................................................92
7.4.1 Reset Sequence ...............................................................................................................93
7.4.2 Interrupt Sequence ..........................................................................................................93
7.4.3 Wait Mode Operation .....................................................................................................94
7.4.4 Stop Mode Operation .....................................................................................................94
7.4.5 BGND Instruction ..........................................................................................................94
7.5 HCS08 Instruction Set Summary ....................................................................................................95
Chapter 8
Carrier Modulator Timer (S08CMTV1)
8.1 Introduction ...................................................................................................................................107
8.2 Features .........................................................................................................................................108
8.3 CMT Block Diagram .....................................................................................................................108
8.4 Pin Description ..............................................................................................................................108
8.5 Functional Description ..................................................................................................................109
8.5.1 Carrier Generator ..........................................................................................................110
8.5.2 Modulator .....................................................................................................................112
8.5.2.1 Time Mode ....................................................................................................113
8.5.2.2 Baseband Mode .............................................................................................114
8.5.2.3 FSK Mode .....................................................................................................114
8.5.3 Extended Space Operation ...........................................................................................115
8.5.3.1 EXSPC Operation in Time Mode .................................................................115
8.5.3.2 EXSPC Operation in FSK Mode ..................................................................116
8.5.4 Transmitter ....................................................................................................................116
8.5.5 CMT Interrupts .............................................................................................................117
8.5.6 Wait Mode Operation ...................................................................................................117
8.5.7 Stop Mode Operation ...................................................................................................117
8.5.8 Background Mode Operation .......................................................................................118
8.6 CMT Registers and Control Bits ...................................................................................................118
8.6.1 Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and
CMTCGL2) ..............................................................................................................118
8.6.2 CMT Output Control Register (CMTOC) ....................................................................120
8.6.3 CMT Modulator Status and Control Register (CMTMSC) ..........................................121
8.6.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3, and
CMTCMD4) .............................................................................................................122
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
10 Freescale Semiconductor
Section Number Title Page
Chapter 9
Keyboard Interrupt (S08KBIV1)
9.1 Introduction ...................................................................................................................................123
9.2 KBI Block Diagram ......................................................................................................................125
9.3 Keyboard Interrupt (KBI) Module ................................................................................................125
9.3.1 Pin Enables ...................................................................................................................125
9.3.2 Edge and Level Sensitivity ...........................................................................................125
9.3.3 KBI Interrupt Controls .................................................................................................126
9.4 KBI Registers and Control Bits .....................................................................................................126
9.4.1 KBI x Status and Control Register (KBIxSC) ..............................................................127
9.4.2 KBI x Pin Enable Register (KBIxPE) ..........................................................................128
Chapter 10
Timer/PWM Module (S08TPMV1)
10.1 Introduction ...................................................................................................................................129
10.2 Features .........................................................................................................................................129
10.3 TPM Block Diagram .....................................................................................................................131
10.4 Pin Descriptions ............................................................................................................................132
10.4.1 External TPM Clock Sources .......................................................................................132
10.4.2 TPM1CHn -- TPM1 Channel n I/O Pins .....................................................................132
10.5 Functional Description ..................................................................................................................132
10.5.1 Counter .........................................................................................................................133
10.5.2 Channel Mode Selection ...............................................................................................134
10.5.2.1 Input Capture Mode ......................................................................................134
10.5.2.2 Output Compare Mode .................................................................................134
10.5.2.3 Edge-Aligned PWM Mode ...........................................................................134
10.5.3 Center-Aligned PWM Mode ........................................................................................135
10.6 TPM Interrupts ..............................................................................................................................137
10.6.1 Clearing Timer Interrupt Flags .....................................................................................137
10.6.2 Timer Overflow Interrupt Description ..........................................................................137
10.6.3 Channel Event Interrupt Description ............................................................................137
10.6.4 PWM End-of-Duty-Cycle Events .................................................................................138
10.7 TPM Registers and Control Bits ...................................................................................................138
10.7.1 Timer Status and Control Register (TPM1SC) .............................................................139
10.7.2 Timer Counter Registers (TPM1CNTH:TPM1CNTL) ................................................140
10.7.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) ................................141
10.7.4 Timer Channel n Status and Control Register (TPM1CnSC) .......................................142
10.7.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL) .......................................143
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 11
Section Number Title Page
Chapter 11
Serial Communications Interface (S08SCIV1)
11.1 Introduction ...................................................................................................................................145
Chapter 12
Serial Communications Interface (S08SCIV1)
12.1 Introduction ...................................................................................................................................147
12.1.1 Features .........................................................................................................................147
12.1.2 Modes of Operation ......................................................................................................147
12.1.3 Block Diagram ..............................................................................................................148
12.2 Register Definition ........................................................................................................................150
12.2.1 SCI Baud Rate Registers (SCI1BDH, SCI1BHL) ........................................................150
12.2.2 SCI Control Register 1 (SCI1C1) .................................................................................151
12.2.3 SCI Control Register 2 (SCI1C2) .................................................................................152
12.2.4 SCI Status Register 1 (SCI1S1) ....................................................................................153
12.2.5 SCI Status Register 2 (SCI1S2) ....................................................................................155
12.2.6 SCI Control Register 3 (SCI1C3) .................................................................................155
12.2.7 SCI Data Register (SCI1D) ..........................................................................................156
12.3 Functional Description ..................................................................................................................157
12.3.1 Baud Rate Generation ...................................................................................................157
12.3.2 Transmitter Functional Description ..............................................................................157
12.3.2.1 Send Break and Queued Idle .........................................................................158
12.3.3 Receiver Functional Description ..................................................................................158
12.3.3.1 Data Sampling Technique .............................................................................159
12.3.3.2 Receiver Wakeup Operation .........................................................................159
12.3.4 Interrupts and Status Flags ...........................................................................................160
12.3.5 Additional SCI Functions .............................................................................................161
12.3.5.1 8- and 9-Bit Data Modes ...............................................................................161
12.3.5.2 Stop Mode Operation ....................................................................................161
12.3.5.3 Loop Mode ....................................................................................................161
12.3.5.4 Single-Wire Operation ..................................................................................162
Chapter 13
Serial Peripheral Interface (S08SPIV3)
13.1 Features .........................................................................................................................................164
13.2 Block Diagrams .............................................................................................................................164
13.2.1 SPI System Block Diagram ..........................................................................................164
13.2.2 SPI Module Block Diagram .........................................................................................165
13.2.3 SPI Baud Rate Generation ............................................................................................167
13.3 Functional Description ..................................................................................................................167
13.3.1 SPI Clock Formats ........................................................................................................168
13.3.2 SPI Pin Controls ...........................................................................................................170
13.3.2.1 SPSCK1 -- SPI Serial Clock ........................................................................170
13.3.2.2 MOSI1 -- Master Data Out, Slave Data In ..................................................170
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
12 Freescale Semiconductor
Section Number Title Page
13.3.2.3 MISO1 -- Master Data In, Slave Data Out ..................................................170
13.3.2.4 SS1 -- Slave Select .......................................................................................170
13.3.3 SPI Interrupts ................................................................................................................171
13.3.4 Mode Fault Detection ...................................................................................................171
13.4 SPI Registers and Control Bits ......................................................................................................171
13.4.1 SPI Control Register 1 (SPI1C1) ..................................................................................172
13.4.2 SPI Control Register 2 (SPI1C2) ..................................................................................173
13.4.3 SPI Baud Rate Register (SPI1BR) ...............................................................................174
13.4.4 SPI Status Register (SPI1S) ..........................................................................................176
13.4.5 SPI Data Register (SPI1D) ...........................................................................................177
Chapter 14
Analog Comparator (S08ACMPV1)
14.1 Features .........................................................................................................................................180
14.2 Block Diagram ..............................................................................................................................180
14.3 Pin Description ..............................................................................................................................180
14.4 Functional Description ..................................................................................................................181
14.4.1 Interrupts .......................................................................................................................181
14.4.2 Wait Mode Operation ...................................................................................................181
14.4.3 Stop Mode Operation ...................................................................................................181
14.4.4 Background Mode Operation .......................................................................................181
14.5 ACMP Status and Control Register (ACMP1SC) .........................................................................182
Chapter 15
Development Support
15.1 Introduction ...................................................................................................................................183
15.1.1 Features .........................................................................................................................183
15.2 Background Debug Controller (BDC) ..........................................................................................184
15.2.1 BKGD Pin Description .................................................................................................184
15.2.2 Communication Details ................................................................................................185
15.2.3 BDC Commands ...........................................................................................................189
15.2.4 BDC Hardware Breakpoint ..........................................................................................191
15.3 On-Chip Debug System (DBG) ....................................................................................................192
15.3.1 Comparators A and B ...................................................................................................192
15.3.2 Bus Capture Information and FIFO Operation .............................................................192
15.3.3 Change-of-Flow Information ........................................................................................193
15.3.4 Tag vs. Force Breakpoints and Triggers .......................................................................193
15.3.5 Trigger Modes ..............................................................................................................194
15.3.6 Hardware Breakpoints ..................................................................................................196
15.4 Register Definition ........................................................................................................................196
15.4.1 BDC Registers and Control Bits ...................................................................................196
15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................197
15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................198
15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................198
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 13
Section Number Title Page
15.4.3 DBG Registers and Control Bits ..................................................................................199
15.4.3.1 Debug Comparator A High Register (DBGCAH) ........................................199
15.4.3.2 Debug Comparator A Low Register (DBGCAL) .........................................199
15.4.3.3 Debug Comparator B High Register (DBGCBH) .........................................199
15.4.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................199
15.4.3.5 Debug FIFO High Register (DBGFH) ..........................................................200
15.4.3.6 Debug FIFO Low Register (DBGFL) ...........................................................200
15.4.3.7 Debug Control Register (DBGC) ..................................................................201
15.4.3.8 Debug Trigger Register (DBGT) ..................................................................202
15.4.3.9 Debug Status Register (DBGS) .....................................................................203
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................205
A.2 Absolute Maximum Ratings ..........................................................................................................205
A.3 Thermal Characteristics .................................................................................................................206
A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................207
A.5 DC Characteristics .........................................................................................................................207
A.6 Supply Current Characteristics ......................................................................................................211
A.7 Analog Comparator (ACMP) Electricals ......................................................................................211
A.8 Oscillator Characteristics ..............................................................................................................212
A.9 AC Characteristics .........................................................................................................................212
A.9.1 Control Timing ...............................................................................................................212
A.9.2 Timer/PWM (TPM) Module Timing .............................................................................213
A.9.3 SPI Timing ......................................................................................................................214
A.10 FLASH Specifications ...................................................................................................................218
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................219
B.2 Mechanical Drawings ....................................................................................................................220
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
14 Freescale Semiconductor
Chapter 1
Introduction
1.1 Overview
The MC9S08RC/RD/RE/RG are members of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). All MCUs in this family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
1.2 Features
Features of the MC9S08RC/RD/RE/RG Family of devices are listed here. Please see Table 1-1 for the
features that are available on the different family members.
HCS08 CPU Object code fully upward-compatible with M68HC05 and M68HC08 Families
(Central Processor Unit) HC08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
On-Chip Memory Power-saving modes: wait plus three stops
Oscillator (OSC) On-chip in-circuit programmable FLASH memory with block protection and security
Analog Comparator option
(ACMP1) On-chip random-access memory (RAM)
Serial Communications Low power oscillator capable of operating from crystal or resonator from 1 to 16 MHz
Interface Module (SCI1) 8 MHz internal bus frequency
Serial Peripheral On-chip analog comparator with internal reference (ACMP1)
Interface Module (SPI1) Full rail-to-rail supply operation
Option to compare to a fixed internal bandgap reference voltage
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable 8-bit or 9-bit character length
Programmable baud rates (13-bit modulo divider)
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 15
Introduction
Timer/Pulse-Width 2-channel, 16-bit timer/pulse-width modulator (TPM1) module that can operate as a
Modulator (TPM1) free-running counter, a modulo counter, or an up-/down-counter when the TPM is
configured for center-aligned PWM
Keyboard Interrupt Ports
(KBI1, KBI2) Selectable input capture, output compare, and edge-aligned or center-aligned PWM
capability on each channel
Carrier Modulator Timer
(CMT) Providing 12 keyboard interrupts
Eight with falling-edge/low-level plus four with selectable polarity
Development Support KBI1 inputs can be configured for edge-only sensitivity or edge-and-level sensitivity
Port Pins Dedicated infrared output (IRO) pin
Drives IRO pin for remote control communications
Package Options Can be disconnected from IRO pin and used as output compare timer
IRO output pin has high-current sink capability
System Protection
Background debugging system (see also the Development Support chapter)
Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus
two more breakpoints in on-chip debug module)
Debug module containing two comparators and nine trigger modes. Eight deep FIFO
for storing change-of-flow addresses and event-only data. Debug module supports
both tag and force breakpoints.
Eight high-current pins (limited by maximum package dissipation)
Software selectable pullups on ports when used as input. Selection is on an individual
port bit basis. During output mode, pullups are disengaged.
39 general-purpose input/output (I/O) pins, depending on package selection
28-pin plastic dual in-line package (PDIP)
28-pin small outline integrated circuit (SOIC)
32-pin low-profile quad flat package (LQFP)
44-pin low-profile quad flat package (LQFP)
48-pin quad flat package (QFN)
Optional computer operating properly (COP) reset
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Illegal address detection with reset (some devices don't have illegal addresses)
1.2.1 Devices in the MC9S08RD/RE/RG Series
Table 1-1 lists the devices available in the MC9S08RD/RE/RG series and summarizes the differences in
functions and configuration among them.
Table 1-1. Devices in the MC9S08RD/RE/RG Series
Device FLASH RAM ACMP(1) SCI SPI
9S08RG32/60 32K/60K 2K/2K Yes Yes Yes
9S08RE8/16/32/60
9S08RD8/16/32/60 8/16K/32K/60K 1K/1K/2K/2K Yes Yes No
8/16K/32K/60K 1K/1K/2K/2K No Yes No
1. Available only in 32-, 44-, and 48-pin LQFP packages.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
16 Freescale Semiconductor
Introduction
1.3 MCU Block Diagram
This block diagram shows the structure of the MC9S08RC/RD/RE/RG MCUs
HCS08 CORE INTERNAL BUS
BDC CPU DEBUG PORT A 7 NOTES1, 2, 6
MODULE (DBG) PTA7/KBI1P7
PTA1/KBI1P1
PTA0/KBI1P0
HCS08 SYSTEM CONTROL 8-BIT KEYBOARD PORT B PTB7/TPM1CH1 NOTES 1, 5
INTERRUPT MODULE (KBI1)
RESETS AND INTERRUPTS PTE6
MODES OF OPERATION 4-BIT KEYBOARD PTB5
POWER MANAGEMENT INTERRUPT MODULE (KBI2) PTB4
PTB3
RTI COP SERIAL COMMUNICATIONS PTB2
INTERFACE MODULE (SCI1) PTB1/RxD1
PTB0/TxD1
ANALOG COMPARATOR
IRQ LVD MODULE (ACMP1)
USER FLASH PORT C PTC7/SS1 NOTE 1
PTC6/SPSCK1
(RC/RD/RE/RG60 = 63,364 BYTES) PTC5/MISO1
(RC/RD/RE/RG32 = 32,768 BYTES) PTC4/MOSI1
PTC3/KBI2P3
(RC/RD/RE16 = 16,384 BYTES) PTC2/KBI2P2
(RC/RD/RE8 = 8192 BYTES) PTC1/KBI2P1
PTC0/KBI2P0
USER RAM 2-CHANNEL TIMER/PWM PORT D PTD6/TPM1CH0 NOTES
MODULE (TPM1) PTD5/ACMP1+ 1, 3, 4
(RC/RD/RE/RG32/60 = 2048 BYTES) PTD4/ACMP1
(RC/RD/RE8/16 = 1024 BYTES) SERIAL PERIPHERAL PTD3
INTERFACE MODULE (SPI1) PTD2/IRQ
EXTAL LOW-POWER OSCILLATOR PTD1/RESET
XTAL PTD0/BKGD/MS
VDD PORT E 8
PTE7PTE0 NOTE 1
VOLTAGE
IRO NOTE 5
VSS REGULATOR CARRIER MODULATOR
TIMER MODULE (CMT)
NOTES:
1. Port pins are software configurable with pullup device if input port
2. PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Also, PTA0 does not pullup to
VDD when internal pullup is enabled.
3. IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1)
4. The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1)
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and
rising edge is selected (KBEDGn = 1).
Figure 1-1. MC9S08RC/RD/RE/RG Block Diagram
Table 1-2 lists the functional versions of the on-chip modules.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 17
Introduction
Table 1-2. Block Versions Version
Module 1
Analog Comparator (ACMP) 1
Carrier Modulator Transmitter (CMT) 1
Keyboard Interrupt (KBI) 1
Serial Communications Interface (SCI) 3
Serial Peripheral Interface (SPI) 1
Timer Pulse-Width Modulator (TPM) 2
Central Processing Unit (CPU) 1
Debug Module (DBG) 1
FLASH 2
System Control
1.4 System Clock Distribution
RTI SYSTEM SCI SPI
RTICLKS CONTROL TPM CMT
OSC LOGIC
RTI
OSCOUT* 2 BUSCLK
OSC
CPU BDC ACMP RAM FLASH
* OSCOUT is the alternate BDC clock source for the MC9S08RC/RD/RE/RG. FLASH has frequency
requirements for program
and erase operation.
See Appendix A.
Figure 1-2. System Clock Distribution Diagram
Table 1-2 shows a simplified clock connection diagram for the MCU. The CPU operates at the input
frequency of the oscillator. The bus clock frequency is half of the oscillator frequency and is used by all of
the internal circuits with the exception of the CPU and RTI. The RTI can use either the oscillator input or
the internal RTI oscillator as its clock source.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
18 Freescale Semiconductor
Chapter 2
Pins and Connections
2.1 Introduction
This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals.
2.2 Device Pin Assignment
PTB0/TxD1 1 44 PTA7/KBI1P7 33 PTA0/KBI1P0
43 PTA6/KBI1P6
42 PTA5/KBI1P5
41 PTA4/KBI1P4
40 PTE7
39 PTE6
38 PTE5
37 PTE4
36 PTA3/KBI1P3
35 PTA2/KBI1P2
34 PTA1/KBI1P1
PTB1/RxD1 2 32 PTD6/TPM1CH0
PTB2 3 31 PTD5/ACMP1+
PTB3 4 30 PTD4/ACMP1
PTB4 5 29 EXTAL
VDD 6 28 XTAL
VSS 7 27 PTD3
IRO 8 26 PTD2/IRQ
PTB5 9 25 PTD1/RESET
PTB6 10 24 PTD0/BKGD/MS
PTB7/TPM1CH1 11 PTC0/KBI2P0 12 23 PTC7/SS1
PTC1/KBI2P1 13
PTC2/KBI2P2 14
PTC3/KBI2P3 15
PTE0 16
PTE1 17
PTE2 18
PTE3 19
PTC4/MOSI1 20
PTC5/MISO1 21
PTC6/SPSCK1 22
Figure 2-1. MC9S08RC/RD/RE/RG in 44-Pin LQFP Package
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 19
Pins and Connections
PTB0/TxD1 1 32 PTA7/KBI1P7 24 PTD6/TPM1CH0
31 PTA6/KBI1P6 23 PTD5/ACMP1+
30 PTA5/KBI1P5 22 PTD4/ACMP1
29 PTA4/KBI1P4 21 EXTAL
28 PTA3/KBI1P3 20 XTAL
27 PTA2/KBI1P2 19 PTD2/IRQ
26 PTA1/KBI1P1 18 PTD1/RESET
25 PTA0/KBI1P017 PTD0/BKGD/MS
PTB1/RxD1 2
PTB2 3
VDD 4
VSS 5
IRO 6
PTB6 7
PTB7/TPM1CH1 8 PTC0/KBI2P0 9
PTC1/KBI2P1 10
PTC2/KBI2P2 11
PTC3/KBI2P3 12
PTC4/MISO1 13
PTC5/MISO1 14
PTC6/SPSCK1 15
PTC7/SS1 16
Figure 2-2. MC9S08RC/RD/RE/RG in 32-Pin LQFP Package
PTA5/KBI1P5 1 28 PTA4/KBI1P4
PTA6/KBI1P6 2 27 PTA3/KBI1P3
PTA7/KBI1P7 3 26 PTA2/KBI1P2
PTB0/TxD1 4 25 PTA1/KBI1P1
PTB1/RxD1 5 24 PTA0/KBI1P0
PTB2 6 23 PTD6/TPM1CH0
VDD 7 22 EXTAL
VSS 8 21 XTAL
IRO 9 20 PTD1/RESET
PTB7/TPM1CH1 10 19 PTD0/BKGD/MS
PTC0/KBI2P0 11 18 PTC7/SS1
PTC1/KBI2P1 12 17 PTC6/SPSCK1
PTC2/KBI2P2 13 16 PTC5/MISO1
PTC3/KBI2P3 14 15 PTC4/MOSI1
Figure 2-3. MC9S08RC/RD/RE/RG in 28-Pin SOIC Package and 28-Pin PDIP Package
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
20 Freescale Semiconductor
48 NC Pins and Connections
47 PTA7/KBI1P7
46 PTA6/KBI1P6 36 NC
45 PTA5/KBI1P5 35 PTA0/KBI1P0
44 PTA4/KBI1P4 34 PTD6/TPM1CH0
43 PTE7 33 PTD5/ACMP1+
42 PTE6 32 PTD4/ACMP1
41 PTE5 31 EXTAL
40 PTE4 30 XTAL
39 PTA3/KBI1P3 29 PTD3
38 PTA2/KBI1P2 28 PTD2/IRQ
37 PTA1/KBI1P1 27 PTD1/RESET
26 PTD0/BKGD/MS
PTB0/TxD1 1 25 PTC7/SS1
PTB1/RxD1 2
PTB2 3
PTB3 4
PTB4 5
VDD 6
VSS 7
IRQ 8
PTB5 9
PTB6 10
PTB7/TPM1CH1 11
NC 12
PTC0/KBI2P0 13
PTC1/KBI2P1 14
PTC2/KBI2P2 15
PTC3/KBI2P3 16
PTE0 17
PTE1 18
PTE2 19
PTE3 20
PTC4/MOSI1 21
PTC5/MISO1 22
PTC6/SPSCK1 23
NC 24
Figure 2-4. MC9S08RC/RD/RE/RG in 48-Pin QFN Package
2.3 Recommended System Connections
Figure 2-5 shows pin connections that are common to almost all MC9S08RC/RD/RE/RG application
systems. A more detailed discussion of system connections follows.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 21
Pins and Connections
SYSTEM VDD CBY MC9S08RC/RD/RE/RG PTA0/KBI1P0
POWER 0.1 F PTA1/KBI1P1
CBLK + VDD PTA2/KBI1P2
+ 10 F PORT PTA3/KBI1P3
A PTA4/KBI1P4
3V PTA5/KBI1P5
VSS PTA6/KBI1P6
PTA7/KBI1P7
RF
C2 X1 C1 XTAL PTB0/TxD1
EXTAL PTB1/RxD1
PORT PTB2
BACKGROUND HEADER B PTB3
1 PTB4
BKGD/MS PTB5 I/O AND
VDD NOTE 1 PTB6 PERIPHERAL
PTB7/TPM1CH1
PTC0/KBI2P0 INTERFACE TO
PTC1/KBI2P1 APPLICATION
PTC2/KBI2P2
PTC3/KBI2P3 SYSTEM
PTC4/MOSI1
RESET PORT PTC5/MISO1
NOTE 2 C PTC6/SPSCK1
PTC7/SS1
OPTIONAL
MANUAL
RESET
PORT PTD0/BKGD/MS
D PTD1/RESET
PTD2/IRQ
PTD3
PTD4/ACMP1
PTD5/ACMP1+
PTD6/TPM1CH0
NOTES: PORT IRO
1. BKGD/MS is the E
same pin as PTD0. PTE0
2. RESET is the Figure 2-5. Basic System Connections PTE1
same pin as PTD1. PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
22 Freescale Semiconductor
Pins and Connections
2.3.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there
should be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storage
for the overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins as
practical to suppress high-frequency noise.
2.3.2 Oscillator
The oscillator in the MC9S08RC/RD/RE/RG is a traditional Pierce oscillator that can accommodate a
crystal or ceramic resonator in the range of 1 MHz to 16 MHz.
Refer to Figure 2-5 for the following discussion. RF should be a low-inductance resistor such as a carbon
composition resistor. Wire-wound resistors, and some metal film resistors, have too much inductance. C1
and C2 normally should be high-quality ceramic capacitors specifically designed for high-frequency
applications.
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 M. Higher values are sensitive to humidity and lower
values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance that
is the series combination of C1 and C2, which are usually the same size. As a first-order approximation,
use 5 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).
2.3.3 PTD1/RESET
The external pin reset function is shared with an output-only port function on the PTD1/RESET pin. The
reset function is enabled when RSTPE in SOPT is set. RSTPE is set following any reset of the MCU and
must be cleared in order to use this pin as an output-only port.
Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin
is driven low for about 34 cycles of fSelf_reset, released, and sampled again about 38 cycles of fSelf_reset
later. If reset was caused by an internal source such as low-voltage reset or watchdog timeout, the circuitry
expects the reset pin sample to return a logic 1. If the pin is still low at this sample point, the reset is
assumed to be from an external source. The reset circuitry decodes the cause of reset and records it by
setting a corresponding bit in the system control reset status register (SRS).
Never connect any significant capacitance to the reset pin because that would interfere with the circuit and
sequence that detects the source of reset. If an external capacitance prevents the reset pin from rising to a
valid logic 1 before the reset sample point, all resets will appear to be external resets.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 23
Pins and Connections
2.3.4 Background/Mode Select (PTD0/BKGD/MS)
The background/mode select function is shared with an output-only port function on the PTD0/BKDG/MS
pin. While in reset, the pin functions as a mode select pin. Immediately after reset rises, the pin functions
as the background pin and can be used for background debug communication. While functioning as a
background/mode select pin, this pin has an internal pullup device enabled. To use as an output-only port,
BKGDPE in SOPT must be cleared.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset, which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU's BDC clock per bit time. The target MCU's BDC
clock could be as fast as the bus clock rate, so there should never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.3.5 IRO Pin Description
The IRO pin is the output of the CMT. See the Carrier Modulator Timer (CMT) Module Chapter for a
detailed description of this pin function.
2.3.6 General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and serial I/O systems. (Not all pins are available in all packages. See Table 2-2.) Immediately after reset,
all 37 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices
disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unused pins to outputs so the pins do not
float.
For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, "Parallel
Input/Output." For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate chapter from Table 2-1.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
24 Freescale Semiconductor
Pins and Connections
Table 2-1. Pin Sharing References
Port Pins Alternate Reference(1)
Function
PTA7PTA0 KBI1P7KBI1P0 Chapter 9, "Keyboard Interrupt (S08KBIV1)"
PTB7 TPM1CH1 Chapter 10, "Timer/PWM Module (S08TPMV1)"
PTB6PTB2 -- Chapter 6, "Parallel Input/Output"
PTB1 RxD1 Chapter 11, "Serial Communications Interface (S08SCIV1)"
PTB0 TxD1
PTC7 SS1 Chapter 13, "Serial Peripheral Interface (S08SPIV3)"
PTC6 SPSCK1
PTC5 MISO1
PTC4 MOSI1
PTC3PTC0 KBI2P3KBI2P0 Chapter 9, "Keyboard Interrupt (S08KBIV1)"
PTD6 TPM1CH0 Chapter 10, "Timer/PWM Module (S08TPMV1)"
PTD5 ACMP1+ Chapter 14, "Analog Comparator (S08ACMPV1)"
PTD4 ACMP1
PTD2 IRQ Chapter 5, "Resets, Interrupts, and System Configuration"
PTD1 RESET
PTD0 BKGD/MS
PTE7PTE0 -- Chapter 6, "Parallel Input/Output"
1. See this chapter for information about modules that share these pins.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin's output buffer. See the Chapter 6, "Parallel Input/Output," for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when PTD2 is
configured as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a
pulldown device rather than a pullup device.
2.3.7 Signal Properties Summary
Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the
common pin interfaces are hardwired to internal circuits.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 25
Pins and Connections
Table 2-2. Signal Properties
Pin Dir(1) High Current Pullup(2) Comments(3)
Name Pin
VDD -- --
VSS
XTAL -- --
O -- -- Crystal oscillator output
EXTAL I -- -- Crystal oscillator input
IRO O Y -- Infrared output
PTA0/KBI1P0 I N SWC PTA0 does not have a clamp diode to VDD. PTA0 should not be
SWC driven above VDD.
PTA1/KBI1P1 I/O N
PTA2/KBI1P2 I/O N SWC
PTA3/KBI1P3 I/O N SWC
PTA4/KBI1P4 I/O N SWC
PTA5/KBI1P5 I/O N SWC
PTA6/KBI1P6 I/O N SWC
PTA7/KBI1P7 I/O N SWC
PTB0/TxD1 I/O Y SWC
PTB1/RxD1 I/O Y SWC
PTB2 I/O Y SWC
PTB3 I/O Y SWC Available only in 44- and 48-pin packages
PTB4 I/O Y SWC Available only in 44- and 48-pin packages
PTB5 I/O Y SWC Available only in 44- and 48-pin packages
PTB6 I/O Y SWC Available only in 32-, 44-, and 48-pin packagess
PTB7/TPM1CH1 I/O Y SWC
PTC0/KBI2P0 I/O N SWC
PTC1/KBI2P1 I/O N SWC
PTC2/KBI2P2 I/O N SWC
PTC3/KBI2P3 I/O N SWC
PTC4/MOSI1 I/O N SWC
PTC5/MISO1 I/O N SWC
PTC6/SPSCK1 I/O N SWC
PTC7/SS1 I/O N SWC
PTD0/BKGD/MS I/O N SWC(4) Output-only when configured as PTD0 pin. Pullup enabled.
PTD1/RESET I/O N SWC(3) Output-only when configured as PTD1 pin.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
26 Freescale Semiconductor
Pins and Connections
Table 2-2. Signal Properties (continued)
Pin Dir(1) High Current Pullup(2) Comments(3)
Name Pin
PTD2/IRQ I/O N SWC(5) Available only in 32-, 44-, and 48-pin packagess
PTD3 I/O N SWC Available only in 44- and 48-pin packages
PTD4/ACMP1 I/O N SWC Available only in 32-, 44-, and 48-pin packagess
PTD5/ACMP1+ I/O N SWC Available only in 32-, 44-, and 48-pin packagess
PTD6/TPM1CH0 I/O N SWC
PTE0 I/O N SWC Available only in 44- and 48-pin packages
PTE1 I/O N SWC Available only in 44- and 48-pin packages
PTE2 I/O N SWC Available only in 44- and 48-pin packages
PTE3 I/O N SWC Available only in 44- and 48-pin packages
PTE4 I/O N SWC Available only in 44- and 48-pin packages
PTE5 I/O N SWC Available only in 44- and 48-pin packages
PTE6 I/O N SWC Available only in 44- and 48-pin packages
PTE7 I/O N SWC Available only in 44- and 48-pin packages
1. Unless otherwise indicated, all digital inputs have input hysteresis.
2. SWC is software-controlled pullup resistor, the register is associated with the respective port.
3. Not all general-purpose I/O pins are available on all packages. To avoid extra current drain from floating input pins, the user's
reset initialization routine in the application program should either enable on-chip pullup devices or change the direction of
unconnected pins to outputs so the pins do not float.
4. When these pins are configured as RESET or BKGD/MS pullup device is enabled.
5. When configured for the IRQ function, this pin will have a pullup device enabled when the IRQ is set for falling edge detection
and a pulldown device enabled when the IRQ is set for rising edge detection.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 27
Pins and Connections
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
28 Freescale Semiconductor
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08RC/RD/RE/RG are described in this section. Entry into each mode,
exit from each mode, and functionality while in each of the modes are described.
3.2 Features
Active background mode for code development
Wait mode:
-- CPU shuts down to conserve power
-- System clocks running
-- Full voltage regulation maintained
Stop modes:
-- System clocks stopped; voltage regulator in standby
-- Stop1 -- Full power down of internal circuits for maximum power savings
-- Stop2 -- Partial power down of internal circuits, RAM remains operational
-- Stop3 -- All internal circuits powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9S08RC/RD/RE/RG. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address fetched from memory at $FFFE:$FFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
When the BKGD/MS pin is low at the rising edge of reset
When a BACKGROUND command is received through the BKGD pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 29
Modes of Operation
After active background mode is entered, the CPU is held in a suspended state waiting for serial
background commands rather than executing instructions from the user's application program.
Background commands are of two types:
Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
-- Memory access commands
-- Memory-access-with-status commands
-- BDC register access commands
-- BACKGROUND command
Active background commands, which can only be executed while the MCU is in active background
mode, include commands to:
-- Read or write CPU registers
-- Trace one user program instruction at a time
-- Leave active background mode to return to the user's application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the
MC9S08RC/RD/RE/RG is shipped from the Freescale Semiconductor factory, the FLASH program
memory is usually erased so there is no program that could be executed in run mode until the FLASH
memory is initially programmed. The active background mode can also be used to erase and reprogram
the FLASH memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
Only the BACKGROUND command and memory-access-with-status commands are available when the
MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they
report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can
be used to wake the MCU from wait mode and enter active background mode.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
30 Freescale Semiconductor
Modes of Operation
3.6 Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the
system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set
when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
Table 3-1. Stop Mode Behavior
Mode PDC PPDC CPU, Digital RAM OSC ACMP Regulator I/O Pins RTI
Peripherals,
Stop1 1 0 Off Off Standby Standby Reset Off
Stop2 1 1 FLASH Standby Off Standby Standby Optionally on
Off States
Off Standby Standby held Optionally on
Off States
held
Stop3 0 Don't Standby Standby
care
3.6.1 Stop1 Mode
Stop1 mode provides the lowest possible standby power consumption by causing the internal circuitry of
the MCU to be powered down. To enter stop1, the user must execute a STOP instruction with the PDC bit
in SPMSC2 set and the PPDC bit clear. Stop1 can be entered only if the LVD reset is disabled
(LVDRE = 0).
When the MCU is in stop1 mode, all internal circuits that are powered from the voltage regulator are turned
off. The voltage regulator is in a low-power standby state, as are the OSC and ACMP.
Exit from stop1 is done by asserting any of the wakeup pins on the MCU: RESET, IRQ, or KBI1, which
have been enabled. IRQ and KBI pins are always active-low when used as wakeup pins in stop1 regardless
of how they were configured before entering stop1.
Upon wakeup from stop1 mode, the MCU will start up as from a power-on reset (POR). The CPU will take
the reset vector.
3.6.2 Stop2 Mode
Stop2 mode provides very low standby power consumption and maintains the contents of RAM and the
current state of all of the I/O pins. To select entry into stop2 upon execution of a STOP instruction, the user
must execute a STOP instruction with the PPDC and PDC bits in SPMSC2 set. Stop2 can be entered only
if LVDRE = 0.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers that they want to restore after exit of stop2, to locations in RAM. Upon exit from
stop2, these values can be restored by user software.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ACMP. Upon entry
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 31
Modes of Operation
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting any of the wakeup pins: RESET, IRQ, or KBI1 that have been enabled,
or through the real-time interrupt. IRQ and KBI1 pins are always active-low when used as wakeup pins in
stop2 regardless of how they were configured before entering stop2. (KBI2 will not wake the MCU from
stop2.)
Upon wakeup from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a 1 is written
to PPDACK in SPMSC2.
For pins that were configured as general-purpose I/O, the user must copy the contents of the I/O port
registers, which have been saved in RAM, back to the port registers before writing to the PPDACK bit. If
the port registers are not restored from RAM before writing to PPDACK, then the register bits will be in
their reset states when the I/O pin latches are opened and the I/O pins will switch to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3 Stop3 Mode
Upon entering stop3 mode, all of the clocks in the MCU, including the oscillator itself, are halted. The
OSC is turned off, the ACMP is disabled, and the voltage regulator is put in standby. The states of all of
the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not
latched at the pin as in stop2. Instead they are maintained by virtue of the states of the internal logic driving
the pins being maintained.
Exit from stop3 is done by asserting RESET, any asynchronous interrupt pin that has been enabled, or
through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI1 and KBI2 pins.
If stop3 is exited by means of the RESET pin, then the MCU will be reset and operation will resume after
taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in
the MCU taking the appropriate interrupt vector.
A separate self-clocked source (1 kHz) for the real-time interrupt allows a wakeup from stop2 or stop3
mode with no external components. When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function
and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in
that case the real-time interrupt cannot wake the MCU from stop.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
32 Freescale Semiconductor
Modes of Operation
3.6.4 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in the Development Support chapter of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when
the MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation. The MCU
cannot enter either stop1 mode or stop2 mode if ENBDM is set.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the active
background mode is enabled.
Table 3-2. BDM Enabled Stop Mode Behavior
Mode PDC PPDC CPU, Digital RAM OSC ACMP Regulator I/O Pins RTI
Stop3 Peripherals, Standby On
Don't Don't Standby On States Optionally on
care care FLASH held
Standby
3.6.5 LVD Reset Enabled
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD reset is enabled in stop by setting the LVDRE bit in SPMSC1 when the CPU
executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user
attempts to enter either stop1 or stop2 with the LVD reset enabled (LVDRE = 1) the MCU will instead
enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-3. LVD Enabled Stop Mode Behavior
Mode PDC PPDC CPU, Digital RAM OSC ACMP Regulator I/O Pins RTI
Stop3 Peripherals, Standby On
Don't Don't Standby On States Optionally on
care care FLASH held
Standby
3.6.6 On-Chip Peripheral Modules in Stop Mode
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to
the peripheral systems are halted to reduce power consumption.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 33
Modes of Operation
I/O Pins
All I/O pin states remain unchanged when the MCU enters stop3 mode.
If the MCU is configured to go into stop2 mode, all I/O pin states are latched before entering stop.
Pin states remain latched until the PPDACK bit is written.
If the MCU is configured to go into stop1 mode, all I/O pins are forced to their default reset state
upon entry into stop.
Memory
All RAM and register contents are preserved while the MCU is in stop3 mode.
All registers will be reset upon wakeup from stop2, but the contents of RAM are preserved. The
user may save any memory-mapped register data into RAM before entering stop2 and restore the
data upon exit from stop2.
All registers will be reset upon wakeup from stop1 and the contents of RAM are not preserved. The
MCU must be initialized as upon reset. The contents of the FLASH memory are non-volatile and
are preserved in any of the stop modes.
OSC -- In any of the stop modes, the OSC stops running.
TPM -- When the MCU enters stop mode, the clock to the TPM module stops. The modules halt
operation. If the MCU is configured to go into stop2 or stop1 mode, the TPM module will be reset upon
wakeup from stop and must be reinitialized.
ACMP -- When the MCU enters any stop mode, the ACMP will enter a low-power standby state. No
compare operation will occur while in stop. If the MCU is configured to go into stop2 or stop1 mode, the
ACMP will be reset upon wakeup from stop and must be reinitialized.
KBI -- During stop3, the KBI pins that are enabled continue to function as interrupt sources. During stop1
or stop2, enabled KBI1 pins function as wakeup inputs. When functioning as a wakeup, a KBI pin is
always active low regardless of how it was configured before entering stop1 or stop2.
SCI -- When the MCU enters stop mode, the clock to the SCI module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SCI module will be reset upon wakeup from
stop and must be reinitialized.
SPI -- When the MCU enters stop mode, the clock to the SPI module stops. The module halts operation.
If the MCU is configured to go into stop2 or stop1 mode, the SPI module will be reset upon wakeup from
stop and must be reinitialized.
CMT -- When the MCU enters stop mode, the clock to the CMT module stops. The module halts
operation. If the MCU is configured to go into stop2 or stop1 mode, the CMT module will be reset upon
wakeup from stop and must be reinitialized.
Voltage Regulator -- The voltage regulator enters a low-power standby state when the MCU enters any
of the stop modes unless the LVD reset function is enabled or BDM is enabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
34 Freescale Semiconductor
Chapter 4
Memory
4.1 MC9S08RC/RD/RE/RG Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08RC/RD/RE/RG series of MCUs consists of
RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers. The
registers are divided into three groups:
Direct-page registers ($0000 through $0045 for 32K and 60K parts, and $0000 through $003F for
16K and 8K parts)
High-page registers ($1800 through $182B)
Nonvolatile registers ($FFB0 through $FFBF)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 35
Memory
$0000 $0000 $0000 $0000
DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS $0045 DIRECT PAGE REGISTERS $003F DIRECT PAGE REGISTERS $003F
$0045
$0046 RAM RAM $0046 RAM 1024 BYTES(1) $0040 RAM 1024 BYTES(1) $0040
$043F $043F
2048 BYTES 2048 BYTES
$0845 FLASH UNIMPLEMENTED $0845 $0440 $0440
$0846 $0846
4026 BYTES 4026 BYTES UNIMPLEMENTED UNIMPLEMENTED
5056 BYTES 5056 BYTES
$17FF HIGH PAGE REGISTERS $17FF HIGH PAGE REGISTERS $17FF HIGH PAGE REGISTERS $17FF
$1800 $1800 $1800
HIGH PAGE REGISTERS $1800
$182B $182B $182B $182B
$182C $182C $182C $182C
UNIMPLEMENTED
26580 BYTES
$8000 UNIMPLEMENTED
42964 BYTES
FLASH UNIMPLEMENTED
59348 BYTES 51156 BYTES
FLASH $BFFF
32768 BYTES $C000
FLASH $DFFF
16384 BYTES $E000
$FFFF $FFFF FLASH $FFFF
MC9S08RC/RD/RE/RG60 8192 BYTES
MC9S08RC/RD/RE/RG32 MC9S08RC/RD/RE16
MC9S08RC/RD/RE8
Figure 4-1. MC9S08RC/RD/RE/RG Memory Map
4.1.1 Reset and Interrupt Vector Assignments
Figure 4-2 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale-provided equate file for the MC9S08RC/RD/RE/RG. For more details
about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to the Chapter 5, "Resets,
Interrupts, and System Configuration."
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
36 Freescale Semiconductor
Memory
Figure 4-2. Reset and Interrupt Vectors
Vector Address Vector Vector Name
Number (High/Low)
16 $FFC0:FFC1 Unused Vector Space Vspi1
through (available for user program) Vrti
$FFDE:FFDF Vkeyboard2
31 $FFE0:FFE1 SPI(1) Vkeyboard1
$FFE2:FFE3 RTI Vacmp1
15 $FFE4:FFE5 KBI2 Vcmt
14 $FFE6:FFE7 KBI1 Vsci1tx
13 $FFE8:FFE9 Vsci1rx
12 $FFEA:FFEB ACMP(2) Vsci1err
11 $FFEC:FFED CMT Vtpm1ovf
10 $FFEE:FFEF Vtpm1ch1
9 $FFF0:FFF1 SCI Transmit(3) Vtpm1ch0
8 $FFF2:FFF3 SCI Receive(3) Virq
7 $FFF4:FFF5 Vlvd
6 $FFF6:FFF7 SCI Error(3) Vswi
5 $FFF8:FFF9 TPM Overflow Vreset
4 $FFFA:FFFB TPM Channel 1
3 $FFFC:FFFD TPM Channel 0
2 $FFFE:FFFF
1 IRQ
0 Low Voltage Detect
SWI
Reset
1. The SPI module is not included on the MC9S08RC/RD/RE devices. This vector location is unused for those devices.
2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This vector location is unused for
those devices.
3. The SCI module is not included on the MC9S08RC devices. This vector location is unused for those devices.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 37
Memory
4.2 Register Addresses and Bit Assignments
The registers in the MC9S08RC/RD/RE/RG are divided into these three groups:
Direct-page registers are located within the first 256 locations in the memory map, so they are
accessible with efficient direct addressing mode instructions.
High-page registers are used much less often, so they are located above $1800 in the memory map.
This leaves more room in the direct page for more frequently used registers and variables.
The nonvolatile register area consists of a block of 16 locations in FLASH memory at
$FFB0$FFBF.
Nonvolatile register locations include:
-- Three values that are loaded into working registers at reset
-- An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-1 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-1 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-2 and Table 4-3, the whole address in column one is shown in bold. In Table 4-1,
Table 4-2, and Table 4-3, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
38 Freescale Semiconductor
Memory
Table 4-1. Direct-Page Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
$0001 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
$0002 Reserved
$0003 PTADD -- -- -- -- -- -- -- --
$0004 PTBD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
$0005 PTBPE PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
$0006 Reserved PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
$0007 PTBDD
$0008 PTCD -- -- -- -- -- -- -- --
$0009 PTCPE PTBDD3 PTBDD2 PTBDD1 PTBDD0
$000A Reserved PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTCD3 PTCD2 PTCD1 PTCD0
$000B PTCDD PTCD7 PTCD6 PTCD5 PTCD4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
$000C PTDD PTCPE7 PTCPE6 PTCPE5 PTCPE4
$000D PTDPE -- -- -- --
$000E Reserved -- -- -- -- PTCDD3 PTCDD2 PTCDD1 PTCDD0
$000F PTDDD PTCDD7 PTCDD6 PTCDD5 PTCDD4 PTDD3 PTDD2 PTDD1 PTDD0
$0010 PTED PTDD6 PTDD5 PTDD4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
$0011 PTEPE 0 PTDPE6 PTDPE5 PTDPE4
$0012 Reserved 0 -- -- -- --
$0013 PTEDD -- -- -- -- PTDDD3 PTDDD2 PTDDD1 PTDDD0
$0014 KBI1SC 0 PTDDD6 PTDDD5 PTDDD4 PTED3 PTED2 PTED1 PTED0
$0015 KBI1PE PTEPE3 PTEPE2 PTEPE1 PTEPE0
$0016 KBI2SC PTED7 PTED6 PTED5 PTED4
$0017 KBI2PE PTEPE7 PTEPE6 PTEPE5 PTEPE4 -- -- -- --
$0018 SCI1BDH(1) PTEDD3 PTEDD2 PTEDD1 PTEDD0
$0019 SCI1BDL(1) -- -- -- -- KBACK KBIMOD
$001A SCI1C1(1) PTEDD7 PTEDD6 PTEDD5 PTEDD4 KBF KBIPE2 KBIE KBIPE0
$001B SCI1C2(1) KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBIPE3 KBACK KBIPE1 KBIMOD
$001C SCI1S1(1) KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE2 KBIPE0
$001D SCI1S2(1) KBF SBR10 KBIE
$001E SCI1C3(1) 0 0 0 0 KBIPE3 KBIPE1 SBR8
$001F SCI1D(1) 0 0 0 0 SBR11 SBR2 SBR9 SBR0
$0020 CMTCGH1 0 0 0 SBR12 SBR3 ILT SBR1
$0021 CMTCGL1 WAKE RE PT
$0022 CMTCGH2 SBR7 SBR6 SBR5 SBR4 NF PE SBK
$0023 CMTCGL2 LOOPS M TE 0 RWU PF
$0024 CMTOC SCISWAI RSRC ILIE OR NEIE RAF
$0025 CMTMSC TIE 0 FE PEIE
$0026 CMTCMD1 TDRE TCIE RIE IDLE ORIE R2/T2 0 R0/T0
$0027 CMTCMD2 0 R3/T3 PH2 FEIE PH0
$0028 CMTCMD3 0 TC RDRF 0 PH3 PL2 R1/T1 PL0
$0029 CMTCMD4 R8 PL3 SH2 PH1 SH0
R7/T7 0 0 R4/T4 SH3 SL2 PL1 SL0
PH7 PH4 SL3 SH1
PL7 T8 TXDIR PL4 0 0 SL1 0
SH7 SH4 BASE FSK 0 MCGEN
SL7 R6/T6 R5/T5 SL4 MB11 MB10 EOCIE
IROL MB3 MB2 MB9 MB8
EOCF PH6 PH5 0 SB11 SB10 MB1 MB0
MB15 EXSPC SB3 SB2 SB9 SB8
MB7 PL6 PL5 MB12 SB1 SB0
SB15
SB7 SH6 SH5 MB4
SB12
SL6 SL5 SB4
CMTPOL IROPEN
CMTDIV1 CMTDIV0
MB14 MB13
MB6 MB5
SB14 SB13
SB6 SB5
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 39
Memory
Table 4-1. Direct-Page Register Summary (continued)
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$002A IRQSC 0 0 IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
$002B ACMP1SC(2) ACME ACBGS ACF ACIE ACO -- ACMOD1 ACMOD0
$002C Reserved -- --
$002F -- -- -- -- -- -- -- --
$0030 TPM1SC -- -- -- -- PS2 -- --
$0031 TPM1CNTH TOF TOIE CPWMS CLKSB CLKSA 10 PS1 PS0
$0032 TPM1CNTL Bit 15 14 13 12 11 2 9 Bit 8
$0033 TPM1MODH Bit 7 6 5 4 3 10 1 Bit 0
$0034 TPM1MODL Bit 15 14 13 12 11 2 9 Bit 8
$0035 TPM1C0SC Bit 7 6 5 4 3 1 Bit 0
$0036 TPM1C0VH CH0F CH0IE MS0A ELS0B ELS0A 0 0
$0037 TPM1C0VL Bit 15 14 MS0B 12 11 10 9 Bit 8
$0038 TPM1C1SC Bit 7 6 13 4 3 2 1 Bit 0
$0039 TPM1C1VH CH1F CH1IE 5 MS1A ELS1B 0 0
$003A TPM1C1VL Bit 15 14 12 11 ELS1A 9 Bit 8
$003B Reserved Bit 7 6 MS1B 4 3 10 1 Bit 0
$003F -- -- 13 -- -- 2 -- --
$0040 SPI1C1(3) -- -- 5 -- -- -- -- --
$0041 SPI1C2(3) SPIE SPE -- MSTR CPOL -- SSOE LSBFE
$0042 SPI1BR(3) 0 0 -- MODFEN BIDIROE SPISWAI SPC0
$0043 SPI1S(3) 0 SPPR2 SPPR0 0 CPHA SPR1 SPR0
$0044 Reserved SPRF 0 SPTIE MODF 0 0 0 0
$0045 SPI1D(3) -- -- 0 -- -- -- --
Bit 7 6 4 3 SPR2 1 Bit 0
SPPR1 0
SPTEF --
2
--
5
1. The SCI module is not included on the MC9S08RC devices. This is a reserved location for those devices.
2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This is a reserved location for those
devices.
3. The SPI module is not included on the MC9S08RC/RD/RE devices. These are reserved locations on the 32K and 60K versions
of these devices. The address range $0040$004F are RAM locations on the 16K and 8K devices. There are no
MC9S08RG8/16 devices.
High-page registers, shown in Table 4-2, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at $1800.
Table 4-2. High-Page Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
ILAD(1)
$1800 SRS POR PIN COP ILOP 0 LVD 0
$1801 SBDFR 0 0 0 0 0 0 0 BDFR
$1802 SOPT 7 -- 0 0 RSTPE
$1803 Reserved -- COPT STOPE -- -- -- BKGDPE
$1804 -- -- -- -- -- -- -- --
0 -- -- 0 0 0 -- --
$1805 Reserved 0 0 ID11 ID10 0 0
$1806 SDIDH REV3 REV0 ID3 ID2 ID9 ID8
$1807 SDIDL ID7 REV2 REV1 ID4 0 RTIS2 ID1 ID0
$1808 SRTISC RTIF ID6 ID5 RTIE RTIS0
RTIS1
RTIACK RTICLKS
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
40 Freescale Semiconductor
Memory
Table 4-2. High-Page Register Summary (continued)
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$1809 SPMSC1 LVDF LVDACK LVDIE SAFE LVDRE -- -- --
$180A SPMSC2 LVWF LVWACK PPDF PPDACK PDC PPDC
$180B Reserved 0 0
$180F -- -- -- -- -- --
$1810 DBGCAH -- -- -- -- -- -- -- --
$1811 DBGCAL Bit 15 14 11 10 9 Bit 8
$1812 DBGCBH Bit 7 6 -- -- 3 2 1 Bit 0
$1813 DBGCBL Bit 15 14 11 10 9 Bit 8
$1814 DBGFH Bit 7 6 13 12 3 2 1 Bit 0
$1815 DBGFL Bit 15 14 11 10 9 Bit 8
$1816 DBGC Bit 7 6 5 4 3 2 1 Bit 0
$1817 DBGT DBGEN ARM RWA RWAEN RWB RWBEN
$1818 DBGS TRGSEL BEGIN 13 12 TRG3 TRG2 TRG1 TRG0
$1819 Reserved AF BF CNT3 CNT2 CNT1 CNT0
$181F -- -- 5 4 -- -- -- --
$1820 FCDIV -- -- -- -- -- --
$1821 FOPT DIVLD PRDIV8 13 12 DIV3 DIV2 DIV1 DIV0
$1822 Reserved KEYEN FNORED 0 0 SEC01 SEC00
$1823 FCNFG -- -- 5 4 -- -- -- --
$1824 FPROT 0 0 0 0 0 0
$1825 FSTAT FPOPEN FPDIS TAG BRKEN FPS0 0 0 0
$1826 FCMD FCBEF FCCF 0 FBLANK 0 0
$1827 Reserved FCMD7 FCMD6 0 0 FCMD3 FCMD2 FCMD1 FCMD0
$182B -- -- -- -- -- --
-- -- ARMF 0 -- -- -- --
-- --
-- --
DIV5 DIV4
0 0
-- --
KEYACC 0
FPS2 FPS1
FPVIOL FACCERR
FCMD5 FCMD4
-- --
-- --
1. The ILAD bit is only present on 16K and 8K versions of the devices.
Nonvolatile FLASH registers, shown in Table 4-3, are located in the FLASH memory. These registers
include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
Table 4-3. Nonvolatile Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$FFB0 NVBACKKEY 8-Byte Comparison Key
$FFB7
$FFB8 Reserved -- -- -- -- -- -- -- --
$FFBC -- --
-- -- -- -- -- -- 0 0
-- --
$FFBD NVPROT FPOPEN FPDIS FPS2 FPS1 FPS0 0 SEC01 SEC00
$FFBE Reserved
$FFBF NVOPT -- -- -- -- -- --
KEYEN FNORED 0 0 0 0
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 41
Memory
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.3 RAM
The MC9S08RC/RD/RE/RG includes static RAM. The locations in RAM below $0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the
bit-manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently
accessed program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to $00FF. In the
MC9S08RC/RD/RE/RG, it is usually best to reinitialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast
is equated to the highest address of the RAM in the Freescale-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.5, "Security," for a detailed
description of the security feature.
4.4 FLASH
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
42 Freescale Semiconductor
Memory
4.4.1 Features
Features of the FLASH memory include:
FLASH Size
-- MC9S08RC/RD/RE/RG60 -- 63374 bytes (124 pages of 512 bytes each)
-- MC9S08RC/RD/RE/RG32 -- 32768 bytes (64 pages of 512 bytes each)
-- MC9S08RC/RD/RE16 -- 16384 bytes (32 pages of 512 bytes each)
-- MC9S08RC/RD/RE8 -- 8192 bytes (16 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
4.4.2 Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and
200 kHz (see Section 4.6.1, "FLASH Clock Divider Register (FCDIV)"). This register can be written only
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/fFCLK) is used by the command processor to time
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-4 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK = 5 s. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-4. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 s
Byte program (burst) 4 20 s(1)
Page erase 20 ms
Mass erase 4000 100 ms
1. Excluding start/end overhead 20,000
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 43
Memory
4.4.3 Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this
write is latched into the FLASH interface. This write is a required first step in any command
sequence. For erase and blank check commands, the value of the data is not important. For page
erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For
mass erase and blank check commands, the address can be any address in the FLASH memory.
Whole pages of 512 bytes are the smallest block of FLASH that may be erased. In the 60K version,
there are two instances where the size of a block that is accessible to the user is less than 512 bytes:
the first page following RAM, and the first page following the high page registers. These pages are
overlapped by the RAM and high page registers respectively.
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits to a byte which is already
programmed is not allowed without first erasing the page in which the byte
resides or mass erasing the entire FLASH memory. Programming without
first erasing may disturb data stored in the FLASH.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check ($05), byte program ($20), burst program ($25), page erase ($40), and mass erase ($41). The
command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag, which must be cleared before
starting a new command.
A strictly monitored procedure must be adhered to, or the command will not be accepted. This minimizes
the possibility of any unintended changes to the FLASH memory contents. The command complete flag
(FCCF) indicates when a command is complete. The command sequence must be completed by clearing
FCBEF to launch the command. Figure 4-3 is a flowchart for executing all of the commands except for
burst programming. The FCDIV register must be initialized before using any FLASH commands. This
must be done only once following a reset.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
44 Freescale Semiconductor
Memory
START
0
FACCERR ?
CLEAR ERROR
WRITE TO FCDIV(1) (1) Required only once
after reset.
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF (2) Wait at least four cycles before
checking FCBEF or FCCF.
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
FPVIO OR YES
FACCERR ? ERROR EXIT
NO
0
FCCF ?
1
DONE
Figure 4-3. FLASH Program and Erase Flowchart
4.4.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the FLASH
array does not need to be disabled between program operations. Ordinarily, when a program or erase
command is issued, an internal charge pump associated with the FLASH memory must be enabled to
supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When
a burst program command is issued, the charge pump is enabled and remains enabled after completion of
the burst program operation if the following two conditions are met:
The new burst program command has been queued before the current program operation
completes.
The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 45
Memory
program time provided that the conditions above are met. In the case where the next sequential address is
the beginning of a new row, the program time for that byte will be the standard time instead of the burst
time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
START
0
FACCERR ?
1
CLEAR ERROR
WRITE TO FCDIV(1) (1) Required only once
after reset.
FCBEF ? 0
1
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
WRITE 1 TO FCBEF (2) Wait at least four cycles before
checking FCBEF or FCCF.
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
FPVIO OR YES
FACCERR ? ERROR EXIT
YES NO
NEW BURST COMMAND ?
NO
0
FCCF ?
1
DONE
Figure 4-4. FLASH Burst Program Flowchart
4.4.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed:
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
46 Freescale Semiconductor
Memory
Writing to a FLASH address before the internal FLASH clock frequency has been set by writing
to the FCDIV register
Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
Writing a second time to a FLASH address before launching the previous command (There is only
one write to FLASH for every command.)
Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
Writing to any FLASH control register other than FCMD after writing to a FLASH address
Writing any command code other than the five allowed codes ($05, $20, $25, $40, or $41) to
FCMD
Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear
FCBEF and launch the command) after writing the command to FCMD
The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
Writing the byte program, burst program, or page erase command code ($20, $25, or $40) with a
background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
Writing 0 to FCBEF to cancel a partial command
4.4.6 FLASH Block Protection
Block protection prevents program or erase changes for FLASH memory locations in a designated address
range. Mass erase is disabled when any block of FLASH is protected. The MC9S08RC/RD/RE/RG allows
a block of memory at the end of FLASH, and/or the entire FLASH memory to be block protected. A
disable control bit and a 3-bit control field, for each of the blocks, allows the user to independently set the
size of these blocks. A separate control bit allows block protection of the entire FLASH memory array. All
seven of these control bits are located in the FPROT register (see Section 4.6.4, "FLASH Protection
Register (FPROT and NVPROT)").
At reset, the high-page register (FPROT) is loaded with the contents of the NVPROT location that is in the
nonvolatile register block of the FLASH memory. The value in FPROT cannot be changed directly from
application software so a runaway program cannot alter the block protection settings. If the last 512 bytes
of FLASH (which includes the NVPROT register) is protected, the application program cannot alter the
block protection settings (intentionally or unintentionally). The FPROT control bits can be written by
background debug commands to allow a way to erase a protected FLASH memory.
One use for block protection is to block protect an area of FLASH memory for a bootloader program. This
bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because
the bootloader is protected, it remains intact even if MCU power is lost during an erase and reprogram
operation.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 47
Memory
4.4.7 Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. For this reason,
a mechanism for redirecting vector reads is provided. Vector redirection allows users to modify interrupt
vector information without unprotecting bootloader and reset vector space. For redirection to occur, at least
some portion but not all of the FLASH memory must be block protected by programming the NVPROT
register located at address $FFBD. All of the interrupt vectors (memory locations $FFC0$FFFD) are
redirected, while the reset vector ($FFFE:FFFF) is not.
For example, if 512 bytes of FLASH are protected, the protected address region is from $FE00 through
$FFFF. The interrupt vectors ($FFC0$FFFD) are redirected to the locations $FDC0$FDFD. Now, if an
SPI interrupt is taken for instance, the values in the locations $FDE0:FDE1 are used for the vector instead
of the values in the locations $FFE0:FFE1. This allows the user to reprogram the unprotected portion of
the FLASH with new program code including new interrupt vector values while leaving the protected area,
which includes the default vector locations, unchanged.
4.5 Security
The MC9S08RC/RD/RE/RG includes circuitry to prevent unauthorized access to the contents of FLASH
and RAM memory. When security is engaged, FLASH and RAM are considered secure resources.
Direct-page registers, high-page registers, and the background debug controller are considered unsecured
resources. Programs executing within secure memory have normal access to any MCU memory locations
and resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH
into the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location, which can be done at the same time the FLASH memory is programmed. The 1:0 state
disengages security while the other three combinations engage security. Notice the erased state (1:1)
makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to
immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU
to remain unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to
the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to
be compared against the key rather than as the first step in a FLASH program or erase command.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
48 Freescale Semiconductor
Memory
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order starting with the value for NVBACKKEY and ending with
NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security
will be disengaged until the next reset.
The security key can be written only from RAM, so it cannot be entered through background commands
without the cooperation of a secure user program. The FLASH memory cannot be accessed by read
operations while KEYACC is set.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of
FLASH as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by performing these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase FLASH if necessary.
3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next
reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
4.6 FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, three locations in the
nonvolatile register space in FLASH memory that are copied into three corresponding high-page control
registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-2 and
Table 4-3 for the absolute address assignments for all FLASH registers. This section refers to registers and
control bits only by their names. A Freescale-provided equate or header file normally is used to translate
these names into the appropriate absolute addresses.
4.6.1 FLASH Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written
only one time. Before any erase or programming operations are possible, write to this register to set the
frequency of the clock for the nonvolatile memory system within acceptable limits.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 49
Memory
R 7 6 5 4 3 2 1 0
W
Reset DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
0 0
0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Table 4-5. FCDIV Field Descriptions
Field Description
7
Divisor Loaded Status Flag -- When set, this read-only status flag indicates that the FCDIV register has been
DIVLD written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
6 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
PRDIV8 1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
5:0 Prescale (Divide) FLASH Clock by 8
DIV[5:0] 0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider -- The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 s
to 6.7 s. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See Equation 4-1 and Equation 4-2.
if PRDIV8 = 0 -- fFCLK = fBus ([DIV5:DIV0] + 1) Eqn. 4-1
if PRDIV8 = 1 -- fFCLK = fBus (8 ([DIV5:DIV0] + 1)) Eqn. 4-2
Table 4-6 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Table 4-6. FLASH Clock Divider Settings
fBus PRDIV8 DIV5:DIV0 fFCLK Program/Erase Timing Pulse
(Binary) (Decimal) (5 s Min, 6.7 s Max)
8 MHz 200 kHz
4 MHz 0 39 200 kHz 5 s
2 MHz 0 19 200 kHz 5 s
1 MHz 0 9 200 kHz 5 s
200 kHz 0 4 200 kHz 5 s
150 kHz 0 0 150 kHz 5 s
0 0 6.7 s
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
50 Freescale Semiconductor
Memory
4.6.2 FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. Bits 5
through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning
or effect. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory
as usual and then issue a new MCU reset.
7 6 5 4 3 2 1 0
R KEYEN FNORED 0 0 0 0 SEC01 SEC00
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6. FLASH Options Register (FOPT)
Table 4-7. FOPT Field Descriptions
Field Description
7 Backdoor Key Mechanism Enable -- When this bit is 0, the backdoor key mechanism cannot be used to
KEYEN disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.5, "Security."
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.
6 Vector Redirection Disable -- When this bit is 1, then vector redirection is disabled.
FNORED 0 Vector redirection enabled.
1 Vector redirection disabled.
1:0 Security State Code -- This 2-bit field determines the security state of the MCU as shown below. When the
SEC0[1:0] MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any
unsecured source including the background debug interface. For more detailed information about security, refer
to Section 4.5, "Security."
00 Secure
01 Secure
10 Unsecured
11 Secure
SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH.
4.6.3 FLASH Configuration Register (FCNFG)
Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 51
Memory
7 6 5 4 3 2 1 0
R
KEYACC
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-7. FLASH Configuration Register (FCNFG)
Table 4-8. FCNFG Field Descriptions
Field Description
5 Enable Writing of Access Key -- This bit enables writing of the backdoor comparison key. For more detailed
KEYACC information about the backdoor key mechanism, refer to Section 4.5, "Security."
0 Writes to $FFB0$FFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY ($FFB0$FFB7) are interpreted as comparison key writes.
Reads of the FLASH return invalid data.
4.6.4 FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. Bits 0,
1, and 2 are not used and each always reads as 0. This register may be read at any time, but user program
writes have no meaning or effect. Background debug commands can write to FPROT at $1824.
7 6 5 4 3 2 1 0
R FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0
W (1) (1) (1) (1) (1)
Reset This register is loaded from nonvolatile location NVPROT during reset.
= Unimplemented or Reserved
Figure 4-8. FLASH Protection Register (FPROT)
1. Background commands can be used to change the contents of these bits in FPROT.
Table 4-9. FPROT Field Descriptions
Field Description
7 Open Unprotected FLASH for Program/Erase
FPOPEN 0 Entire FLASH memory is block protected (no program or erase allowed).
1 Any FLASH location, not otherwise block protected or secured, may be erased or programmed.
6
FPDIS FLASH Protection Disable
0 FLASH block specified by FPS2:FPS0 is block protected (program and erase not allowed).
5:3 1 No FLASH block is protected.
FPS[2:0]
FLASH Protect Size Selects -- When FPDIS = 0, this 3-bit field determines the size of a protected block of
FLASH locations at the high address end of the FLASH (see Table 4-10 and Table 4-11). Protected FLASH
locations cannot be erased or programmed.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
52 Freescale Semiconductor
Memory
Table 4-10. High Address Protected Block for 32K and 60K Versions
FPS2:FPS1:FPS0 Protected Address Range Protected Block Size Redirected Vectors(1)
0:0:0 $FE00$FFFF 512 bytes $FDC0$FDFD(2)
$FBC0$FBFD
0:0:1 $FC00$FFFF 1 Kbytes $F7C0$F7FD
$EFC0$EFFD
0:1:0 $F800$FFFF 2 Kbytes $DFC0$DFFD
$BFC0$BFFD
0:1:1 $F000$FFFF 4 Kbytes $7FC0$7FFD
$7FC0$7FFD
1:0:0 $E000$FFFF 8 Kbytes
1:0:1 $C000$FFFF 16 Kbytes
1:1:0(3) $8000$FFFF 32 Kbytes
1:1:1(3) $8000$FFFF 32 Kbytes
1. No redirection if FPOPEN = 0, or FNORED = 1.
2. Reset vector is not redirected.
3. Use for 60K version only. When protecting all of 32K version memory, use FPOPEN = 0.
Table 4-11. High Address Protected Block for 8K and 16K Version
FPS2:FPS1:FPS0 Protected Address Range Protected Block Size Redirected Vectors(1)
0:0:0 $FE00$FFFF 512 bytes $FDC0$FDFD(2)
$FBC0$FBFD
0:0:1 $FC00$FFFF 1 Kbytes $F7C0$F7FD
$EFC0$EFFD
0:1:0 $F800$FFFF 2 Kbytes $DFC0$DFFD
$DFC0$DFFD
0:1:1 $F000$FFFF 4 Kbytes $DFC0$DFFD
$DFC0$DFFD
1:0:0(3) $E000$FFFF 8 Kbytes
1:0:1(3) $E000$FFFF 8 Kbytes
1:1:0(3) $E000$FFFF 8 Kbytes
1:1:1(3) $E000$FFFF 8 Kbytes
1. No redirection if FPOPEN = 0, or FNORED = 1.
2. Reset vector is not redirected.
3. Use for 60K version only. When protecting all of 32K version memory, use FPOPEN = 0.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 53
Memory
4.6.5 FLASH Status Register (FSTAT)
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
7 6 5 4 3 2 1 0
R FCCF 0 FBLANK 0 0
FCBEF FPVIOL FACCERR
W
Reset 1 1 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-9. FLASH Status Register (FSTAT)
Table 4-12. FSTAT Field Descriptions
Field Description
7 FLASH Command Buffer Empty Flag -- The FCBEF bit is used to launch commands. It also indicates that the
FCBEF command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command may be written to the command buffer.
6 FLASH Command Complete Flag -- FCCF is set automatically when the command buffer is empty and no
FCCF command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
5 Protection Violation Flag -- FPVIOL is set automatically when FCBEF is cleared to register a command that
FPVIOL attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
4 Access Error Flag -- FACCERR is set automatically when the proper command sequence is not followed
FACCERR exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV
register has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see Section 4.4.5, "Access Errors." FACCERR
is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.
2 FLASH Verified as All Blank (erased) Flag -- FBLANK is set automatically at the conclusion of a blank check
FBLANK command if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a
new valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is
completely erased (all $FF).
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
54 Freescale Semiconductor
Memory
4.6.6 FLASH Command Register (FCMD)
Only four command codes are recognized in normal user modes as shown in Table 4-14. Refer to
Section 4.4.3, "Program and Erase Command Execution," for a detailed discussion of FLASH
programming and erase operations.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
W FCMD7 FCMD1 FCMD0
Reset FCMD6 FCMD5 FCMD4 FCMD3 FCMD2
0 0 0
0 0 0 0 0
Figure 4-10. FLASH Command Register (FCMD)
Table 4-13. FCMD Field Descriptions
Field Description
7:0 See Table 4-14 for FLASH commands.
FCMD[7:0]
Table 4-14. FLASH Commands
Command FCMD Equate File Label
Blank check $05 mBlank
Byte program $20
Byte program burst mode $25 mByteProg
Page erase (512 bytes/page) $40 mBurstProg
Mass erase (all FLASH) $41 mPageErase
mMassErase
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 55
Memory
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
56 Freescale Semiconductor
Chapter 5
Resets, Interrupts, and System Configuration
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08RC/RD/RE/RG. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this data sheet. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems having their own sections but are part of the system control logic.
5.2 Features
Reset and interrupt features include:
Multiple sources of reset for flexible system configuration and reliable operation:
-- Power-on detection (POR)
-- Low voltage detection (LVD) with enable
-- External reset pin with enable (RESET)
-- COP watchdog with enable and two timeout choices
-- Illegal opcode
-- Illegal address (on 16K and 8K devices)
-- Serial command from a background debug host
Reset status register (SRS) to indicate source of most recent reset; flag to indicate stop2 (partial
power down) mode recovery (PPDF)
Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-1)
Safe state for protecting the MCU in low-voltage condition
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector ($FFFE:$FFFF). On-chip peripheral modules are disabled and I/O pins are initially configured
as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the condition code
register (CCR) is set to block maskable interrupts until the user program has a chance to initialize the stack
pointer (SP) and system control settings. SP is forced to $00FF at reset.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 57
Resets, Interrupts, and System Configuration
The MC9S08RC/RD/RE/RG has these sources for reset:
Power-on reset (POR)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect
Illegal address (16K and 8K devices only)
Background debug forced reset
The reset pin (RESET)
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the reset pin is driven low for 34 internal
bus cycles where the internal bus frequency is one-half the OSC frequency. After the 34 cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin
is the cause of the MCU reset.
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point. The COP
watchdog is enabled by the COPE bit in SOPT (see Section 5.8.4, "System Options Register (SOPT)," for
additional information). The COP timer is reset by writing any value to the address of SRS. This write does
not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a
reset signal to the COP timer.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing
as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE
bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods
(218 or 220 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE
and COPT, the user must write to write-once SOPT during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost.
The write to SRS that services (clears) the COP timer must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
When the MCU is in active background mode, the COP timer is temporarily disabled.
5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than
the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
58 Freescale Semiconductor
Resets, Interrupts, and System Configuration
as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under
certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I
bit in the CCR is logic 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set
after reset, which masks (prevents) all maskable interrupt sources. The user program initializes the stack
pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence uses the same cycle-by-cycle sequence as the SWI instruction and
consists of:
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that restores the CCR, A,
X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.
NOTE
For compatibility with the M68HC08 Family, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it just before the RTI that is used to return from the ISR.
If two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-1).
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack, which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 59
Resets, Interrupts, and System Configuration
UNSTACKING TOWARD LOWER ADDRESSES
ORDER
7 0
51 CONDITION CODE REGISTER SP AFTER
42 ACCUMULATOR INTERRUPT STACKING
33
24 INDEX REGISTER (LOW BYTE X*) SP BEFORE
15 PROGRAM COUNTER HIGH THE INTERRUPT
PROGRAM COUNTER LOW
STACKING TOWARD HIGHER ADDRESSES
ORDER
* High byte (H) of index register is not automatically stacked.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address just recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag must be cleared at the beginning of the ISR so that if another interrupt is generated by
this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQSC status and control register. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in the IRQSC register must be 1 in order for the IRQ pin to act as
the interrupt request (IRQ) input. When the pin is configured as an IRQ input, the user can choose the
polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels
(IRQMOD), and whether an event causes an interrupt or merely sets the IRQF flag (which can be polled
by software).
When the IRQ pin is configured to detect rising edges, an optional pulldown resistor is available rather than
a pullup resistor. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is
configured to act as the IRQ input.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
60 Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located towards the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 61
Resets, Interrupts, and System Configuration
Table 5-1. Vector Summary
Vector Vector Address Vector Name Module Source Enable Description
Priority Number (High/Low)
Lower 16 $FFC0/FFC1 Unused Vector Space
through through (available for user program)
31 $FFDE/FFDF
15 $FFE0/FFE1 Vspi1 SPI(1) SPIF SPIE SPI
MODF SPIE
14 $FFE2/FFE3 Vrti System SPTEF SPTIE Real-time interrupt
Vkeyboard2 control Keyboard 2 pins
13 $FFE4/FFE5 Vkeyboard1 KBI2 RTIF RTIE Keyboard 1 pins
KBI1 ACMP compare
12 $FFE6/FFE7 Vacmp1 ACMP(2) KBF KBIE CMT
Vcmt CMT KBF KBIE SCI transmit
11 $FFE8/FFE9 Vsci1tx SCI(3) ACIE
ACF EOCIE SCI receive
10 $FFEA/FFEB Vsci1rx SCI(3) TIE
EOCF TCIE SCI error
9 $FFEC/FFED Vsci1err SCI(3) TDRE ILIE
RIE TPM overflow
8 $FFEE/FFEF Vtpm1ovf TPM TC ORIE TPM channel 1
Vtpm1ch1 TPM IDLE NFIE TPM channel 0
7 $FFF0/FFF1 Vtpm1ch0 TPM RDRF FEIE
IRQ OR PFIE IRQ pin
6 $FFF2/FFF3 Virq System NF TOIE Low-voltage detect
Vlvd control FE CH1IE
5 $FFF4/FFF5 Vswi Core PF CH0IE Software interrupt
TOF IRQIE Watchdog timer
4 $FFF6/FFF7 Vreset System CH1F Low-voltage detect
control CH0F LVDIE
3 $FFF8/FFF9 IRQF External pin
-- Illegal opcode
2 $FFFA/FFFB LVDF Illegal address
COPE
1 $FFFC/FFFD SWI LVDRE
Instruction RSTPE
0 $FFFE/FFFF
COP --
Higher LVD --
RESET pin
Illegal opcode
Illegal address
1. The SPI module is not included on the MC9S08RC/RD/RE devices. This vector location is unused for those devices.
2. The analog comparator (ACMP) module is not included on the MC9S08RD devices. This vector location is unused for those
devices.
3. The SCI module is not included on the MC9S08RC devices. This vector location is unused for those devices.
5.6 Low-Voltage Detect (LVD) System
The MC9S08RC/RD/RE/RG includes a system to protect against low-voltage conditions in order to
protect memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit, an LVD circuit with flag bits for warning and detection, and
a mechanism for entering a system safe state following an LVD interrupt. The LVD circuit can be
configured to generate an interrupt or a reset when low supply voltage has been detected.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
62 Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the VLVD level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition. This is done by
setting LVDRE to 1. LVDRE is a write-once bit that is set following a POR and is unaffected by other
resets. When LVDRE = 1, setting the SAFE bit has no effect. After an LVD reset has occurred, the LVD
system will hold the MCU in reset until the supply voltage is above the VLVD level. The LVD bit in the
SRS register is set following either an LVD reset or POR.
5.6.3 LVD Interrupt and Safe State Operation
When the voltage on the supply pin VDD drops below VLVD and the LVD circuit is configured for interrupt
operation (LVDIE is set and LVDRE is clear), an LVD interrupt will occur. The LVD trip point is set above
the minimum voltage at which the MCU can reliably operate, but the supply voltage may still be dropping.
It is recommended that the user place the MCU in the safe state as soon as possible following a LVD
interrupt. For systems where the supply voltage may drop so rapidly that the MCU may not have time to
service the LVD interrupt and enter the safe state, it is recommended that the LVD be configured to
generate a reset. The safe state is entered by executing a STOP instruction with the SAFE bit in the system
power management status and control 1 (SPMSC1) register set while in a low voltage condition
(LVDF = 1).
After the LVD interrupt has occurred, the user may configure the system to block all interrupts, resets, or
wakeups by writing a 1 to the SAFE bit. While SAFE =1 and VDD is below VREARM all interrupts, resets,
and wakeups are blocked. After VDD is above VREARM, the SAFE bit is ignored (the SAFE bit will still
read a 1). After setting the SAFE bit, the MCU must be put into either the stop3 or stop2 mode before the
supply voltage drops below the minimum operating voltage of the MCU. The supply voltage may now
drop to a level just above the POR trip point and then restored to a level above VREARM and the MCU state
(in the case of stop3) and RAM contents will be preserved. When the supply voltage has been restored,
interrupts, resets, and wakeups are then unblocked. When the MCU has recovered from stop mode, the
SAFE bit should be cleared.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the low-voltage detect voltage. The LVW does not have an interrupt
associated with it. However, the FLASH memory cannot be reliably programmed or erased below the
VLVW level, so the status of the LVWF bit in the system power management status and control 2 (SPMSC2)
register must be checked before initiating any FLASH program or erase operation.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 63
Resets, Interrupts, and System Configuration
5.7 Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the
source clock's period. The RTI has two source clock choices, the external clock input or the RTI's own
internal clock. The RTI can be used in run, wait, stop2, and stop3 modes. It is not available in stop1 mode.
In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only
the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used.
When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and
configured for low bandwidth operation (RANGE = 0).
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable,
RTIE, to allow masking of the real-time interrupt. The module can be disabled by writing 0:0:0 to
RTIS2:RTIS1:RTIS0 in which case the clock source input is disabled and no interrupts will be generated.
See Section 5.8.6, "System Real-Time Interrupt Status and Control Register (SRTISC)," for detailed
information about this register.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and five 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, "Modes of Operation."
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes two unimplemented bits that always read 0, four read/write bits, one
read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status,
and acknowledge IRQ events.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
64 Freescale Semiconductor
Resets, Interrupts, and System Configuration
7 6 5 4 3 2 1 0
R 0 0 IRQF 0 IRQMOD
W 0
Reset IRQEDG IRQPE IRQIE
IRQACK
0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-2. IRQSC Field Descriptions
Field Description
5 Interrupt Request (IRQ) Edge Select -- This read/write control bit is used to select the polarity of edges or
IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
4 to detect rising edges, the optional pullup resistor is reconfigured as an optional pulldown resistor.
IRQPE 0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
3
IRQF IRQ Pin Enable -- This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
2 resistor is enabled depending on the state of the IRQMOD bit.
IRQACK 0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
1
IRQIE IRQ Flag -- This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
0 1 IRQ event detected.
IRQMOD
IRQ Acknowledge -- This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable -- This read/write control bit determines whether IRQ events generate a hardware
interrupt request.
0 Hardware interrupt requests from IRQF disabled (use polling).
1 Hardware interrupt requested whenever IRQF = 1.
IRQ Detection Mode -- This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, "Edge and Level Sensitivity," for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
5.8.2 System Reset Status Register (SRS)
This register includes six read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 65
Resets, Interrupts, and System Configuration
7 6 5 4 3 2 1 0
R POR PIN COP ILOP ILAD(1) 0 LVD 0
W Writing any value to SRS address clears COP watchdog timer.
POR 1 0 0 0 0 0 1 0
LVR u 0 0 0 0 0 1 0
Any other 0 (2) (2) (2) (2) 0 0 0
reset:
u = Unaffected by reset
Figure 5-3. System Reset Status (SRS)
1. The ILAD bit is only present in 16K and 8K versions of the devices.
2. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
Field Table 5-3. SRS Field Descriptions
7
Description
POR
Power-On Reset -- Reset was caused by the power-on detection logic. Because the internal supply voltage was
6 ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
PIN the internal supply was below the LVR threshold.
0 Reset not caused by POR.
5 1 POR caused reset.
COP
External Reset Pin -- Reset was caused by an active-low level on the external reset pin.
4 0 Reset not caused by external reset pin.
ILOP 1 Reset came from external reset pin.
3 Computer Operating Properly (COP) Watchdog -- Reset was caused by the COP watchdog timer timing out.
ILAD This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 1 Reset caused by COP timeout.
LVD
Illegal Opcode -- Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address Access -- Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access
1 Reset caused by an illegal address access
Illegal address areas only exist in the 16K and 8K versions and are defined as:
$0440$17FF -- Gap from end of RAM to start of high-page registers
$1834$BFFF -- Gap from end of high-page registers to start of FLASH memory
Unused and reserved locations in register areas are not considered designated illegal addresses and do not
trigger illegal address resets.
Low Voltage Detect -- If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset
occurs. This bit is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
66 Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.8.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return $00.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
BDFR(1)
W
0
Reset 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
1. BDFR is writable only through serial background debug commands, not from user programs.
Field Table 5-4. SBDFR Field Descriptions
0 Description
BDFR
Background Debug Force Reset -- A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit
cannot be written from a user program.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 67
Resets, Interrupts, and System Configuration
5.8.4 System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
must be written during the user's reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
7 6 5 4 3 2 1 0
R COPE 0 0 BKGDPE RSTPE
W 1
Reset COPT STOPE
1 0 1 0 0 1 1
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Field Descriptions
Field Description
7 COP Watchdog Enable -- This write-once bit defaults to 1 after reset.
COPE 0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT COP Watchdog Timeout -- This write-once bit defaults to 1 after reset.
0 Short timeout period selected (218 cycles of BUSCLK).
5 1 Long timeout period selected (220 cycles of BUSCLK).
STOPE
Stop Mode Enable -- This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
1 disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
BKGDPE 0 Stop mode disabled.
1 Stop mode enabled.
0
RSTPE Background Debug Mode Pin Enable -- The BKGDPE bit enables the PTD0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTD0, which is an output only general purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
RESET Pin Enable -- The RSTPE bit enables the PTD1/RESET pin to function as RESET. When the bit is clear,
the pin will function as PTD1, which is an output only general purpose I/O. This pin always defaults to RESET
function after any reset.
0 RESET pin disabled.
1 RESET pin enabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
68 Freescale Semiconductor
Resets, Interrupts, and System Configuration
5.8.5 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
7 6 5 4 3 2 1 0
R REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
W
Reset 0(1) 0(1) 0(1) 0(1) 0 0 0 0
= Unimplemented or Reserved
Figure 5-6. System Device Identification Register -- High (SDIDH)
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Table 5-6. SDIDH Field Descriptions
Field Description
7:4 Revision Number -- The high-order 4 bits of address $1806 are hard coded to reflect the current mask set
REV[3:0] revision number (0F).
3:0 Part Identification Number -- Each derivative in the HCS08 Family has a unique identification number. The
ID[11:8] MC9S08RC/RD/RE/RG32/60 is hard coded to the value $004 and the MC9S08RC/RD/RE8/16 is hard coded to
the value $003.
7 6 5 4 3 2 1 0
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset, 8/16K: 0 0 0 0 0 1 1 1
Reset, 32/60K: 0 0 0 0 0 1 0 0
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register -- Low (SDIDL)
Table 5-7. SDIDL Field Descriptions
Field Description
7:0 Part Identification Number -- Each derivative in the HCS08 Family has a unique identification number. The
ID[7:0] MC9S08RC/RD/RE/RG32/60 is hard coded to the value $004 and the MC9S08RC/RD/RE8/16 is hard coded to
the value $003.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 69
Resets, Interrupts, and System Configuration
5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC)
This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay
selects, and three unimplemented bits, which always read 0.
7 6 5 4 3 2 1 0
R RTIF 0 RTICLKS RTIE 0 RTIS0
W RTIACK 0
Reset 0 RTIS2 RTIS1
0 0 0 0 0 0
= Unimplemented or Reserved
Figure 5-8. System RTI Status and Control Register (SRTISC)
Table 5-8. SRTISC Field Descriptions
Field Description
7
Real-Time Interrupt Flag -- This read-only status bit indicates the periodic wakeup timer has timed out.
RTIF 0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK Real-Time Interrupt Acknowledge -- This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS Real-Time Interrupt Clock Select -- This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal 1-kHz oscillator.
4 1 Real-time interrupt request clock source is external clock.
RTIE
Real-Time Interrupt Enable -- This read-write bit enables real-time interrupts.
2:0 0 Real-time interrupts disabled.
RTIS[2:0] 1 Real-time interrupts enabled.
Real-Time Interrupt Period Selects -- These read/write bits select the wakeup period for the RTI. One clock
source for the real-time interrupt is its own internal clock source, which oscillates with a period of approximately
tRTI and is independent of other MCU clock sources. Using an external clock source the delays will be crystal
frequency divided by value in RTIS2:RTIS1:RTIS0. See Table 5-9.
Table 5-9. Real-Time Interrupt Period
RTIS2:RTIS1:RTIS0 Internal Clock Source (1) External Clock Source (2)
(tRTI = 1 ms, Nominal) Period = text
0:0:0 Disable periodic wakeup timer Disable periodic wakeup timer
0:0:1 8 ms text x 256
0:1:0 32 ms tex x 1024
0:1:1 64 ms tex x 2048
1:0:0 128 ms tex x 4096
1:0:1 256 ms text x 8192
1:1:0 512 ms text x 16384
1:1:1 1.024 s tex x 32768
1. See Table A-9 tRTI in Appendix A, "Electrical Characteristics," for the tolerance on these values.
2. text is based on the external clock source, resonator, or crystal selected by the ICG configuration. See Table A-9 for details.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
70 Freescale Semiconductor
5.8.7 Resets, Interrupts, and System Configuration
System Power Management Status and Control 1 Register
(SPMSC1)
7 6 5 4 3 2 1 0
R LVDF 0 LVDRE(1) 0 0 0
LVDIE SAFE
W LVDACK
POR: 0 0 0 0 1 0 0 0
Any other 0 0 0 0 u 0 0 0
reset:
= Unimplemented or Reserved u = Unaffected by reset
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
1. This bit can be written only one time after reset. Additional writes are ignored.
Table 5-10. SPMSC1 Field Descriptions
Field Description
7 Low-Voltage Detect Flag -- Provided LVDE = 1, this read-only status bit indicates a low-voltage detect error.
LVDF
Low-Voltage Detect Acknowledge -- This write-only bit is used to acknowledge low voltage detection errors
6 (write 1 to clear LVDF). Reads always return logic 0.
LVDACK
Low-Voltage Detect Interrupt Enable -- This read/write bit enables hardware interrupt requests for LVDF.
5 0 Hardware interrupt disabled (use polling).
LVDIE 1 Request a hardware interrupt when LVDF = 1.
4 SAFE System from interrupts -- This read/write bit enables hardware to block interrupts and resets from
SAFE waking the MCU from stop mode while the supply voltage VDD is below the VREARM voltage. For a more detailed
description see Section 5.6.3, "LVD Interrupt and Safe State Operation"
3 0 Enable pending interrupts and resets
LVDRE 1 Interrupts and resets are blocked while supply voltage is below re-arm voltage
Low-Voltage Detect Reset Enable -- This bit enables the LVD reset function. This bit can be written only once
after a reset and additional writes have no meaning or effect. It is set following a POR and is unaffected by any
other resets, including an LVD reset.
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 71
Resets, Interrupts, and System Configuration
5.8.8 System Power Management Status and Control 2 Register
(SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
7 6 5 4 3 2 1 0
R LVWF 0 0 0 PPDF 0 PPDC
0
PDC
W LVWACK PPDACK
Reset 0(1) 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
1. LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.
Table 5-11. SPMSC2 Field Descriptions
Field Description
7 Low-Voltage Warning Flag -- The LVWF bit indicates the low voltage warning status.
LVWF 0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK Low-Voltage Warning Acknowledge -- The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
3
PPDF Partial Power Down Flag -- The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
2 1 Stop2 mode recovery.
PPDACK
Partial Power Down Acknowledge -- Writing a logic 1 to PPDACK clears the PPDF bit.
1
PDC Power Down Control -- The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
0 1 Power down modes are enabled.
PPDC
Partial Power Down Control -- The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
72 Freescale Semiconductor
Chapter 6
Parallel Input/Output
6.1 Introduction
This section explains software controls related to parallel input/output (I/O). The MC9S08RC/RD/RE/RG
has five I/O ports that include a total of 39 general-purpose I/O pins (two of these pins are output only and
one pin is input only). Not all of the ports are available in all packages. See Chapter 2, "Pins and
Connections," for more information about the logic and hardware aspects of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or
keyboard interrupts. When these other modules are not controlling the port pins, they revert to
general-purpose I/O control. For each I/O pin, a port data bit provides access to input (read) and output
(write) data. A data direction bit controls the direction of the pin and a pullup enable bit enables an internal
pullup device (if the pin is configured as an input).
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user's reset initialization
routine in the application program should either enable on-chip pullup
devices or change the direction of unconnected pins to outputs so the pins
do not float.
6.2 Features
Parallel I/O features for the MC9S08RC/RD/RE/RG MCUs, depending on specific device and package
choice, include:
A total of 39 general-purpose I/O pins in five ports (two pins are output only, one is input only)
High-current drivers on port B pins
Hysteresis input buffers on all inputs
Software-controlled pullups on each input pin
Eight port A pins shared with KBI1
Eight port B pins shared with SCI and TPMCH1
Eight port C pins shared with KBI2 and SPI
Seven port D pins shared with TPMCH0, ACMP, IRQ, RESET, and BKGD/MS
Eight port E pins
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 73
Parallel Input/Output
6.3 Pin Descriptions
The MC9S08RC/RD/RE/RG has a total of 39 parallel I/O pins distributed between four 8-bit ports and one
7-bit port. Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2, "Pins and
Connections," for available parallel I/O pins. All of these pins are available for general-purpose I/O when
they are not used by other on-chip peripheral systems.
The following paragraphs discuss each port and the software controls that determine each pin's use.
6.3.1 Port A
Port A Bit 7 6 5 4 3 2 1 Bit 0
MCU Pin: PTA7/ PTA6/ PTA5/ PTA4/ PTA3/ PTA2/ PTA1/ PTA0/
KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0
Figure 6-1. Port A Pin Names
Port A is an 8-bit general-purpose I/O port shared with the KBI1 keyboard interrupt inputs. Bit 0 of port
A is an input-only pin.
Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction
(PTADD), and pullup enable (PTAPE) registers. Refer to Section 6.4, "Parallel I/O Controls," for more
information about general-purpose I/O control.
Any of the port A pins can be configured as a KBI1 keyboard interrupt pin. Refer to the Keyboard Interrupt
(KBI) Module chapter for more information about using port A pins as keyboard interrupt pins.
6.3.2 Port B
Port B Bit 7 6 5 4 3 2 1 Bit 0
PTB2
MCU Pin: PTB7/ PTB6 PTB5 PTB4 PTB3 PTB1/ PTB0/
TPM1CH1 RxD1 TxD1
Figure 6-2. Port B Pin Names
Port B is an 8-bit general-purpose I/O port with two pins shared with the SCI and one pin shared with the
TPM. The port B output drivers are capable of high current drive.
Port B pins are available as general-purpose I/O pins controlled by the port B data (PTBD), data direction
(PTBDD), and pullup enable (PTBPE) registers. Refer to Section 6.4, "Parallel I/O Controls," for more
information about general-purpose I/O control.
When the SCI module is enabled, PTB0 and PTB1 function as the transmit (TxD1) and receive (RxD1)
pins of the SCI. Refer to the Serial Communications Interface (SCI) Module chapter for more information
about using PTB0 and PTB1 as SCI pins.
The TPM can be configured to use PTB7 as either an input capture, output compare, or PWM pin. Refer
to the Timer/PWM Module (TPM) Module chapter for more information about using PTB7 as a timer pin.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
74 Freescale Semiconductor
Parallel Input/Output
6.3.3 Port C
Port C Bit 7 6 5 3 3 2 1 Bit 0
MCU Pin: PTC7/ PTC6/ PTC5/ PTC4/ PTC3/ PTC2/ PTC1/ PTC0/
SS1 SPSCK1 MISO1 MOSI1 KBI2P3 KBI2P2 KBI2P1 KBI2P0
Figure 6-3. Port C Pin Names
Port C is an 8-bit general-purpose I/O port with four pins shared with the KBI2 keyboard interrupt inputs
and four pins shared with the SPI.
Port C pins are available as general-purpose I/O pins controlled by the port C data (PTCD), data direction
(PTCDD), and pullup enable (PTCPE) registers. Refer to Section 6.4, "Parallel I/O Controls," for more
information about general-purpose I/O control.
When the SPI module is enabled, PTC7 serves as the SPI module's slave select pin (SS1), PTC6 serves as
the SPI clock pin (SPSCK1), PTC5 serves as the master-in slave-out pin (MISO1), and PTC4 serves as the
master-out slave-in pin (MOSI1). Refer to the Serial Peripheral Interface (SPI) Module chapter for more
information about using PTC7PTC4 as SPI pins.
Any of the port C pins PTC3-PTC0 can be configured as a KBI2 keyboard interrupt pin. Refer to the
Keyboard Interrupt (KBI) Module chapter for more information about using port C pins as keyboard
interrupt pins.
6.3.4 Port D
Port D Bit 7 6 5 4 3 2 1 Bit 0
PTD2
MCU Pin: PTD6/ PTD5 PTD4 PTD3 PTD1/ PTD0/
TPM1CH0 RESET BKGD/MS
Figure 6-4. Port D Pin Names
Port D is an 7-bit general-purpose I/O port with one pin shared with the BKGD/MS function, one pin
shared with the RESET function, one pin shared with the IRQ function, and one pin shared with the TPM.
Port D pins are available as general-purpose I/O pins controlled by the port D data (PTDD), data direction
(PTDDD), and pullup enable (PTDPE) registers. Refer to Section 6.4, "Parallel I/O Controls," for more
information about general-purpose I/O control.
The PTD0/BKGD/MS pin is configured for the BKGD/MS function during reset and following reset. The
internal pullup for this pin is enabled when the BKGD/MS function is enabled, regardless of the PTDPE0
bit. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU is out of reset, the
BKGD/MS pin becomes the background communications input/output pin. PTD0 can be configured to be
a general-purpose output pin through software control. Refer to Chapter 3, "Modes of Operation,"
Chapter 5, "Resets, Interrupts, and System Configuration," and the Development Support chapter for more
information about using this pin.
The PTD1/RESET pin is configured for the RESET function during reset and following reset.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 75
Parallel Input/Output
The TPM can be configured to use PTD6 as either an input capture, output compare, PWM, or external
clock input pin. Refer to the Chapter 6, "Parallel Input/Output," for more information about using PTD6
as a timer pin.
6.3.5 Port E
Port E Bit 7 6 5 4 3 2 1 Bit 0
MCU Pin: PTE7 PTE2 PTE1 PTE0
PTE6 PTE5 PTE4 PTE3
Figure 6-5. Port E Pin Names
Port E is an 8-bit general-purpose I/O port.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), and pullup enable (PTEPE) registers. Refer to Section 6.4, "Parallel I/O Controls," for more
information about general-purpose I/O control.
6.4 Parallel I/O Controls
Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that
are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), and a pullup
enable register (PTxPE) where x is A, B, C, D, or E.
Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if
PTxDDn = 1). Writes to the port data register are latched into the port register whether the pin is controlled
by an on-chip peripheral or the pin is configured as an input. If the corresponding pin is not controlled by
a peripheral and is configured as an output, this level will be driven out the port pin.
6.4.1 Data Direction Control
The data direction control bits determine whether the pin output driver is enabled, and they control what
is read for port data register reads. Each port pin has a data direction control bit. When PTxDDn = 0, the
corresponding pin is an input and reads of PTxD return the pin value. When PTxDDn = 1, the
corresponding pin is an output and reads of PTxD return the last value written to the port data register.
When a peripheral module or system function is in control of a port pin, the data direction control still
controls what is returned for reads of the port data register, even though the peripheral system has
overriding control of the actual pin direction.
For the MC9S08RC/RD/RE/RG MCU, reads of PTD0/BKGD/MS and PTD1/RESET will return the value
on the output pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven with an old data value that happened
to be in the port data register.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
76 Freescale Semiconductor
Parallel Input/Output
6.4.2 Internal Pullup Control
An internal pullup device can be enabled for each port pin that is configured as an input (PTxDDn = 0).
The pullup device is available for a peripheral module to use, provided the peripheral is enabled and is an
input function as long as the PTxDDn = 0.
NOTE
The voltage measured on the pulled up PTA0 pin will be less than VDD. The
internal gates connected to this pin are pulled all the way to VDD. All other
pins with enabled pullup resistors will have an unloaded measurement of
VDD.
6.5 Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
When the MCU enters stop1 mode, all internal registers, including general-purpose I/O control and
data registers, are powered down. All of the general-purpose I/O pins assume their reset state:
output buffers and pullups turned off. Upon exit from stop1, all I/O must be initialized as if the
MCU had been reset.
When the MCU enters stop2 mode, the internal registers are powered down as in stop1 but the I/O
pin states are latched and held. For example, a port pin that is an output driving low continues to
function as an output driving low even though its associated data direction and output data registers
are powered down internally. Upon exit from stop2, the pins continue to hold their states until a 1
is written to the PPDACK bit. To avoid discontinuity in the pin state following exit from stop2, the
user must restore the port control and data registers to the values they held befor4e entering stop2.
These values can be stored in RAM before entering stop2 because the RAM is maintained during
stop2.
In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.6 Parallel I/O Registers and Control Bits
This section provides information about all registers and control bits associated with the parallel I/O ports.
Refer to tables in the Memory chapter for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 77
Parallel Input/Output
6.6.1 Port A Registers (PTAD, PTAPE, and PTADD)
Port A pins used as general-purpose I/O pins are controlled by the port A data (PTAD), data direction
(PTADD), and pullup enable (PTAPE) registers.
R 7 6 5 4 3 2 1 0
W
Reset PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0 0 0
0 0 0 0 0
Figure 6-6. Port A Data Register (PTAD)
Table 6-1. PTAD Field Descriptions
Field Description
7:0 Port A Data Register Bits -- For port A pins that are inputs, reads of this register return the logic level on the
PTAD[7:0] pin. For port A pins that are configured as outputs, reads of this register return the last value written to this
register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R 7 6 5 4 3 2 1 0
W
Reset PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0 0 0
0 0 0 0 0
Figure 6-7. Pullup Enable for Port A (PTAPE)
Table 6-2. PTAPE Field Descriptions
Field Description
7:0 Pullup Enable for Port A Bits -- For port A pins that are inputs, these read/write control bits determine whether
PTAPE[7:0] internal pullup devices are enabled provided the corresponding PTADDn is a logic 0. For port A pins that are
configured as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7
through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup
enable bits enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
78 Freescale Semiconductor
Parallel Input/Output
R 7 6 5 4 3 2 1 0
W
Reset PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0 0 0
0 0 0 0 0
Figure 6-8. Data Direction for Port A (PTADD)
Table 6-3. PTADD Field Descriptions
Field Description
7:0 Data Direction for Port A Bits -- These read/write bits control the direction of port A pins and what is read for
PTADD[7:0] PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.6.2 Port B Registers (PTBD, PTBPE, and PTBDD)
Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction
(PTBDD), and pullup enable (PTBPE) registers.
R 7 6 5 4 3 2 1 0
W
Reset PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0 0 0
0 0 0 0 0
Figure 6-9. Port B Data Register (PTBD)
Table 6-4. PTBD Field Descriptions
Field Description
7:0 Port B Data Register Bits -- For port B pins that are inputs, reads return the logic level on the pin. For port B
PTBD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 79
Parallel Input/Output
R 7 6 5 4 3 2 1 0
W
Reset PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0 0 0
0 0 0 0 0
Figure 6-10. Pullup Enable for Port B (PTBPE)
Table 6-5. PTBPE Field Descriptions
Field Description
7:0 Pullup Enable for Port B Bits -- For port B pins that are inputs, these read/write control bits determine whether
PTBPE[7:0] internal pullup devices are enabled. For port B pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
7 6 5 4 3 2 1 0
R PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
PTBDD7 0 0
W
Reset 0 0 0 0 0 0
Figure 6-11. Data Direction for Port B (PTBDD)
Table 6-6. PTBDD Field Descriptions
Field Description
7:0 Data Direction for Port B Bits -- These read/write bits control the direction of port B pins and what is read for
PTBDD[7:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
80 Freescale Semiconductor
Parallel Input/Output
6.6.3 Port C Registers (PTCD, PTCPE, and PTCDD)
Port C pins used as general-purpose I/O pins are controlled by the port C data (PTCD), data direction
(PTCDD), and pullup enable (PTCPE) registers.
R 7 6 5 4 3 2 1 0
W
Reset PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
0 0 0
0 0 0 0 0
Figure 6-12. Port C Data Register (PTCD)
Table 6-7. PTCD Field Descriptions
Field Description
7:0 Port C Data Register Bits -- For port C pins that are inputs, reads return the logic level on the pin. For port C
PTCD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7 6 5 4 3 2 1 0
R PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
PTCPE7 0 0
W
Reset 0 0 0 0 0 0
Figure 6-13. Pullup Enable for Port C (PTCPE)
Table 6-8. PTCPE Field Descriptions
Field Description
7:0 Pullup Enable for Port C Bits -- For port C pins that are inputs, these read/write control bits determine whether
PTCPE[7:0] internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 81
Parallel Input/Output
7 6 5 4 3 2 1 0
R PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
PTCDD7 0 0
W
Reset 0 0 0 0 0 0
Figure 6-14. Data Direction for Port C (PTCDD)
Table 6-9. PTCDD Field Descriptions
Field Description
7:0 Data Direction for Port C Bits -- These read/write bits control the direction of port C pins and what is read for
PTCDD[7:0] PTCD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
6.6.4 Port D Registers (PTDD, PTDPE, and PTDDD)
Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction
(PTDDD), and pullup enable (PTDPE) registers.
7 6 5 4 3 2 1 0
R 0 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 6-15. Port D Data Register (PTDD)
Table 6-10. PTDD Field Descriptions
Field Description
6:0 Port D Data Register Bits -- For port D pins that are inputs, reads return the logic level on the pin. For port D
PTDD[6:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
82 Freescale Semiconductor
Parallel Input/Output
7 6 5 4 3 2 1 0
R 0 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 6-16. Pullup Enable for Port D (PTDPE)
Table 6-11. PTDPE Field Descriptions
Field Description
6:0 Pullup Enable for Port D Bits -- For port D pins that are inputs, these read/write control bits determine whether
PTDPE[6:0] internal pullup devices are enabled. For port D pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
7 6 5 4 3 2 1 0
R 0 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 6-17. Data Direction for Port D (PTDDD)
Table 6-12. PTDDD Field Descriptions
Field Description
6:0 Data Direction for Port D Bits -- These read/write bits control the direction of port D pins and what is read for
PTDDD[6:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 83
Parallel Input/Output
6.6.5 Port E Registers (PTED, PTEPE, and PTEDD)
Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction
(PTEDD), and pullup enable (PTEPE) registers.
R 7 6 5 4 3 2 1 0
W
Reset PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0 0 0
0 0 0 0 0
Figure 6-18. Port E Data Register (PTED)
Table 6-13. PTED Field Descriptions
Field Description
7:0 Port E Data Register Bits -- For port E pins that are inputs, reads return the logic level on the pin. For port E
PTED[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R 7 6 5 4 3 2 1 0
W
Reset PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0 0 0
0 0 0 0 0
Figure 6-19. Pullup Enable for Port E (PTED)
Table 6-14. PTED Field Descriptions
Field Description
7:0 Pullup Enable for Port E Bits -- For port E pins that are inputs, these read/write control bits determine whether
PTED[7:0] internal pullup devices are enabled. For port E pins that are configured as outputs, these bits are ignored and
the internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
84 Freescale Semiconductor
Parallel Input/Output
7 6 5 4 3 2 1 0
R PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
PTEDD7 0 0
W
Reset 0 0 0 0 0 0
Figure 6-20. Data Direction for Port E (PTEDD)
Table 6-15. PTEDD Field Descriptions
Field Description
7:0 Data Direction for Port E Bits -- These read/write bits control the direction of port E pins and what is read for
PTEDD[7:0] PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
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Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
7.1.1 Features
Features of the HCS08 CPU include:
Object code fully upward-compatible with M68HC05 and M68HC08 Families
All registers and memory are mapped to a single 64-Kbyte address space
16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
-- Inherent -- Operands in internal registers
-- Relative -- 8-bit signed offset to branch destination
-- Immediate -- Operand in next object code byte(s)
-- Direct -- Operand in memory at 0x00000x00FF
-- Extended -- Operand anywhere in 64-Kbyte address space
-- Indexed relative to H:X -- Five submodes including auto increment
-- Indexed relative to SP -- Improves C efficiency dramatically
Memory-to-memory data move instructions with four address mode combinations
Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
Efficient bit manipulation instructions
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
STOP and WAIT instructions to invoke low-power operating modes
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7.2 Programmer's Model and CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 0
ACCUMULATOR A
16-BIT INDEX REGISTER H:X
H INDEX REGISTER (HIGH) INDEX REGISTER (LOW) X
15 87 0
SP
STACK POINTER
15 0
PROGRAM COUNTER PC
7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO'S COMPLEMENT OVERFLOW
Figure 7-1. CPU Registers
7.2.1 Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.
7.2.2 Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
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7.2.3 Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
7.2.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at $FFFE and $FFFF. The
vector stored there is the address of the first instruction that will be executed after exiting the reset state.
7.2.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1/D.
7 0
CONDITION CODE REGISTER V 1 1 H I N Z C CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO'S COMPLEMENT OVERFLOW
Figure 7-2. Condition Code Register
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Field Table 7-1. CCR Register Field Descriptions
7
V Description
4 Two's Complement Overflow Flag -- The CPU sets the overflow flag when a two's complement overflow occurs.
H The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
3 1 Overflow
I
Half-Carry Flag -- The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
2 an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
N decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
1 result to a valid BCD value.
Z 0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
0
C Interrupt Mask Bit -- When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
Negative Flag -- The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
Zero Flag -- The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
Carry/Borrow Flag -- The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and
branch, shift, and rotate -- also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
7.3 Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
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of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
7.3.1 Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
7.3.2 Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
7.3.3 Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
7.3.4 Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x00000x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
7.3.5 Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
7.3.6 Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
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7.3.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
7.3.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
7.3.6.3 Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
7.3.6.5 Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6 SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.7 SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.4 Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
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7.4.1 Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
7.4.2 Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
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7.4.3 Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
7.4.4 Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.
7.4.5 BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background
mode rather than continuing the user program.
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7.5 HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 7-2.
Operators
( ) = Contents of register or memory location shown inside parentheses
= Is loaded with (read: "gets")
& = Boolean AND
| = Boolean OR
= Boolean exclusive-OR
= Multiply
= Divide
: = Concatenate
+ = Add
= Negate (two's complement)
CPU registers Accumulator
Condition code register
A= Index register, higher order (most significant) 8 bits
CCR = Index register, lower order (least significant) 8 bits
Program counter
H= Program counter, higher order (most significant) 8 bits
X= Program counter, lower order (least significant) 8 bits
PC = Stack pointer
PCH =
PCL =
SP =
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Condition code register (CCR) bits
V = Two's complement overflow indicator, bit 7
H = Half carry, bit 4
I = Interrupt mask, bit 3
N = Negative indicator, bit 2
Z = Zero indicator, bit 1
C = Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
= Bit not affected
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0 = Bit forced to 0
1 = Bit forced to 1
= Bit set or cleared according to results of operation
U = Undefined after the operation
Machine coding notation
dd = Low-order 8 bits of a direct address 0x00000x00FF (high byte assumed to be 0x00)
ee = Upper 8 bits of 16-bit offset
ff = Lower 8 bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
rr = Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n -- Any label or expression that evaluates to a single integer in the range 07
opr8i -- Any label or expression that evaluates to an 8-bit immediate value
opr16i -- Any label or expression that evaluates to a 16-bit immediate value
opr8a -- Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a -- Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 -- Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
oprx16 -- Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
rel -- Any label or expression that refers to an address that is within 128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes Inherent (no operands)
8-bit or 16-bit immediate
INH = 8-bit direct
IMM = 16-bit extended
DIR =
EXT =
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IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer with 8-bit offset
SP2 = Stack pointer with 16-bit offset
Table 7-2. HCS08 Instruction Set Summary (Sheet 1 of 7)
Source Operation Description Effect Address
Form on CCR Mode
VH I NZC Opcode
Operand
Bus Cycles1
ADC #opr8i IMM A9 ii 2
ADC opr8a
ADC opr16a DIR B9 dd 3
ADC oprx16,X
ADC oprx8,X EXT C9 hh ll 4
ADC ,X
ADC oprx16,SP Add with Carry A (A) + (M) + (C) IX2 D9 ee ff 4
ADC oprx8,SP IX1
Add without Carry E9 ff 3
ADD #opr8i
ADD opr8a Add Immediate Value IX F9 3
ADD opr16a (Signed) to Stack Pointer
ADD oprx16,X Add Immediate Value SP2 9ED9 ee ff 5
ADD oprx8,X (Signed) to Index
ADD ,X Register (H:X) SP1 9EE9 ff 4
ADD oprx16,SP
ADD oprx8,SP Logical AND IMM AB ii 2
AIS #opr8i Arithmetic Shift Left DIR BB dd 3
(Same as LSL)
AIX #opr8i EXT CB hh ll 4
Arithmetic Shift Right
AND #opr8i Branch if Carry Bit Clear A (A) + (M) IX2 DB ee ff 4
AND opr8a IX1
AND opr16a SP (SP) + (M) EB ff 3
AND oprx16,X M is sign extended to a 16-bit value
AND oprx8,X IX FB 3
AND ,X H:X (H:X) + (M)
AND oprx16,SP M is sign extended to a 16-bit value SP2 9EDB ee ff 5
AND oprx8,SP
A (A) & (M) SP1 9EEB ff 4
ASL opr8a
ASLA IMM A7 ii 2
ASLX
ASL oprx8,X IMM AF ii 2
ASL ,X
ASL oprx8,SP IMM A4 ii 2
ASR opr8a DIR B4 dd 3
ASRA
ASRX EXT C4 hh ll 4
ASR oprx8,X
ASR ,X 0 IX2 D4 ee ff 4
ASR oprx8,SP IX1
E4 ff 3
BCC rel
IX F4 3
SP2 9ED4 ee ff 5
SP1 9EE4 ff 4
DIR 38 dd 5
INH 48 1
C 0 INH 58 1
b7 b0 IX1
68 ff 5
IX 78 4
SP1 9E68 ff 6
DIR 37 dd 5
INH 47 1
C INH 57 1
IX1
b7 b0 67 ff 5
IX 77 4
SP1 9E67 ff 6
Branch if (C) = 0 REL 24 rr 3
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Table 7-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
Source Operation Description Effect Address
Form on CCR Mode
BCLR n,opr8a VH I NZC Opcode
Operand
BCS rel Bus Cycles1
BEQ rel
DIR (b0) 11 dd 5
BGE rel
DIR (b1) 13 dd 5
BGND
DIR (b2) 15 dd 5
BGT rel
BHCC rel Clear Bit n in Memory Mn 0 DIR (b3) 17 dd 5
BHCS rel
BHI rel DIR (b4) 19 dd 5
BHS rel
BIH rel DIR (b5) 1B dd 5
BIL rel
BIT #opr8i DIR (b6) 1D dd 5
BIT opr8a
BIT opr16a DIR (b7) 1F dd 5
BIT oprx16,X
BIT oprx8,X Branch if Carry Bit Set Branch if (C) = 1 REL 25 rr 3
BIT ,X (Same as BLO)
BIT oprx16,SP
BIT oprx8,SP Branch if Equal Branch if (Z) = 1 REL 27 rr 3
BLE rel
Branch if Greater Than or Branch if (N V) = 0 90 rr 3
BLO rel Equal To REL
BLS rel (Signed Operands)
BLT rel
BMC rel Enter Active Background Waits For and Processes BDM
BMI rel if ENBDM = 1 Commands Until GO, TRACE1, or INH 82 5+
BMS rel
BNE rel TAGGO
BPL rel
BRA rel Branch if Greater Than Branch if (Z) | (N V) = 0 REL 92 rr 3
(Signed Operands)
Branch if Half Carry Bit Branch if (H) = 0 REL 28 rr 3
Clear
Branch if Half Carry Bit Branch if (H) = 1 REL 29 rr 3
Set
Branch if Higher Branch if (C) | (Z) = 0 REL 22 rr 3
Branch if Higher or Same Branch if (C) = 0 REL 24 rr 3
(Same as BCC)
Branch if IRQ Pin High Branch if IRQ pin = 1 REL 2F rr 3
Branch if IRQ Pin Low Branch if IRQ pin = 0 REL 2E rr 3
0 IMM A5 ii 2
DIR B5 dd 3
(A) & (M) EXT C5 hh ll 4
(CCR Updated but Operands
Bit Test IX2 D5 ee ff 4
Not Changed) IX1
E5 ff 3
IX F5 3
SP2 9ED5 ee ff 5
SP1 9EE5 ff 4
Branch if Less Than Branch if (Z) | (N V) = 1 93 rr 3
or Equal To REL
(Signed Operands)
Branch if Lower Branch if (C) = 1 REL 25 rr 3
(Same as BCS)
Branch if Lower or Same Branch if (C) | (Z) = 1 REL 23 rr 3
Branch if Less Than Branch if (N V ) = 1 REL 91 rr 3
(Signed Operands)
Branch if Interrupt Mask Branch if (I) = 0 REL 2C rr 3
Clear
Branch if Minus Branch if (N) = 1 REL 2B rr 3
Branch if Interrupt Mask Branch if (I) = 1 REL 2D rr 3
Set
Branch if Not Equal Branch if (Z) = 0 REL 26 rr 3
Branch if Plus Branch if (N) = 0 REL 2A rr 3
Branch Always No Test REL 20 rr 3
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
98 Freescale Semiconductor
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
Source Operation Description Effect Address
Form on CCR Mode
VH I NZC Opcode
Operand
Bus Cycles1
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
BRCLR n,opr8a,rel Branch if Bit n in Memory Branch if (Mn) = 0 DIR (b2) 05 dd rr 5
Clear DIR (b3) 07 dd rr 5
DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never Uses 3 Bus Cycles REL 21 rr 3
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
BRSET n,opr8a,rel Branch if Bit n in Memory Branch if (Mn) = 1 DIR (b2) 04 dd rr 5
Set DIR (b3) 06 dd rr 5
DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
BSET n,opr8a Set Bit n in Memory Mn 1 DIR (b3) 16 dd 5
DIR (b4) 18 dd 5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
BSR rel Branch to Subroutine PC (PC) + 0x0002 AD rr 5
push (PCL); SP (SP) 0x0001 REL
push (PCH); SP (SP) 0x0001
PC (PC) + rel
CBEQ opr8a,rel Branch if (A) = (M) DIR 31 dd rr 5
CBEQA #opr8i,rel Branch if (A) = (M) IMM
CBEQX #opr8i,rel Branch if (X) = (M) IMM 41 ii rr 4
CBEQ oprx8,X+,rel Branch if (A) = (M) IX1+
CBEQ ,X+,rel Compare and Branch if Branch if (A) = (M) IX+ 51 ii rr 4
CBEQ oprx8,SP,rel Equal Branch if (A) = (M) SP1
61 ff rr 5
71 rr 5
9E61 ff rr 6
CLC Clear Carry Bit C0 0 INH 98 1
CLI Clear Interrupt Mask Bit I0 0 INH 9A 1
CLR opr8a M 0x00 0 0 1 DIR 3F dd 5
CLRA A 0x00 INH
CLRX X 0x00 INH 4F 1
CLRH H 0x00 INH
CLR oprx8,X M 0x00 IX1 5F 1
CLR ,X M 0x00 IX
CLR oprx8,SP Clear M 0x00 SP1 8C 1
6F ff 5
7F 4
9E6F ff 6
CMP #opr8i IMM A1 ii 2
CMP opr8a
CMP opr16a DIR B1 dd 3
CMP oprx16,X
CMP oprx8,X (A) (M) EXT C1 hh ll 4
CMP ,X (CCR Updated But Operands Not
CMP oprx16,SP Compare Accumulator IX2 D1 ee ff 4
CMP oprx8,SP with Memory Changed)
IX1 E1 ff 3
IX F1 3
SP2 9ED1 ee ff 5
SP1 9EE1 ff 4
COM opr8a M (M)= 0xFF (M) 0 1 DIR 33 dd 5
COMA A (A) = 0xFF (A) INH
COMX X (X) = 0xFF (X) INH 43 1
COM oprx8,X M (M) = 0xFF (M) IX1
COM ,X Complement M (M) = 0xFF (M) IX 53 1
COM oprx8,SP (One's Complement) M (M) = 0xFF (M) SP1
63 ff 5
73 4
9E63 ff 6
CPHX opr16a (H:X) (M:M + 0x0001) EXT 3E hh ll 6
CPHX #opr16i (CCR Updated But Operands Not
CPHX opr8a Compare Index Register IMM 65 jj kk 3
CPHX oprx8,SP (H:X) with Memory Changed)
DIR 75 dd 5
SP1 9EF3 ff 6
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 99
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-2. HCS08 Instruction Set Summary (Sheet 4 of 7)
Source Operation Description Effect Address
Form on CCR Mode
VH I NZC Opcode
Operand
Bus Cycles1
CPX #opr8i IMM A3 ii 2
CPX opr8a
CPX opr16a DIR B3 dd 3
CPX oprx16,X
CPX oprx8,X Compare X (Index (X) (M) EXT C3 hh ll 4
CPX ,X Register Low) with (CCR Updated But Operands Not
CPX oprx16,SP Memory IX2 D3 ee ff 4
CPX oprx8,SP Changed)
Decimal Adjust IX1 E3 ff 3
DAA Accumulator After ADD or (A)10
ADC of BCD Values Decrement A, X, or M IX F3 3
DBNZ opr8a,rel Decrement and Branch if Branch if (result) 0
DBNZA rel Not Zero DBNZX Affects X Not H SP2 9ED3 ee ff 5
DBNZX rel
DBNZ oprx8,X,rel Decrement M (M) 0x01 SP1 9EE3 ff 4
DBNZ ,X,rel A (A) 0x01
DBNZ oprx8,SP,rel Divide X (X) 0x01 U 72 1
M (M) 0x01 INH
DEC opr8a Exclusive OR M (M) 0x01
DECA Memory with M (M) 0x01 DIR 3B dd rr 7
DECX Accumulator A (H:A)(X) INH
DEC oprx8,X H Remainder INH 4B rr 4
DEC ,X Increment IX1
DEC oprx8,SP A (A M) IX 5B rr 4
Jump SP1
DIV M (M) + 0x01 6B ff rr 7
Jump to Subroutine A (A) + 0x01
EOR #opr8i X (X) + 0x01 7B rr 6
EOR opr8a Load Accumulator from M (M) + 0x01
EOR opr16a Memory M (M) + 0x01 9E6B ff rr 8
EOR oprx16,X M (M) + 0x01
EOR oprx8,X Load Index Register (H:X) PC Jump Address DIR 3A dd 5
EOR ,X from Memory
EOR oprx16,SP PC (PC) + n (n = 1, 2, or 3) INH 4A 1
EOR oprx8,SP Push (PCL); SP (SP) 0x0001
Push (PCH); SP (SP) 0x0001 INH 5A 1
INC opr8a IX1
INCA PC Unconditional Address 6A ff 5
INCX
INC oprx8,X A (M) IX 7A 4
INC ,X
INC oprx8,SP H:X (M:M + 0x0001) SP1 9E6A ff 6
JMP opr8a INH 52 6
JMP opr16a
JMP oprx16,X 0 IMM A8 ii 2
JMP oprx8,X DIR
JMP ,X EXT B8 dd 3
IX2
JSR opr8a IX1 C8 hh ll 4
JSR opr16a IX
JSR oprx16,X SP2 D8 ee ff 4
JSR oprx8,X SP1
JSR ,X E8 ff 3
LDA #opr8i F8 3
LDA opr8a
LDA opr16a 9ED8 ee ff 5
LDA oprx16,X
LDA oprx8,X 9EE8 ff 4
LDA ,X
LDA oprx16,SP DIR 3C dd 5
LDA oprx8,SP INH
INH 4C 1
LDHX #opr16i IX1
LDHX opr8a IX 5C 1
LDHX opr16a SP1
LDHX ,X 6C ff 5
LDHX oprx16,X
LDHX oprx8,X 7C 4
LDHX oprx8,SP
9E6C ff 6
DIR BC dd 3
EXT
IX2 CC hh ll 4
IX1
IX DC ee ff 4
EC ff 3
FC 3
DIR BD dd 5
EXT
IX2 CD hh ll 6
IX1
IX DD ee ff 6
ED ff 5
FD 5
0 IMM A6 ii 2
DIR
EXT B6 dd 3
IX2
IX1 C6 hh ll 4
IX
SP2 D6 ee ff 4
SP1
E6 ff 3
F6 3
9ED6 ee ff 5
9EE6 ff 4
0 IMM 45 jj kk 3
DIR
EXT 55 dd 4
IX
IX2 32 hh ll 5
IX1
SP1 9EAE 5
9EBE ee ff 6
9ECE ff 5
9EFE ff 5
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
100 Freescale Semiconductor
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
Source Operation Description Effect Address
Form on CCR Mode
VH I NZC Opcode
Operand
Bus Cycles1
LDX #opr8i 0 IMM AE ii 2
LDX opr8a DIR
LDX opr16a EXT BE dd 3
LDX oprx16,X IX2
LDX oprx8,X IX1 CE hh ll 4
LDX ,X IX
LDX oprx16,SP Load X (Index Register X (M) SP2 DE ee ff 4
LDX oprx8,SP Low) from Memory SP1
EE ff 3
LSL opr8a Logical Shift Left
LSLA (Same as ASL) FE 3
LSLX
LSL oprx8,X Logical Shift Right 9EDE ee ff 5
LSL ,X
LSL oprx8,SP Move 9EEE ff 4
LSR opr8a Unsigned multiply DIR 38 dd 5
LSRA
LSRX Negate INH 48 1
LSR oprx8,X (Two's Complement)
LSR ,X C 0 INH 58 1
LSR oprx8,SP No Operation b7 b0
Nibble Swap IX1 68 ff 5
MOV opr8a,opr8a Accumulator
MOV opr8a,X+ IX 78 4
MOV #opr8i,opr8a Inclusive OR Accumulator
MOV ,X+,opr8a and Memory SP1 9E68 ff 6
MUL Push Accumulator onto 0 DIR 34 dd 5
Stack
NEG opr8a Push H (Index Register INH 44 1
NEGA High) onto Stack
NEGX Push X (Index Register 0 C INH 54 1
NEG oprx8,X Low) onto Stack b7 b0
NEG ,X Pull Accumulator from IX1 64 ff 5
NEG oprx8,SP Stack
Pull H (Index Register IX 74 4
NOP High) from Stack
Pull X (Index Register SP1 9E64 ff 6
NSA Low) from Stack
(M)destination (M)source 0 DIR/DIR 4E dd dd 5
ORA #opr8i Rotate Left through Carry DIR/IX+
ORA opr8a H:X (H:X) + 0x0001 in IMM/DIR 5E dd 5
ORA opr16a IX+/DIR and DIR/IX+ Modes IX+/DIR
ORA oprx16,X 6E ii dd 4
ORA oprx8,X X:A (X) (A)
ORA ,X M (M) = 0x00 (M) 7E dd 5
ORA oprx16,SP A (A) = 0x00 (A)
ORA oprx8,SP X (X) = 0x00 (X) 0 0 INH 42 5
M (M) = 0x00 (M)
PSHA M (M) = 0x00 (M) DIR 30 dd 5
M (M) = 0x00 (M)
PSHH INH 40 1
Uses 1 Bus Cycle
PSHX INH 50 1
A (A[3:0]:A[7:4])
PULA IX1 60 ff 5
PULH IX 70 4
PULX SP1 9E60 ff 6
ROL opr8a INH 9D 1
ROLA
ROLX INH 62 1
ROL oprx8,X
ROL ,X 0 IMM AA ii 2
ROL oprx8,SP DIR
EXT BA dd 3
IX2
IX1 CA hh ll 4
IX
A (A) | (M) SP2 DA ee ff 4
SP1
EA ff 3
FA 3
9EDA ee ff 5
9EEA ff 4
Push (A); SP (SP) 0x0001 INH 87 2
Push (H); SP (SP) 0x0001
Push (X); SP (SP) 0x0001 INH 8B 2
SP (SP + 0x0001); Pull (A)
SP (SP + 0x0001); Pull (H) INH 89 2
SP (SP + 0x0001); Pull (X)
INH 86 3
INH 8A 3
INH 88 3
DIR 39 dd 5
INH 49 1
C INH 59 1
b7 b0 IX1 69 ff 5
IX 79 4
SP1 9E69 ff 6
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 101
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-2. HCS08 Instruction Set Summary (Sheet 6 of 7)
Source Operation Description Effect Address
Form on CCR Mode
ROR opr8a VH I NZC Opcode
RORA Operand
RORX Bus Cycles1
ROR oprx8,X
ROR ,X DIR 36 dd 5
ROR oprx8,SP
INH 46 1
RSP
Rotate Right through C INH 56 1
RTI Carry
b7 b0 IX1 66 ff 5
RTS Reset Stack Pointer
IX 76 4
SBC #opr8i Return from Interrupt
SBC opr8a SP1 9E66 ff 6
SBC opr16a Return from Subroutine
SBC oprx16,X SP 0xFF INH 9C 1
SBC oprx8,X Subtract with Carry (High Byte Not Affected)
SBC ,X INH 80 9
SBC oprx16,SP Set Carry Bit SP (SP) + 0x0001; Pull (CCR)
SBC oprx8,SP Set Interrupt Mask Bit SP (SP) + 0x0001; Pull (A) INH 81 6
SEC SP (SP) + 0x0001; Pull (X)
Store Accumulator in
SEI Memory SP (SP) + 0x0001; Pull (PCH)
STA opr8a SP (SP) + 0x0001; Pull (PCL)
STA opr16a Store H:X (Index Reg.)
STA oprx16,X Enable Interrupts: SP SP + 0x0001; Pull (PCH)
STA oprx8,X Stop Processing SP SP + 0x0001; Pull (PCL)
STA ,X Refer to MCU
STA oprx16,SP Documentation IMM A2 ii 2
STA oprx8,SP Store X (Low 8 Bits of
STHX opr8a Index Register) DIR B2 dd 3
STHX opr16a in Memory
STHX oprx8,SP EXT C2 hh ll 4
Subtract
STOP A (A) (M) (C) IX2 D2 ee ff 4
Software Interrupt
STX opr8a IX1 E2 ff 3
STX opr16a
STX oprx16,X IX F2 3
STX oprx8,X
STX ,X SP2 9ED2 ee ff 5
STX oprx16,SP
STX oprx8,SP SP1 9EE2 ff 4
SUB #opr8i
SUB opr8a C1 1 INH 99 1
SUB opr16a I1
SUB oprx16,X 1 INH 9B 1
SUB oprx8,X M (A)
SUB ,X 0 DIR B7 dd 3
SUB oprx16,SP EXT
SUB oprx8,SP IX2 C7 hh ll 4
IX1
SWI IX D7 ee ff 4
SP2
SP1 E7 ff 3
F7 2
9ED7 ee ff 5
9EE7 ff 4
0 DIR 35 dd 4
EXT
(M:M + 0x0001) (H:X) SP1 96 hh ll 5
I bit 0; Stop Processing
9EFF ff 5
0
INH 8E 2+
0 DIR BF dd 3
EXT
IX2 CF hh ll 4
IX1
IX DF ee ff 4
SP2
M (X) SP1 EF ff 3
A (A) (M) FF 2
PC (PC) + 0x0001
Push (PCL); SP (SP) 0x0001 9EDF ee ff 5
Push (PCH); SP (SP) 0x0001
Push (X); SP (SP) 0x0001 9EEF ff 4
Push (A); SP (SP) 0x0001
Push (CCR); SP (SP) 0x0001 IMM A0 ii 2
I 1; DIR B0 dd 3
PCH Interrupt Vector High Byte
PCL Interrupt Vector Low Byte EXT C0 hh ll 4
IX2 D0 ee ff 4
IX1 E0 ff 3
IX F0 3
SP2 9ED0 ee ff 5
SP1 9EE0 ff 4
1
INH 83 11
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
102 Freescale Semiconductor
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-2. HCS08 Instruction Set Summary (Sheet 7 of 7)
Source Operation Description Effect Address
Form on CCR Mode
VH I NZC Opcode
Operand
Bus Cycles1
TAP Transfer Accumulator to CCR (A) INH 84 1
CCR
TAX Transfer Accumulator to X (A) INH 97 1
X (Index Register Low)
TPA Transfer CCR to A (CCR) INH 85 1
Accumulator
TST opr8a (M) 0x00 0 DIR 3D dd 4
TSTA Test for Negative or Zero (A) 0x00 INH
TSTX (X) 0x00 INH 4D 1
TST oprx8,X Transfer SP to Index Reg. (M) 0x00 IX1
TST ,X Transfer X (Index Reg. (M) 0x00 IX 5D 1
TST oprx8,SP Low) to Accumulator (M) 0x00 SP1
TSX Transfer Index Reg. to SP H:X (SP) + 0x0001 6D ff 4
Enable Interrupts; Wait
TXA for Interrupt A (X) 7D 3
TXS SP (H:X) 0x0001 9E6D ff 5
WAIT I bit 0; Halt CPU INH 95 2
INH 9F 1
INH 94 2
0 INH
8F 2+
1 Bus clock frequency is one-half of the CPU clock frequency.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 103
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-3. Opcode Map (Sheet 1 of 2)
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
00 5 10 5 20 3 30 5 40 1 50 1 60 5 70 4 80 9 90 3 A0 2 B0 3 C0 4 D0 4 E0 3 F0 3
SUB SUB
BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG RTI BGE SUB SUB SUB SUB
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 2 IX1 1 IX
01 5 11 5 21 3 31 5 41 4 51 4 61 5 71 5 81 6 91 3 A1 2 B1 3 C1 4 D1 4 E1 3 F1 3
CMP CMP
BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ RTS BLT CMP CMP CMP CMP
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 2 IX1 1 IX
02 5 12 5 22 3 32 5 42 5 52 6 62 1 72 1 82 5+ 92 3 A2 2 B2 3 C2 4 D2 4 E2 3 F2 3
SBC SBC
BRSET1 BSET1 BHI LDHX MUL DIV NSA DAA BGND BGT SBC SBC SBC SBC
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 3 EXT 1 INH 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 2 IX1 1 IX
03 5 13 5 23 3 33 5 43 1 53 1 63 5 73 4 83 11 93 3 A3 2 B3 3 C3 4 D3 4 E3 3 F3 3
CPX CPX
BRCLR1 BCLR1 BLS COM COMA COMX COM COM SWI BLE CPX CPX CPX CPX
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 REL 2 IMM 2 DIR 2 IX1 1 IX
04 5 14 5 24 3 34 5 44 1 54 1 64 5 74 4 84 1 94 2 A4 2 B4 3 C4 4 D4 4 E4 3 F4 3
AND AND
BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 2 IX1 1 IX
05 5 15 5 25 3 35 4 45 3 55 4 65 3 75 5 85 1 95 2 A5 2 B5 3 C5 4 D5 4 E5 3 F5 3
BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
06 5 16 5 26 3 36 5 46 1 56 1 66 5 76 4 86 3 96 5 A6 2 B6 3 C6 4 D6 4 E6 3 F6 3
BRSET3 BSET3 BNE ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 3 EXT 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 A7 2 B7 3 C7 4 D7 4 E7 3 F7 2
BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
08 5 18 5 28 3 38 5 48 1 58 1 68 5 78 4 88 3 98 1 A8 2 B8 3 C8 4 D8 4 E8 3 F8 3
EOR EOR
BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 2 IX1 1 IX
09 5 19 5 29 3 39 5 49 1 59 1 69 5 79 4 89 2 99 1 A9 2 B9 3 C9 4 D9 4 E9 3 F9 3
ADC ADC
BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC
3 EXT 3 IX2
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 IMM 2 DIR 2 IX1 1 IX
0A 5 1A 5 2A 3 3A 5 4A 1 5A 1 6A 5 7A 4 8A 3 9A 1 AA 2 BA 3 CA 4 DA 4 EA 3 FA 3
ORA ORA ORA ORA ORA
BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 1 IX
0B 5 1B 5 2B 3 3B 7 4B 4 5B 4 6B 7 7B 6 8B 2 9B 1 AB 2 BB 3 CB 4 DB 4 EB 3 FB 3
ADD ADD ADD ADD ADD
BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD
2 IMM 2 DIR 3 EXT 3 IX2 2 IX1
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 2 IX 1 INH 1 INH 1 IX
0C 5 1C 5 2C 3 3C 5 4C 1 5C 1 6C 5 7C 4 8C 1 9C 1 BC 3 CC 4 DC 4 EC 3 FC 3
BRSET6 BSET6 BMC INC CLRH RSP JMP JMP
3 DIR 2 DIR INCA INCX INC INC JMP JMP JMP
2 REL 2 DIR 1 INH 1 INH 2 DIR 2 IX1
1 INH 1 INH 2 IX1 1 IX 3 EXT 3 IX2 1 IX
0D 5 1D 5 2D 3 3D 4 4D 1 5D 1 6D 4 7D 3 9D 1 AD 5 BD 5 CD 6 DD 6 ED 5 FD 5
BRCLR6 BCLR6 BMS TST TSTA TSTX TST NOP BSR JSR JSR
3 DIR 2 DIR TST JSR JSR JSR
2 REL 2 DIR 1 INH 1 INH 2 IX1 1 INH 2 REL 2 DIR 2 IX1
1 IX 3 EXT 3 IX2 1 IX
AE 2
0E 5 1E 5 2E 3 3E 6 4E 5 5E 5 6E 4 7E 5 8E 2+ 9E LDX BE 3 CE 4 DE 4 EE 3 FE 3
STOP Page 2 LDX LDX
BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV 2 IMM LDX LDX LDX
1 INH 2 DIR 2 IX1
3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 DIX+ 3 IMD 2 IX+D AF 2 3 EXT 3 IX2 1 IX
AIX
0F 5 1F 5 2F 3 3F 5 4F 1 5F 1 6F 5 7F 4 8F 2+ 9F 1 BF 3 CF 4 DF 4 EF 3 FF 2
2 IMM STX STX
BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX STX STX
2 DIR 2 IX1
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 3 EXT 3 IX2 1 IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment
Opcode in
Hexadecimal F0 3 HCS08 Cycles
SUB Instruction Mnemonic
IX Addressing Mode
Number of Bytes 1
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
104 Freescale Semiconductor
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
Table 7-3. Opcode Map (Sheet 2 of 2)
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
9E60 6
NEG 9ED0 5 9EE0 4 9EF3 6
3 SP1 SUB SUB CPHX
9E61 6
CBEQ 4 SP2 3 SP1 3 SP1
4 SP1
9ED1 5 9EE1 4
9E63 6 CMP CMP
COM
4 SP2 3 SP1
3 SP1
9E64 6 9ED2 5 9EE2 4
SBC SBC
LSR
3 SP1 4 SP2 3 SP1
9E66 6 9ED3 5 9EE3 4
ROR CPX CPX
3 SP1 4 SP2 3 SP1
9E67 6
9ED4 5 9EE4 4
ASR AND AND
3 SP1
9E68 6 4 SP2 3 SP1
LSL 9ED5 5 9EE5 4
3 SP1 BIT BIT
9E69 6
4 SP2 3 SP1
ROL
3 SP1 9ED6 5 9EE6 4
9E6A 6 LDA LDA
DEC 4 SP2 3 SP1
3 SP1
9E6B 8 9ED7 5 9EE7 4
STA STA
DBNZ
4 SP1 4 SP2 3 SP1
9E6C 6
9ED8 5 9EE8 4
INC EOR EOR
3 SP1
9E6D 5 4 SP2 3 SP1
TST 9ED9 5 9EE9 4
3 SP1 ADC ADC
9E6F 6 4 SP2 3 SP1
CLR
9EDA 5 9EEA 4
3 SP1 ORA ORA
4 SP2 3 SP1
9EDB 5 9EEB 4
ADD ADD
4 SP2 3 SP1
9EAE 5 9EBE 6 9ECE 5 9EDE 5 9EEE 4 9EFE 5
LDHX LDHX LDX LDX LDHX
LDHX
4 IX2 3 IX1 4 SP2 3 SP1 3 SP1
2 IX
9EDF 5 9EEF 4 9EFF 5
STX STX STHX
4 SP2 3 SP1 3 SP1
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in
Hexadecimal 9E60 6 HCS08 Cycles
NEG Instruction Mnemonic
Number of Bytes 3 SP1 Addressing Mode
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 105
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
106 Freescale Semiconductor
Chapter 8
Carrier Modulator Timer (S08CMTV1)
8.1 Introduction INTERNAL BUS
HCS08 CORE DEBUG
MODULE (DBG)
BDC CPU PORT A 7 NOTES1, 2, 6
PTA7/KBI1P7
PTA1/KBI1P1
PTA0/KBI1P0
HCS08 SYSTEM CONTROL 8-BIT KEYBOARD PORT B PTB7/TPM1CH1 NOTES 1, 5
INTERRUPT MODULE (KBI1)
RESETS AND INTERRUPTS PTE6
MODES OF OPERATION 4-BIT KEYBOARD PTB5
POWER MANAGEMENT INTERRUPT MODULE (KBI2) PTB4
PTB3
RTI COP SERIAL COMMUNICATIONS PTB2
INTERFACE MODULE (SCI1) PTB1/RxD1
PTB0/TxD1
ANALOG COMPARATOR
IRQ LVD MODULE (ACMP1)
USER FLASH PORT C PTC7/SS1 NOTE 1
PTC6/SPSCK1
(RC/RD/RE/RG60 = 63,364 BYTES) PTC5/MISO1
(RC/RD/RE/RG32 = 32,768 BYTES) PTC4/MOSI1
PTC3/KBI2P3
(RC/RD/RE16 = 16,384 BYTES) PTC2/KBI2P2
(RC/RD/RE8 = 8192 BYTES) PTC1/KBI2P1
PTC0/KBI2P0
USER RAM 2-CHANNEL TIMER/PWM PORT D PTD6/TPM1CH0 NOTES
MODULE (TPM1) PTD5/ACMP1+ 1, 3, 4
(RC/RD/RE/RG32/60 = 2048 BYTES) PTD4/ACMP1
(RC/RD/RE8/16 = 1024 BYTES) SERIAL PERIPHERAL PTD3
INTERFACE MODULE (SPI1) PTD2/IRQ
EXTAL LOW-POWER OSCILLATOR PTD1/RESET
XTAL PTD0/BKGD/MS
VDD VOLTAGE PORT E 8
PTE7PTE0 NOTE 1
VSS REGULATOR CARRIER MODULATOR
TIMER MODULE (CMT)
IRO NOTE 5
NOTES:
1. Port pins are software configurable with pullup device if input port
2. PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Also, PTA0 does not pullup to VDD when internal
pullup is enabled.
3. IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1)
4. The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1)
5. High current drive
6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is
selected (KBEDGn = 1).
Figure 8-1. MC9S08RC/RD/RE/RG Block Diagram
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 107
Carrier Modulator Transmitter (CMT) Block Description
8.2 Features
The CMT consists of a carrier generator, modulator, and transmitter that drives the infrared out (IRO) pin.
The features of this module include:
Four modes of operation
-- Time with independent control of high and low times
-- Baseband
-- Frequency shift key (FSK)
-- Direct software control of IRO pin
Extended space operation in time, baseband, and FSK modes
Selectable input clock divide: 1, 2, 4, or 8
Interrupt on end of cycle
-- Ability to disable IRO pin and use as timer interrupt
8.3 CMT Block Diagram
PRIMARY/SECONDARY SELECT
MODULATOR
CLOCK CMTCLK CARRIER CARRIER MODULATOR OUT IRO
CONTROL GENERATOR OUT (fCG) TRANSMITTER PIN
OUTPUT
CMTDIV IROL
IROPEN
CMTPOL
MCGEN
CMTCMD REGS
MIREQ
EOC INT EN
EOC FLAG
EXSPC
BASE
FSK
CMTCG REGS
CMT REGISTERS
AND BUS INTERFACE
BUS CLOCK
INTERNAL BUS IIREQ
Figure 8-2. Carrier Modulator Transmitter Module Block Diagram
8.4 Pin Description
The IRO pin is the only pin associated with the CMT. The pin is driven by the transmitter output when the
MCGEN bit in the CMTMSC register and the IROPEN bit in the CMTOC register are set. If the MCGEN
bit is clear and the IROPEN bit is set, the pin is driven by the IROL bit in the CMTOC register. This enables
user software to directly control the state of the IRO pin by writing to the IROL bit. If the IROPEN bit is
clear, the pin is disabled and is not driven by the CMT module. This is so the CMT can be configured as a
modulo timer for generating periodic interrupts without causing pin activity.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
108 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
8.5 Functional Description
The CMT module consists of a carrier generator, a modulator, a transmitter output, and control registers.
The block diagram is shown in Figure 8-2. When operating in time mode, the user independently defines
the high and low times of the carrier signal to determine both period and duty cycle. The carrier generator
resolution is 125 ns when operating with an 8 MHz internal bus frequency and the CMTDIV1 and
CMTDIV0 bits in the CMTMSC register are both equal to 0. The carrier generator can generate signals
with periods between 250 ns (4 MHz) and 127.5 s (7.84 kHz) in steps of 125 ns. See Table 8-1.
Table 8-1. Clock Divide
Bus CMTDIV1:CMTDIV0 Carrier Min Carrier Min
Clock Generator Generator Modulator
(MHz) 0:0 Resolution
0:1 Period Period
8 1:0 (s) (s) (s)
1:1
8 0.125 0.25 1.0
8 0.25 0.5 2.0
8 0.5 1.0 4.0
1.0 2.0 8.0
The possible duty cycle options will depend upon the number of counts required to complete the carrier
period. For example, a 1.6 MHz signal has a period of 625 ns and will therefore require 5 125 ns counts
to generate. These counts may be split between high and low times, so the duty cycles available will be
20 percent (one high, four low), 40 percent (two high, three low), 60 percent (three high, two low) and
80 percent (four high, one low).
For lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty
cycles are possible.
When the BASE bit in the CMT modulator status and control register (CMTMSC) is set, the carrier output
(fCG) to the modulator is held high continuously to allow for the generation of baseband protocols.
A third mode allows the carrier generator to alternate between two sets of high and low times. When
operating in FSK mode, the generator will toggle between the two sets when instructed by the modulator,
allowing the user to dynamically switch between two carrier frequencies without CPU intervention.
The modulator provides a simple method to control protocol timing. The modulator has a minimum
resolution of 1.0 s with an 8 MHz internal bus clock. It can count bus clocks (to provide real-time control)
or it can count carrier clocks (for self-clocked protocols). See Section 8.5.2, "Modulator," for more details.
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
on to the IRO pin when the modulator/carrier generator is enabled.
A summary of the possible modes is shown in Table 8-2.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 109
Carrier Modulator Transmitter (CMT) Block Description
Table 8-2. CMT Modes of Operation
Mode MCGEN BASE FSK EXSPC Comment
Bit(2) Bit
Bit(1) Bit(2)
Time 1 0 0 0 fCG controlled by primary high and low registers.
fCG transmitted to IRO pin when modulator gate is open.
Baseband 1 1 x 0 fCG is always high. IRO pin high when modulator gate is open.
fCG control alternates between primary high/low registers and
FSK 1 0 1 0 secondary high/low registers.
fCG transmitted to IRO pin when modulator gate is open.
Extended Setting the EXSPC bit causes subsequent modulator cycles
Space
1 x x 1 to be spaces (modulator out not asserted) for the duration of
the modulator period (mark and space times).
IRO Latch 0 x x x IROL bit controls state of IRO pin.
1. To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1).
2. These bits are not double buffered and should not be changed during a transmission (while MCGEN=1).
8.5.1 Carrier Generator
The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz
bus) for both the carrier high time and the carrier low time. The period is determined by the total number
of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted.
The high and low time values are user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the generation of dual
frequency FSK (frequency shift keying) protocols without CPU intervention.
NOTE
Only non-zero data values are allowed. The carrier generator will not work
if any of the count values are equal to zero.
The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier
generator clocks. When the BASE bit is set, the carrier output to the modulator is held high continuously.
The block diagram is shown in Figure 8-3.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
110 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
CMTCGH2
CMTCGH1
=?
CMTCLK CLOCK AND OUTPUT CONTROL CLK 8-BIT UP COUNTER PRIMARY/
BASE CLR SECONDARY
FSK SELECT
MCGEN
CARRIER OUT (fCG) =?
CMTCGL1
CMTCGL2
Figure 8-3. Carrier Generator Block Diagram
The high/low time counter is an 8-bit up counter. After each increment, the contents of the counter are
compared with the appropriate high or low count value register. When the compare value is reached, the
counter is reset to a value of $01, and the compare is redirected to the other count value register.
Assuming that the high time count compare register is currently active, a valid compare will cause the
carrier output to be driven low. The counter will continue to increment (starting at reset value of $01).
When the value stored in the selected low count value register is reached, the counter will again be reset
and the carrier output will be driven high.
The cycle repeats, automatically generating a periodic signal that is directed to the modulator. The lowest
frequency (maximum period) and highest frequency (minimum period) that can be generated are defined
as:
fmax = fCMTCLK (2 x 1) Hz Eqn. 8-1
fmin = fCMTCLK (2 x (28 1)) Hz Eqn. 8-2
In the general case, the carrier generator output frequency is:
fCG = fCMTCLK (Highcount + Lowcount) Hz Eqn. 8-3
Where: 0 < Highcount < 256 and
0 < Lowcount < 256
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 111
Carrier Modulator Transmitter (CMT) Block Description
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As
the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts
required to generate the desired carrier period.
Duty Cycle = H-----i--g----h----c----oH----u-i--g-n---h-t---c-+---o--L--u--o--n--w--t---c---o----u----n----t- Eqn. 8-4
8.5.2 Modulator
The modulator has three main modes of operation:
Gate the carrier onto the modulator output (time mode)
Control the logic level of the modulator output (baseband mode)
Count carrier periods and instruct the carrier generator to alternate between two carrier frequencies
whenever a modulation period (mark + space counts) expires (FSK mode)
The modulator includes a 17-bit down counter with underflow detection. The counter is loaded from the
16-bit modulation mark period buffer registers, CMTCMD1 and CMTCMD2. The most significant bit is
loaded with a logic zero and serves as a sign bit. When the counter holds a positive value, the modulator
gate is open and the carrier signal is driven to the transmitter block.
When the counter underflows, the modulator gate is closed and a 16-bit comparator is enabled that
compares the logical complement of the value of the down-counter with the contents of the modulation
space period register (which has been loaded from the registers CMTCMD3 and CMTCMD4).
When a match is obtained the cycle repeats by opening the modulator gate, reloading the counter with the
contents of CMTCMD1 and CMTCMD2, and reloading the modulation space period register with the
contents of CMTCMD3 and CMTCMD4.
If the contents of the modulation space period register are all zeroes, the match will be immediate and no
space period will be generated (for instance, for FSK protocols that require successive bursts of different
frequencies).
The MCGEN bit in the CMTMSC register must be set to enable the modulator timer.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
112 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
16 BITS
MODE
0 CMTCMD1:CMTCMD2
8 CMTCLOCK
CLOCK CONTROL
17-BIT DOWN COUNTER * . CARRIER OUT (fCG)
16
MS BIT
COUNTER LOAD . MODULATOR GATE MODULATOR
OUT
=? EOC FLAG SET
SYSTEM CONTROL MODULE INTERRUPT REQUEST
PRIMARY/SECONDARY SELECT
16 EOCIE
SPACE PERIOD REGISTER * EXSPC
BASE
FSK
CMTCMD3:CMTCMD4
16 BITS
* DENOTES HIDDEN REGISTER
Figure 8-4. Modulator Block Diagram
8.5.2.1 Time Mode
When the modulator operates in time mode (MCGEN bit is set, BASE bit is clear, and FSK bit is clear),
the modulation mark period consists of an integer number of CMTCLK 8 clock periods. The modulation
space period consists of zero or an integer number of CMTCLK 8 clock periods. With an 8 MHz bus and
CMTDIV1:CMTDIV0 = 00, the modulator resolution is 1 s and has a maximum mark and space period
of about 65.535 ms each. See Figure 8-5 for an example of the time mode and baseband mode outputs.
The mark and space time equations for time and baseband mode are:
tmark = (CMTCMD1:CMTCMD2 + 1) (fCMTCLK 8) Eqn. 8-5
tspace = CMTCMD3:CMTCMD4 (fCMTCLK 8) Eqn. 8-6
where CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated
registers.
NOTE
If the modulator is disabled while the tmark time is less than the programmed
carrier high time (tmark < CMTCGH1/fCMTCLK), the modulator can enter
into an illegal state and end the curent cycle before the programmed value.
Make sure to program tmark greater than the carrier high time to avoid this
illegal state.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 113
Carrier Modulator Transmitter (CMT) Block Description
CMTCLK 8 MARK SPACE MARK
CARRIER OUT(fCG)
MODULATOR GATE
IRO PIN (TIME MODE)
IRO PIN
(BASEBAND MODE)
Figure 8-5. Example CMT Output in Time and Baseband Modes
8.5.2.2 Baseband Mode
Baseband mode (MCGEN bit is set and BASE bit is set) is a derivative of time mode, where the mark and
space period is based on (CMTCLK 8) counts. The mark and space calculations are the same as in time
mode. In this mode the modulator output will be at a logic 1 for the duration of the mark period and at a
logic 0 for the duration of a space period. See Figure 8-5 for an example of the output for both baseband
and time modes. In the example, the carrier out frequency (fCG) is generated with a high count of $01 and
a low count of $02, which results in a divide of 3 of CMTCLK with a 33 percent duty cycle. The modulator
down-counter was loaded with the value $0003 and the space period register with $0002.
NOTE
The waveforms in Figure 8-5 and Figure 8-6 are for the purpose of
conceptual illustration and are not meant to represent precise timing
relationships between the signals shown.
8.5.2.3 FSK Mode
When the modulator operates in FSK mode (MCGEN bit is set, FSK bit is set, and BASE bit is clear), the
modulation mark and space periods consist of an integer number of carrier clocks (space period can be 0).
When the mark period expires, the space period is transparently started (as in time mode). The carrier
generator toggles between primary and secondary data register values whenever the modulator space
period expires.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
114 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
The space period provides an interpulse gap (no carrier). If CMTCMD3:CMTCMD4 = $0000, then the
modulator and carrier generator will switch between carrier frequencies without a gap or any carrier
glitches (zero space).
Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode can
automatically generate a phase-coherent, dual-frequency FSK signal with programmable burst and
interburst gaps.
The mark and space time equations for FSK mode are:
tmark = (CMTCMD1:CMTCMD2 + 1) fCG Eqn. 8-7
tspace = CMTCMD3:CMTCMD4 fCG Eqn. 8-8
Where fCG is the frequency output from the carrier generator. The example in Figure 8-6 shows what the
IRO pin output looks like in FSK mode with the following values: CMTCMD1:CMTCMD2 = $0003,
CMTCMD3:CMTCMD4 = $0002, primary carrier high count = $01, primary carrier low count = $02,
secondary carrier high count = $03, and secondary carrier low count = $01.
CARRIER OUT (fCG)
MODULATOR GATE MARK1 SPACE1 MARK2 SPACE2 MARK1 SPACE1 MARK2
IRO PIN
Figure 8-6. Example CMT Output in FSK Mode
8.5.3 Extended Space Operation
In time, baseband, or FSK mode, the space period can be made longer than the maximum possible value
of the space period register. Setting the EXSPC bit in the CMTMSC register will force the modulator to
treat the next modulation period (beginning with the next load of the counter and space period register) as
a space period equal in length to the mark and space counts combined. Subsequent modulation periods will
consist entirely of these extended space periods with no mark periods. Clearing EXSPC will return the
modulator to standard operation at the beginning of the next modulation period.
8.5.3.1 EXSPC Operation in Time Mode
To calculate the length of an extended space in time or baseband modes, add the mark and space times and
multiply by the number of modulation periods that EXSPC is set.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 115
Carrier Modulator Transmitter (CMT) Block Description
texspace = tspace + (tmark + tspace) x (number of modulation periods) Eqn. 8-9
For an example of extended space operation, see Figure 8-7.
NOTE
The EXSPC feature can be used to emulate a zero mark event.
SET EXSPC CLEAR EXSPC
Figure 8-7. Extended Space Operation
8.5.3.2 EXSPC Operation in FSK Mode
In FSK mode, the modulator continues to count carrier out clocks, alternating between the primary and
secondary registers at the end of each modulation period.
To calculate the length of an extended space in FSK mode, the user must know whether the EXSPC bit
was set on a primary or secondary modulation period, as well as the total number of both primary and
secondary modulation periods completed while the EXSPC bit is high. A status bit for the current
modulation is not accessible to the CPU. If necessary, software should maintain tracking of the current
modulation cycle (primary or secondary). The extended space period ends at the completion of the space
period time of the modulation period during which the EXSPC bit is cleared.
If the EXSPC bit was set during a primary modulation cycle, use the equation:
texspace = (tspace)p + (tmark + tspace)s + (tmark + tspace)p +... Eqn. 8-10
Where the subscripts p and s refer to mark and space times for the primary and secondary modulation
cycles.
If the EXSPC bit was set during a secondary modulation cycle, use the equation:
texspace = (tspace)s + (tmark + tspace)p + (tmark + tspace)s +... Eqn. 8-11
8.5.4 Transmitter
The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated
on to the IRO pin when the modulator/carrier generator is enabled. When the modulator/carrier generator
is disabled, the IRO pin is controlled by the state of the IRO latch.
A polarity bit in the CMTOC register enables the IRO pin to be high true or low true.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
116 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
8.5.5 CMT Interrupts
The end of cycle flag (EOCF) is set when:
The modulator is not currently active and the MCGEN bit is set to begin the initial CMT
transmission
At the end of each modulation cycle (when the counter is reloaded from CMTCMD1:CMTCMD2)
while the MCGEN bit is set
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, the EOCF
bit will not be set when the MCGEN is set, but will become set at the end of the current modulation cycle.
When the MCGEN becomes disabled, the CMT module does not set the EOC flag at the end of the last
modulation cycle.
The EOCF bit is cleared by reading the CMT modulator status and control register (CMTMSC) followed
by an access of CMTCMD2 or CMTCMD4.
If the EOC interrupt enable (EOCIE) bit is high when the EOCF bit is set, the CMT module will generate
an interrupt request. The EOCF bit must be cleared within the interrupt service routine to prevent another
interrupt from being generated after exiting the interrupt service routine.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMTCMD1:CMTCMD2 and loading the space period register with the contents of
CMTCMD3:CMTCMD4. The EOC interrupt provides a means for the user to reload new mark/space
values into the modulator data registers. Modulator data register updates will take effect at the end of the
current modulation cycle. Note that the down-counter and space period register are updated at the end of
every modulation cycle, regardless of interrupt handling and the state of the EOCF flag.
8.5.6 Wait Mode Operation
During wait mode the CMT, if enabled, will continue to operate normally. However, there will be no new
codes or changes of pattern mode while in wait mode, because the CPU is not operating.
8.5.7 Stop Mode Operation
During all stop modes, clocks to the CMT module are halted.
In stop1 and stop2 modes, all CMT register data is lost and must be re-initialized upon recovery from these
two stop modes.
No CMT module registers are affected in stop3 mode.
Note, because the clocks are halted, the CMT will resume upon exit from stop (only in stop3 mode).
Software should ensure stop2 or stop3 mode is not entered while the modulator is in operation to prevent
the IRO pin from being asserted while in stop mode. This may require a time-out period from the time that
the MCGEN bit is cleared to allow the last modulator cycle to complete.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 117
Carrier Modulator Transmitter (CMT) Block Description
8.5.8 Background Mode Operation
When the microcontroller is in active background mode, the CMT temporarily suspends all counting until
the microcontroller returns to normal user mode.
8.6 CMT Registers and Control Bits
The following registers control and monitor CMT operation:
CMT carrier generator data registers (CMTCGH1, CMTCGL1, CMTCGH2, CMTCGL2)
CMT output control register (CMTOC)
CMT modulator status and control register (CMTMSC)
CMT modulator period data registers (CMTCMD1, CMTCMD2, CMTCMD3, CMTCMD4)
8.6.1 Carrier Generator Data Registers (CMTCGH1, CMTCGL1,
CMTCGH2, and CMTCGL2)
The carrier generator data registers contain the primary and secondary high and low values for generating
the carrier output.
7 6 5 4 3 2 1 0
R PH6 PH5 PH4 PH3 PH2 PH1 PH0
PH7
W
Reset u u u u u u u u
u = Unaffected
Figure 8-8. Carrier Generator Data Register High 1(CMTCGH1)
Table 8-3. CMTCGH1 Field Descriptions
Field Description
7:0 Primary Carrier High Time Data Values -- When selected, these bits contain the number of input clocks
PH[7:0] required to generate the carrier high and low time periods. When operating in time mode (see Section 8.5.2.1,
"Time Mode"), this register pair is always selected. When operating in FSK mode (see Section 8.5.2.3, "FSK
Mode"), this register pair and the secondary register pair are alternatively selected under control of the
modulator. The primary carrier high and low time values are unaffected out of reset. These bits must be written
to nonzero values before the carrier generator is enabled to avoid spurious results.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
118 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
7 6 5 4 3 2 1 0
R
PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
W
Reset u u u u u u u u
u = Unaffected
Figure 8-9. Carrier Generator Data Register Low 1 (CMTCGL1)
Table 8-4. CMTCGL1 Field Descriptions
Field Description
7:0 Primary Carrier Low Time Data Values -- When selected, these bits contain the number of input clocks
PL[7:0] required to generate the carrier high and low time periods. When operating in time mode (see Section 8.5.2.1,
"Time Mode"), this register pair is always selected. When operating in FSK mode (see Section 8.5.2.3, "FSK
Mode"), this register pair and the secondary register pair are alternatively selected under control of the
modulator. The primary carrier high and low time values are unaffected out of reset. These bits must be written
to nonzero values before the carrier generator is enabled to avoid spurious results.
7 6 5 4 3 2 1 0
R SH6 SH5 SH4 SH3 SH2 SH1 SH0
SH7
W
Reset u u u u u u u u
u = Unaffected
Figure 8-10. Carrier Generator Data Register High 2 (CMTCGH2)
Table 8-5. CMTCGH2 Field Descriptions
Field Description
7:0 Secondary Carrier High Time Data Values -- When selected, these bits contain the number of input clocks
SH[7:0] required to generate the carrier high and low time periods. When operating in time mode (see Section 8.5.2.1,
"Time Mode"), this register pair is never selected. When operating in FSK mode (see Section 8.5.2.3, "FSK
Mode"), this register pair and the primary register pair are alternatively selected under control of the modulator.
The secondary carrier high and low time values are unaffected out of reset. These bits must be written to nonzero
values before the carrier generator is enabled when operating in FSK mode.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 119
Carrier Modulator Transmitter (CMT) Block Description
7 6 5 4 3 2 1 0
R
SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0
W
Reset u u u u u u u u
u = Unaffected
Figure 8-11. Carrier Generator Data Register Low 2 (CMTCGL2)
Table 8-6. CMTCGL2 Field Descriptions
Field Description
7:0 Secondary Carrier Low Time Data Values -- When selected, these bits contain the number of input clocks
SL[7:0] required to generate the carrier high and low time periods. When operating in time mode (see Section 8.5.2.1,
"Time Mode"), this register pair is never selected. When operating in FSK mode (see Section 8.5.2.3, "FSK
Mode"), this register pair and the primary register pair are alternatively selected under control of the modulator.
The secondary carrier high and low time values are unaffected out of reset. These bits must be written to nonzero
values before the carrier generator is enabled when operating in FSK mode.
8.6.2 CMT Output Control Register (CMTOC)
This register is used to control the IRO output of the CMT module.
7 6 5 4 3 2 1 0
R 0 0 0 0 0
IROL CMTPOL IROPEN
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-12. CMT Output Control Register (CMTOC)
Table 8-7. CMTOC Field Descriptions
Field Description
7 IRO Latch Control -- Reading IROL reads the state of the IRO latch. Writing IROL changes the state of the IRO
IROL pin when the MCGEN bit is clear in the CMTMSC register and the IROPEN bit is set.
6 CMT Output Polarity -- The CMTPOL bit controls the polarity of the IRO pin output of the CMT.
CMTPOL 0 IRO pin is active low
1 IRO pin is active high
5
IROPEN IRO Pin Enable -- The IROPEN bit is used to enable and disable the IRO pin. When the pin is enabled, it is an
output that drives out either the CMT transmitter output or the state of the IROL bit depending on whether the
MCGEN bit in the CMTMSC register is set. Also, the state of the output is either inverted or not depending on
the state of the CMTPOL bit. When the pin is disabled, it is in a high impedance state so it doesn't draw any
current. The pin is disabled during reset.
0 IRO pin disabled
1 IRO pin enabled as output
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
120 Freescale Semiconductor
Carrier Modulator Transmitter (CMT) Block Description
8.6.3 CMT Modulator Status and Control Register (CMTMSC)
The CMT modulator status and control register (CMTMSC) contains the modulator and carrier generator
enable (MCGEN), end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
(BASE), extended space (EXSPC), prescaler (CMTDIV1:CMTDIV0) bits, and the end of cycle (EOCF)
status bit.
7 6 5 4 3 2 1 0
R EOCF EXSPC BASE FSK EOCIE MCGEN
W 0
Reset CMTDIV1 CMTDIV0
0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-13. CMT Modulator Status and Control Register (CMTMSC)
Table 8-8. CMTMSC Field Descriptions
Field Description
7 End of Cycle Status Flag -- The EOCF bit is set when:
EOCF The modulator is not currently active and the MCGEN bit is set to begin the initial CMT transmission.
At the end of each modulation cycle while the MCGEN bit is set. This is recognized when a match occurs
between the contents of the space period register and the down-counter. At this time, the counter is
initialized with the (possibly new) contents of the mark period buffer, CMTCMD1 and CMTCMD2. The
space period register is loaded with the (possibly new) contents of the space period buffer, CMTCMD3 and
CMTCMD4.
This flag is cleared by a read of the CMTMSC register followed by an access of CMTCMD2 or CMTCMD4.
In the case where the MCGEN bit is cleared and then set before the end of the modulation cycle, EOCF will not
be set when MCGEN is set, but will be set at the end of the current modulation cycle.
0 No end of modulation cycle occurrence since flag last cleared
1 End of modulator cycle has occurred
6:5 CMT Clock Divide Prescaler -- The CMT clock divide prescaler causes the CMT to be clocked at the BUS
CMTDIV[1:0] CLOCK frequency, or the BUS CLOCK frequency divided by 1, 2, 4, or 8. Because these bits are not double
buffered, they should not be changed during a transmission.
00 Bus clock 1
01 Bus clock 2
10 Bus clock 4
11 Bus clock 8
4 Extended Space Enable -- The EXSPC bit enables extended space operation.
EXSPC 0 Extended space disabled
1 Extended space enabled
3 Baseband Enable -- When set, the BASE bit disables the carrier generator and forces the carrier output high
BASE for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output
toggles at the frequency determined by values stored in the carrier data registers. See Section 8.5.2.2,
"Baseband Mode." This bit is cleared by reset. This bit is not double buffered and should not be written to during
a transmission.
0 Baseband mode disabled
1 Baseband mode enabled
2 FSK Mode Select -- The FSK bit enables FSK operation.
FSK 0 CMT operates in time or baseband mode
1 CMT operates in FSK mode
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 121
Carrier Modulator Transmitter (CMT) Block Description
Table 8-8. CMTMSC Field Descriptions (continued)
Field Description
1 End of Cycle Interrupt Enable -- A CPU interrupt will be requested when EOCF is set if EOCIE is high.
EOCIE 0 CPU interrupt disabled
1 CPU interrupt enabled
0
MCGEN Modulator and Carrier Generator Enable -- Setting MCGEN will initialize the carrier generator and modulator
and enable all clocks. After it is enabled, the carrier generator and modulator will function continuously. When
MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks
are disabled (to save power) and the modulator output is forced low. To prevent spurious operation, the user
should initialize all data and control registers before enabling the system.
0 Modulator and carrier generator disabled
1 Modulator and carrier generator enabled
8.6.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3,
and CMTCMD4)
The modulator data registers control the mark and space periods of the modulator for all modes. The
contents of these registers are transferred to the modulator down counter and space period register upon
the completion of a modulation period.
Table 8-9. Sample Register Summary
Name 7 6 5 4 3 2 1 0
CMTCMD1
CMTCMD2 R MB14 MB13 MB12 MB11 MB10 MB9 MB8
CMTCMD3 MB15 MB6 MB5 MB4 MB3 MB2 MB1 MB0
CMTCMD4 SB14 SB13 SB12 SB11 SB10 SB9 SB8
W SB6 SB5 SB4 SB3 SB2 SB1 SB0
R
MB7
W
R
SB15
W
R
SB7
W
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
122 Freescale Semiconductor
Chapter 9
Keyboard Interrupt (S08KBIV1)
9.1 Introduction
The MC9S08RC/RD/RE/RG has two KBI modules. One has eight keyboard interrupt inputs that share
port A pins. The other KBI module has four inputs that are shared on the upper four pins of port C. See the
Pins and Connections chapter for more information about the logic and hardware aspects of these pins.
Port A is an 8-bit port that is shared between the KBI1 keyboard interrupt inputs and general-purpose I/O.
The eight KBI1PEn control bits in the KBI1PE register allow selection of any combination of port A pins
to be assigned as KBI1 inputs. Any pins that are enabled as KBI1 inputs will be forced to act as inputs and
the remaining port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD),
data direction (PTADD) and pullup enable (PTAPE) registers. The eight PTAPEn control bits in the
PTAPE register allow the user to select whether an internal pullup device is enabled on each port A pin
that is configured as a port input or a KBI1 input.
KBI1 inputs can be configured for edge-only sensitivity or edge-and-level sensitivity. Bits 3 through 0 of
port A are falling-edge/low-level sensitive and bits 7 through 4 can be configured for
rising-edge/high-level or for falling-edge/low-level sensitivity.
Port C is an 8-bit port with its lower four pins shared between the KBI2 keyboard interrupt inputs and
general-purpose I/O. The four KBI2PEn control bits in the KBI2PE register allow selection of any
combination of the lower four port C pins to be assigned as KBI2 inputs. Any pins that are enabled as KBI2
inputs will be forced to act as inputs and the remaining port C pins are available as general-purpose I/O
pins controlled by the port C data (PTCD), data direction (PTCDD) and pullup enable (PTCPE) registers.
The eight PTCPEn control bits in the PTCPE register allow the user to select whether an internal pullup
device is enabled on each port C pin that is configured as a port input or a KBI2 input.
Any enabled keyboard interrupt can be used to wake the MCU from wait, standby (stop3), partial
power-down (stop2) or power-down modes (stop1). In either stop1 or stop2 mode, an input functions as a
falling edge/low-level wakeup, therefore it should be configured to use falling-edge sensing if the MCU
will be used in stop1 or stop2 modes.
Either KBI1 or KBI2 can be used to wake the MCU from wait or standby (stop3). Only KBI1 can be used
to wake the MCU from partial power down (stop2) or power down (stop1). When using KBI1 to wake up
from stop2 or stop1, the pins must be configured to use falling-edge/low-level sensing (KBEDG = 0). The
KBF bits for both KBI modules must be cleared before entering stop mode, regardless of whether the
interrupt is enabled.
NOTE
The voltage measured on the pulled up PTA0 pin will be less than VDD. The
internal gates connected to this pin are pulled all the way to VDD. All other
pins with enabled pullup resistors will have an unloaded measurement of
VDD.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 123
Keyboard Interrupt (S08KBIV1)
HCS08 CORE INTERNAL BUS
BDC CPU DEBUG PORT A 7
MODULE (DBG) PTA7/KBI1P7
PTA1/KBI1P1 NOTES1, 2
PTA0/KBI1P0
HCS08 SYSTEM CONTROL 8-BIT KEYBOARD PORT B PTB7/TPM1CH1 NOTES 1, 5
INTERRUPT MODULE (KBI1)
RESETS AND INTERRUPTS PTE6
MODES OF OPERATION 4-BIT KEYBOARD PTB5
POWER MANAGEMENT INTERRUPT MODULE (KBI2) PTB4
PTB3
RTI COP SERIAL COMMUNICATIONS PTB2
INTERFACE MODULE (SCI1) PTB1/RxD1
PTB0/TxD1
ANALOG COMPARATOR
IRQ LVD MODULE (ACMP1)
USER FLASH PORT C PTC7/SS1 NOTE 1
PTC6/SPSCK1
(RC/RD/RE/RG60 = 63,364 BYTES) PTC5/MISO1
(RC/RD/RE/RG32 = 32,768 BYTES) PTC4/MOSI1
PTC3/KBI2P3
(RC/RD/RE16 = 16,384 BYTES) PTC2/KBI2P2
(RC/RD/RE8 = 8192 BYTES) PTC1/KBI2P1
PTC0/KBI2P0
USER RAM 2-CHANNEL TIMER/PWM PORT D PTD6/TPM1CH0 NOTES
MODULE (TPM1) PTD5/ACMP1+ 1, 3, 4
(RC/RD/RE/RG32/60 = 2048 BYTES) PTD4/ACMP1
(RC/RD/RE8/16 = 1024 BYTES) SERIAL PERIPHERAL PTD3
INTERFACE MODULE (SPI1) PTD2/IRQ
EXTAL LOW-POWER OSCILLATOR PTD1/RESET
XTAL PTD0/BKGD/MS
PORT E 8
PTE7PTE0 NOTE 1
VDD VOLTAGE
VSS REGULATOR CARRIER MODULATOR
TIMER MODULE (CMT)
IRO NOTE 5
NOTES:
7. Port pins are software configurable with pullup device if input port
8. PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Also, PTA0 does not pullup to VDD when internal
pullup is enabled.
9. IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1)
10.The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1)
11.High current drive
12.Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is
selected (KBEDGn = 1).
Figure 9-1. MC9S08RC/RD/RE/RG Block Diagram
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
124 Freescale Semiconductor
Keyboard Interrupt (KBI) Block Description
9.2 KBI Block Diagram
Figure 9-2 shows the block diagram for a KBI module.
KBIxP0 KBIPE0
KBIxP3 KBIPE3 VDD KBACK BUSCLK
KBIxP4 D CLR Q RESET KBF
1 CK
0 S KBIPE4 SYNCHRONIZER
KEYBOARD STOP STOP BYPASS KEYBOARD
INTERRUPT FF INTERRUPT
KBEDG4 REQUEST
1 KBIMOD
0 S KBIPEn
KBIxPn KBIE
KBEDGn
Figure 9-2. KBI Block Diagram
The KBI module allows up to eight pins to act as additional interrupt sources. Four of these pins allow
falling-edge sensing while the other four can be configured for either rising-edge sensing or falling-edge
sensing. The sensing mode for all eight pins can also be modified to detect edges and levels instead of only
edges.
9.3 Keyboard Interrupt (KBI) Module
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was
designed to simplify the connection and use of row-column matrices of keyboard switches. However, these
inputs are also useful as extra external interrupt inputs and as an external means of waking up the MCU
from stop or wait low-power modes.
9.3.1 Pin Enables
The KBIPEn control bits in the KBIxPE register allow a user to enable (KBIPEn = 1) any combination of
KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBIxPE are
general-purpose I/O pins that are not associated with the KBI module.
9.3.2 Edge and Level Sensitivity
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI
module must be at the deasserted logic level.
A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level)
during one bus cycle and then a logic 0 (the asserted level) during the next cycle.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 125
Keyboard Interrupt (KBI) Block Description
A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1
during the next cycle.
The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels.
In KBIMOD = 1 mode, the KBF status flag becomes set when an edge is detected (when one or more
enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their
deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard
input pin remains at the asserted level. When the MCU enters stop mode, the synchronous edge-detection
logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous
level-sensitive inputs so they can wake the MCU from stop mode.
9.3.3 KBI Interrupt Controls
The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If
KBIE = 1 in the KBIxSC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag
is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit.
When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
When KBIMOD = 1 (selecting edge-and-level operation), KBF cannot be cleared as long as any keyboard
input is at its asserted level.
9.4 KBI Registers and Control Bits
This section provides information about all registers and control bits associated with the KBI modules.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all KBI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some MCU systems have more than one KBI, so register names include placeholder characters to identify
which KBI is being referenced. For example, KBIxSC refers to the KBIx status and control register and
KBI2SC is the status and control register for KBI2.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
126 Freescale Semiconductor
9.4.1 Keyboard Interrupt (KBI) Block Description
KBI x Status and Control Register (KBIxSC)
7 6 5 4 3 2 1 0
R KBEDG6 KBEDG5 KBEDG4 KBF 0 KBIE KBIMOD
KBEDG7 KBACK 0 0
W
Reset 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-3. KBI x Status and Control Register (KBIxSC)
Table 9-1. KBIxSC Field Descriptions
Field Description
7:4 Keyboard Edge Select for KBI Port Bits -- Each of these read/write bits selects the polarity of the edges and/or
KBEDG[7:4] levels that are recognized as trigger events on the corresponding KBI port pin when it is configured as a keyboard
interrupt input (KBIPEn = 1). Also see the KBIMOD control bit, which determines whether the pin is sensitive to
edges-only or edges and levels.
0 Falling edges/low levels.
1 Rising edges/high levels.
3 Keyboard Interrupt Flag -- This read-only status flag is set whenever the selected edge event has been
KBF detected on any of the enabled KBI port pins. This flag is cleared by writing a logic 1 to the KBACK control bit.
The flag will remain set if KBIMOD = 1 to select edge-and-level operation and any enabled KBI port pin remains
at the asserted level.
0 No KBI interrupt pending.
1 KBI interrupt pending.
KBF can be used as a software pollable flag (KBIE = 0) or it can generate a hardware interrupt request to the
CPU (KBIE = 1). KBF must be cleared before entering stop mode.
2 Keyboard Interrupt Acknowledge -- This write-only bit (reads always return 0) is used to clear the KBF status
KBACK flag by writing a logic 1 to KBACK. When KBIMOD = 1 to select edge-and-level operation and any enabled KBI
port pin remains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the
KBF flag.
1 Keyboard Interrupt Enable -- This read/write control bit determines whether hardware interrupts are generated
KBIE when the KBF status flag equals 1. When KBIE = 0, no hardware interrupts are generated, but KBF can still be
used for software polling.
0 KBF does not generate hardware interrupts (use polling).
1 KBI hardware interrupt requested when KBF = 1.
0 Keyboard Detection Mode -- This read/write control bit selects either edge-only detection or edge-and-level
KBIMOD detection. KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels.
KBI port bits 7 through 4 can be configured to detect either:
Rising edges-only or rising edges and high levels (KBEDGn = 1)
Falling edges-only or falling edges and low levels (KBEDGn = 0)
0 Edge-only detection.
1 Edge-and-level detection.
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 127
Keyboard Interrupt (KBI) Block Description
9.4.2 KBI x Pin Enable Register (KBIxPE)
R 7 6 5 4 3 2 1 0
W
Reset KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0 0 0
0 0 0 0 0
Figure 9-4. KBI x Pin Enable Register (KBIxPE)
Table 9-2. KBIxPE Field Descriptions
Field Description
7:0 Keyboard Pin Enable for KBI Port Bits -- Each of these read/write bits selects whether the associated KBI
KBIPE[7:0] port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin.
0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI.
1 Bit n of KBI port enabled as a keyboard interrupt input
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
128 Freescale Semiconductor
Chapter 10
Timer/PWM Module (S08TPMV1)
10.1 Introduction
The MC9S08RC/RD/RE/RG includes a timer/PWM (TPM) module that supports traditional input capture,
output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit
in the TPM configures both channels in the timer to operate as center-aligned PWM functions. Timing
functions in the TPM are based on a 16-bit counter with prescaler and modulo features to control frequency
and range (period between overflows) of the time reference. This timing system is ideally suited for a wide
range of control applications. The MC9S08RC/RD/RE/RG devices do not have a separate fixed internal
clock source (XCLK). If the XCLK source is selected using the CLKSA and CLKSB control bits (see
Table 10-2), the TPM will use the BUSCLK.
10.2 Features
Timer system features include:
Two separate channels:
-- Each channel may be input capture, output compare, or buffered edge-aligned PWM
-- Rising-edge, falling-edge, or any-edge input capture trigger
-- Set, clear, or toggle output compare action
-- Selectable polarity on PWM outputs
The TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on
both channels
Clock source to prescaler for the TPM is selectable between the bus clock or an external pin:
-- Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
-- External clock input shared with TPM1CH0 timer channel pin
16-bit modulus register to control counter range
Timer system enable
One interrupt per channel plus terminal count interrupt
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor 129
Timer/PWM Module (S08TPMV1) INTERNAL BUS
HCS08 CORE
DEBUG
BDC CPU MODULE (DBG) PORT A 7 NOTES1, 2
PTA7/KBI1P7
PTA1/KBI1P1
PTA0/KBI1P0
HCS08 SYSTEM CONTROL 8-BIT KEYBOARD PORT B PTB7/TPM1CH1 NOTES 1, 5
INTERRUPT MODULE (KBI1)
RESETS AND INTERRUPTS PTE6
MODES OF OPERATION 4-BIT KEYBOARD PTB5
POWER MANAGEMENT INTERRUPT MODULE (KBI2) PTB4
PTB3
RTI COP SERIAL COMMUNICATIONS PTB2
INTERFACE MODULE (SCI1) PTB1/RxD1
PTB0/TxD1
ANALOG COMPARATOR
IRQ LVD MODULE (ACMP1)
USER FLASH PORT C PTC7/SS1 NOTE 1
PTC6/SPSCK1
(RC/RD/RE/RG60 = 63,364 BYTES) PTC5/MISO1
(RC/RD/RE/RG32 = 32,768 BYTES) PTC4/MOSI1
PTC3/KBI2P3
(RC/RD/RE16 = 16,384 BYTES) PTC2/KBI2P2
(RC/RD/RE8 = 8192 BYTES) PTC1/KBI2P1
PTC0/KBI2P0
USER RAM 2-CHANNEL TIMER/PWM PORT D PTD6/TPM1CH0 NOTES
MODULE (TPM1) PTD5/ACMP1+ 1, 3, 4
(RC/RD/RE/RG32/60 = 2048 BYTES) PTD4/ACMP1
(RC/RD/RE8/16 = 1024 BYTES) SERIAL PERIPHERAL PTD3
INTERFACE MODULE (SPI1) PTD2/IRQ
EXTAL LOW-POWER OSCILLATOR PTD1/RESET
XTAL PTD0/BKGD/MS
PORT E 8
PTE7PTE0 NOTE 1
VDD VOLTAGE
VSS REGULATOR CARRIER MODULATOR
TIMER MODULE (CMT)
NOTES: IRO NOTE 5
13.Port pins are software configurable with pullup device if input port
14.PTA0 does not have a clamp diode to VDD. PTA0 should not be driven above VDD. Also, PTA0 does not pullup to VDD when interna
pullup is enabled.
15.IRQ pin contains software configurable pullup/pulldown device if IRQ enabled (IRQPE = 1)
16.The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1)
17.High current drive
18.Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is
selected (KBEDGn = 1).
Figure 10-1. MC9S08RC/RD/RE/RG Block Diagram Highlighting TPM Block and Pins
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
130 Freescale Semiconductor
Timer/PWM (TPM) Block Description
10.3 TPM Block Diagram
The TPM uses one input/output (I/O) pin per channel, TPM1CHn where n is the channel number (for
example, 04). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and
Connections chapter for more information). Figure 10-2 shows the structure of a TPM. Some MCUs
include more than one TPM, with various numbers of channels.
BUSCLK SYNC CLOCK SOURCE PRESCALE AND SELECT
XCLK SELECT DIVIDE BY
TPM1) EXT CLK OFF, BUS, XCLK, EXT 1, 2, 4, 8, 16, 32, 64, or 128
COUNTER RESET INTERRUPT
MAIN 16-BIT COUNTER LOGIC
16-BIT COMPARATOR ELS0B ELS0A
TPM1MODH:TPM1
PORT TPM1CH0
CHANNEL 0 LOGIC
16-BIT COMPARATOR
TPM1C0VH:TPM1C0VL CH0F
16-BIT LATCH INTERRUPT
LOGIC
CH0IE
MS0B MS0A
CHANNEL 1 ELS1B ELS1A PORT TPM1CH1
16-BIT COMPARATOR LOGIC
TPM1C1VH:TPM1C1VL
16-BIT LATCH
INTERNAL BUS CH1F
...
...CH1IE INTERRUPT
... LOGIC
MS1B MS1A
CHANNEL n ELSnB ELSnA TPM1CHn
16-BIT COMPARATOR
TPM1CnVH:TPM1CnVL PORT
LOGIC
16-BIT LATCH
CHnF INTERRUPT
MSnB MSnA CHnIE LOGIC
Figure 10-2. TPM Block Diagram
The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a
modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM
counter (when operating in normal up-counting mode) provides the timing reference for the input capture,
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor &nbs
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