MC74LVX574
Octal D-Type Flip-Flop http://onsemi.com
with 3-State Outputs
MARKING
The MC74LVX574 is an advanced high speed CMOS octal DIAGRAMS
flip-flop with 3-state outputs. The inputs tolerate voltages up to 7.0 V,
allowing the interface of 5.0 V systems to 3.0 V systems. 20 20 LVX574
1 AWLYYWW
This 8-bit D-type flip-flop is controlled by a clock pulse input and SOIC-20
an output enable input. When the output enable input is high, the eight DW SUFFIX
outputs are in a high impedance state. CASE 751D
Features 1
High Speed: tPD = 8.5 ns (Typ) at VCC = 3.3 V 20 20 LVX
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C 1 574
Power Down Protection Provided on Inputs TSSOP-20 ALYW
Balanced Propagation Delays DT SUFFIX
Low Noise: VOLP = 0.8 V (Max) CASE 948E
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA 1
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Pb-Free Packages are Available*
VCC O0 O1 O2 O3 O4 O5 O6 O7 CP 20 74LVX574
20 19 18 17 16 15 14 13 12 11 AWLYWW
SOEIAJ-20
20 M SUFFIX
1 CASE 967
1
1 2 3 4 5 6 7 8 9 10 A = Assembly Location
OE D0 D1 D2 D3 D4 D5 D6 D7 GND L, WL = Wafer Lot
Y, YY = Year
Figure 1. 20-Lead Pinout (Top View) W, WW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005 1 Publication Order Number:
MC74LVX574/D
March, 2005 - Rev. 2
MC74LVX574
D0 2 C 19 Q0
D1 3 Q
D2 4 18 Q1 PIN NAMES
D3 5 D 17 Q2
D4 6 C 16 Q3 Pins Function
D5 7 15 Q4
D6 8 Q OE Output Enable Input
D7 9 D CP Clock Pulse Input
C D0-D7 Data Inputs
DQ O0-O7 3-State Latch Outputs
C
DQ 14 Q5 FUNCTION TABLE
C 13 Q6
DQ 12 Q7 INPUTS OUTPUT
C
DQ OE CP D Q
C
L H H
Q L
D No Change
CQ Z
D
L L
CP 11 L L, H, X
OE 1
H X X
Figure 2. Logic Diagram
ORDERING INFORMATION Package Shipping
Device
MC74LVX574DWR2 SOIC-20 1000 Tape & Reel
MC74LVX574DWR2G SOIC-20 1000 Tape & Reel
(Pb-Free)
MC74LVX574DT TSSOP-20* 75 Units / Rail
MC74LVX574DTR2 TSSOP-20* 2500 Tape & Reel
MC74LVX574M SOEIAJ-20 40 Units / Rail
MC74LVX574MG SOEIAJ-20 40 Units / Rail
(Pb-Free)
MC74LVX574MEL SOEIAJ-20 2000 Tape & Reel
MC74LVX574MELG SOEIAJ-20 2000 Tape & Reel
(Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
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2
MC74LVX574
MAXIMUM RATINGS
Symbol
VCC DCSupplyVoltage
Parameter Value Unit
Vin DCInputVoltage
0.5 to +7.0 V
Vout DCOutputVoltage
0.5 to +7.0 V
IIK InputDiodeCurrent
0.5 to VCC +0.5 V
IOK OutputDiodeCurrent -20 mA
Iout DC Output Current, per Pin 20 mA
ICC DC Supply Current, VCC and GND Pins 25 mA
PD PowerDissipation 75 mA
Tstg Storage Temperature 180 mW
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit_C
65 to +150
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Symbol
RECOMMENDED OPERATING CONDITIONS
VCC
Vin Parameter Min Max Unit
Vout
TA
Dt/DV
DC Supply Voltage 2.0 3.6 V
DC Input Voltage
DC Output Voltage 0 5.5 V
Operating Temperature, All Package Types
Input Rise and Fall Time 0 VCC V
-40 +85 _C
DC ELECTRICAL CHARACTERISTICS
0 100 ns/V
Symbol
VCC TA = 25C TA = - 40 to 85C
VIH High-Level Input Voltage
Parameter Test Conditions V Min Typ Max Min Max Unit
VIL Low-LevelInputVoltage2.0 1.51.5 V
3.0 2.0
3.6 2.4 2.0
2.4
VOH High-LevelOutputVoltage
(Vin = VIH or VIL) 2.0 0.5 0.5 V
3.0 0.8 0.8
3.6 0.8 0.8
IOH = -50mA 2.0 1.9 2.0 1.9 V
VOL Low-LevelOutputVoltageIOH = -50mA
(Vin = VIH or VIL) IOH = -4mA
3.0 2.9 3.0 2.9
IOL = 50mA
IOL = 50mA 3.0 2.58 2.48
IOL = 4mA
Iin2.0 0.0 0.1 0.1 V
Vin = 5.5V or GND
3.0 0.0 0.1 0.1
Vin = VIL or VIH
Vout = VCC or GND 3.0 0.36 0.44
Vin = VCC or GND
IOZ Maximum 3-State Leakage Current 0.1 1.0 mA
Input Leakage Current 3.6
ICC QuiescentSupplyCurrent3.60.22.5mA
5
3.6 4.0 40.0 mA
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3
MC74LVX574
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol
TA = 25C TA = - 40 to 85C
fmax Maximum Clock Frequency
(50% Duty Cycle)
Parameter Test Conditions Min Typ Max Min Max Unit
tPLH,VCC = 2.7VCL = 15pF60 11550ns
tPHL CL = 50pF
45 60 40
VCC = 3.3 0.3V CL = 15pF 80 125 65
CL = 50pF
50 75 45
tPZL,Propagation DelayVCC = 2.7VCL = 15pF9.2 14.5 1.017.5ns
tPZHCP to O CL = 50pF
11.5 18.0 1.0 21.0
VCC = 3.3 0.3V CL = 15pF 8.5 13.2 1.0 15.5
CL = 50pF
11.0 16.7 1.0 19.0
Output Enable Time VCC = 2.7V CL = 15pF 9.8 15.0 1.0 18.5 ns
OE to O RL = 1kW CL = 50pF
tPLZ,
tPHZ
11.4 18.5 1.0 22.0
VCC = 3.3 0.3V CL = 15pF 8.2 12.8 1.0 15.0
RL = 1kW CL = 50pF
10.7 16.3 1.0 18.5
Output Disable Time VCC = 2.7V CL = 50pF 12.1 19.1 1.0 22.0 ns
OE to O RL = 1kW
tOSHL Output-to-OutputSkew
tOSLH (Note1)
VCC = 3.3 0.3V CL = 50pF 11.0 15.0 1.0 17.0
RL = 1kW
VCC = 2.7V CL = 50pF 1.5 1.5 ns
VCC = 3.3 0.3V CL = 50pF
1.5 1.5
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
TA = 25C TA = - 40 to 85C
Cin InputCapacitance
Parameter Min Typ Max Min Max Unit
Cout Maximum Three-State Output Capacitance
4 10 10 pF
CPD Power Dissipation Capacitance (Note 2) 6 pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.28pF
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the
no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25C
Symbol Characteristic Typ Max Unit
VOLP Quiet Output Maximum Dynamic VOL 0.5 0.8 V
VOLV Quiet Output Minimum Dynamic VOL -0.5 -0.8 V
VIHD Minimum High Level Dynamic Input Voltage 2.0 V
VILD Maximum Low Level Dynamic Input Voltage 0.8 V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25C TA = - 40 to 85C
Symbol Parameter Test Conditions Typ Limit Limit Unit
tw(h) Minimum Pulse Width, CP VCC = 2.7V 6.5 7.5 ns
VCC = 3.3 0.3V
5.0 5.0
VCC = 2.7V
tsu Minimum Setup Time, D to CP VCC = 3.3 0.3V 5.0 5.0 ns
VCC = 2.7V 3.5 3.5
VCC = 3.3 0.3V
th Minimum Hold Time, D to CP 1.5 1.5 ns
1.5 1.5
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MC74LVX574
SWITCHING WAVEFORMS
CP 50% VCC
GND
tw
1/fmax
tPLH tPHL
Q 50% VCC
Figure 3.
OE
50% VCC
VOL +0.3V
tPZL tPLZ VALID
GND
VOL -0.H3IVGH VCC
IMPEDANCE D 50%
O 50% VCC HIGH tsu th GND
IMPEDANCE
tPZH tPHZ CP VCC
50%
O 50% VCC GND
Figure 4. Figure 5.
TEST CIRCUITS
TEST POINT TEST POINT
OUTPUT
OUTPUT 1 kW CONNECT TO VCC WHEN
CL* TESTING tPLZ AND tPZL.
DEVICE DEVICE CL* CONNECT TO GND WHEN
UNDER UNDER
TEST TEST TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance *Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit Figure 7. Three-State Test Circuit
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5
MC74LVX574
PACKAGE DIMENSIONS
SOIC-20
DW SUFFIX
CASE 751D-05
ISSUE G
D q NOTES:
A C 1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
20 11 PER ASME Y14.5M, 1994.
10X H 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
0.25 M B M E PROTRUSION.
h X 45_ 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
L 5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1 10 MILLIMETERS
DIM MIN MAX
A 2.35 2.65
B A1 0.10 0.25
20X B B 0.35 0.49
0.25 M T A S B S C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
A h 0.25 0.75
SEATING L 0.50 0.90
PLANE
q 0_ 7_
A1 T
18X e
TSSOP-20
DT SUFFIX
CASE 948E-02
ISSUE B
0.15 (0.006) T U S 20X K REF K NOTES:
2X L/2 20 0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING
J J1 K1 PER ANSI Y14.5M, 1982.
L 11 SECTION N-N 2. CONTROLLING DIMENSION:
MILLIMETER.
PIN 1 B N 0.25 (0.010) 3. DIMENSION A DOES NOT INCLUDE
IDENT -U- MOLD FLASH, PROTRUSIONS OR GATE
M BURRS. MOLD FLASH OR GATE BURRS
1 10 SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
0.15 (0.006) T U S A 4. DIMENSION B DOES NOT INCLUDE
-V- INTERLEAD FLASH OR PROTRUSION.
C INTERLEAD FLASH OR PROTRUSION
D GH SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
0.100 (0.004) 5. DIMENSION K DOES NOT INCLUDE
-T- SEATING DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
PLANE (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
N MILLIMETERS INCHES
F
DETAIL E DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
-W- D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
DETAIL E J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
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6
MC74LVX574
PACKAGE DIMENSIONS
SOEIAJ-20
M SUFFIX
CASE 967-01
ISSUE O
20 11 LE L Q1 NOTES:
M_ DETAIL P c 1. DIMENSIONING AND TOLERANCING PER ANSI
1 E HE Y14.5M, 1982.
VIEW P 2. CONTROLLING DIMENSION: MILLIMETER.
Z 10 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
D FLASH OR PROTRUSIONS AND ARE MEASURED
A AT THE PARTING LINE. MOLD FLASH OR
e PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
A1 PER SIDE.
b 0.10 (0.004) 4. TERMINAL NUMBERS ARE SHOWN FOR
0.13 (0.005) M REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
--- 0.081
A --- 2.05 0.002 0.008
0.014 0.020
A1 0.05 0.20 0.007 0.011
0.486 0.504
b 0.35 0.50 0.201 0.215
0.050 BSC
c 0.18 0.27 0.291 0.323
0.020 0.033
D 12.35 12.80 0.043 0.059
E 5.10 5.45 0 _ 10 _
e 1.27 BSC 0.028 0.035
--- 0.032
HE 7.40 8.20
L 0.50 0.85
LE 1.10 1.50
0 _ 10 _
M
Q1 0.70 0.90
Z --- 0.81
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MC74LVX574
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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