MC33171, MC33172,
MC33174, NCV33172
Single Supply 3.0 V to 44 V, http://onsemi.com
Low Power Operational
Amplifiers 8 PDIP-8
1 P SUFFIX
Quality bipolar fabrication with innovative design concepts are CASE 626
employed for the MC33171/72/74 series of monolithic operational 8
amplifiers. These devices operate at 180 mA per amplifier and offer 1.8 1 SO-8
MHz of gain bandwidth product and 2.1 V/ms slew rate without the use D, VD SUFFIX
of JFET device technology. Although this series can be operated from
split supplies, it is particularly suited for single supply operation, since CASE 751
the common mode input voltage includes ground potential (VEE).
With a Darlington input stage, these devices exhibit high input 14 PDIP-14
resistance, low input offset voltage and high gain. The all NPN output 1 P, VP SUFFIX
stage, characterized by no deadband crossover distortion and large
output voltage swing, provides high capacitance drive capability, 14 CASE 646
excellent phase and gain margins, low open loop high frequency 1
output impedance and symmetrical source/sink AC frequency SO-14
response. D, VD SUFFIX
The MC33171/72/74 are specified over the industrial/automotive CASE 751A
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic as well as the surface 14 TSSOP-14
mount packages. 1 DTB SUFFIX
CASE 948G
Features
ORDERING INFORMATION
Low Supply Current: 180 mA (Per Amplifier)
Wide Supply Operating Range: 3.0 V to 44 V or 1.5 V to 22 V See detailed ordering and shipping information in the package
Wide Input Common Mode Range, Including Ground (VEE) dimensions section on page 9 of this data sheet.
Wide Bandwidth: 1.8 MHz
High Slew Rate: 2.1 V/ms DEVICE MARKING INFORMATION
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: -14.2 V to +14.2 V See general marking information in the device marking
section on page 10 of this data sheet.
(with 15 V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.03%
Excellent Phase Margin: 60
Excellent Gain Margin: 15 dB
Output Short Circuit Protection
ESD Diodes Provide Input Protection for Dual and Quad
Pb-Free Packages are Available
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:
MC33171/D
October, 2006 - Rev. 9
MC33171, MC33172, MC33174, NCV33172
PIN CONNECTIONS
SINGLE QUAD
Offset Null 1 8 NC Output 1 1 14 Output 4
7 VCC
Inv. Input 2 - 6 Output 2 - - 13
Noninv. Input 3 + 5 Offset Null + +
Inputs 1 1 4 Inputs 4
VEE 4
3 12
VCC 4 11 VEE
5+
(Single, Top View) + 10 Inputs 3
Inputs 2 6 - 2 3- 9
DUAL Output 2 7 8 Output 3
(Top View)
Output 1 1 8 VCC
7 Output 2
Inputs 1 2 -1
3+
2- 6 Inputs 2
+5
VEE 4
(Top View)
VCC
Q3 Q4 Q5 Q6 Q7
Q1 Q11 Q17
R1 C1 R2
Q2 D2
R6 Q18 Output
Bias R7
Q8
Q9 Q10
-
Inputs R8
+ C2 D3
Q19
Q13 Q14 Q15 Q16
Q12 Current
D1 Limit
R5
R3 R4
VEE/GND
Offset Null
(MC33171)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
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2
MC33171, MC33172, MC33174, NCV33172
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC/VEE 22 V
Input Differential Voltage Range
Input Voltage Range VIDR (Note 1) V
VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Operating Ambient Temperature Range TA (Note 3) C
Operating Junction Temperature TJ +150 C
Storage Temperature Range Tstg -65 to +150 C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL connected to ground, TA = +25C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (VCM = 0 V) VIO - 2.0 4.5 mV
VCC = +15 V, VEE = -15 V, TA = +25C - 2.5 5.0 mV/C
VCC = +5.0 V, VEE = 0 V, TA = +25C DVIO/DT - - 6.5
VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh (Note 3) IIB - 10 - nA
IIO nA
Average Temperature Coefficient of Offset Voltage - 20 100 V/mV
AVOL - - 200 V
Input Bias Current (VCM = 0 V) VOH
TA = +25C - 5.0 20 mA
TA = Tlow to Thigh (Note 3) VOL - - 40
ISC
Input Offset Current (VCM = 0 V) 50 500 -
TA = +25C 25 - -
TA = Tlow to Thigh (Note 3)
3.5 4.3 -
Large Signal Voltage Gain (VO = 10 V, RL = 10 k) 13.6 14.2 -
TA = +25C 13.3 -
TA = Tlow to Thigh (Note 3) - 0.15
- 0.05 -13.6
Output Voltage Swing - -14.2 -13.3
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25C -
VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C - -
VCC = +15 V, VEE = -15 V, RL = 10 k, TA = Tlow to Thigh (Note 3) 3.0 -
15 5.0
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25C 27
VCC = +15 V, VEE = -15 V, RL = 10 k, TA = +25C
VCC = +15 V, VEE = -15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
Output Short Circuit (TA = +25C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
Input Common Mode Voltage Range VICR V
TA = +25C
TA = Tlow to Thigh (Note 3) VEE to (VCC -1.8)
VEE to (VCC -2.2)
Common Mode Rejection Ratio (RS 10 k), TA = +25C CMRR 80 90 - dB
Power Supply Rejection Ratio (RS = 100 W), TA = +25C PSRR 80 100 - dB
Power Supply Current (Per Amplifier) ID mA
VCC = +5.0 V, VEE = 0 V, TA = +25C - 180 250
VCC = +15 V, VEE = -15 V, TA = +25C
VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh (Note 3) - 220 250
- - 300
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
3. MC3317x Tlow = -40C Thigh = +85C
MC3317xV, NCV33172 Tlow = -40C Thigh = +125C
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3
MC33171, MC33172, MC33174, NCV33172
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL connected to ground, TA = +25C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Slew Rate (Vin = -10 V to +10 V, RL = 10 k, CL = 100 pF) SR 1.6 2.1 V/ms
AV +1 GBW -
AV -1 - 2.1 -
Gain Bandwidth Product (f = 100 kHz) 1.4 1.8 - MHz
Power Bandwidth BWp kHz
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%
- 35 -
Phase Margin fm Deg
RL = 10 k
RL = 10 k, CL = 100 pF - 60 -
Gain Margin - 45 -
RL = 10 k
RL = 10 k, CL = 100 pF Am dB
Equivalent Input Noise Voltage - 15 -
RS = 100 W, f = 1.0 kHz
- 5.0 -
en - 32 - nV/Hz
Equivalent Input Noise Current (f = 1.0 kHz) In - 0.2 - pA/Hz
Differential Input Resistance Rin MW
Vcm = 0 V
- 300 -
Input Capacitance Cin - 0.8 - pF
THD
Total Harmonic Distortion %
AV = +10, RL = 10 k, 2.0 Vpp VO 20 Vpp, f = 10 kHz
- 0.03 -
Channel Separation (f = 10 kHz) CS - 120 - dB
Open Loop Output Impedance (f = 1.0 MHz) zo - 100 - W
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)0VCC/VEE = 1.5 V to 22 V 0 VCC/VEE = 5.0 V to 22 V
Vsat , OUTPUT SATURATION VOLTAGE (V)VCCDVIO = 5.0 mVVCC TA = 25C
-0.8 -1.0
Source
-1.6
-2.4 1.0
0.1 Sink
0
-55 VEE VEE
-25 0 25 50 75 100 125 0 0 1.0 2.0 3.0 4.0
TA, AMBIENT TEMPERATURE (C) IL, LOAD CURRENT (mA)
Figure 2. Input Common Mode Voltage Range Figure 3. Split Supply Output Saturation
versus Temperature versus Load Current
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4
MC33171, MC33172, MC33174, NCV33172
A VOL , OPEN LOOP VOLTAGE GAIN (dB) 3 70 70
0 60
120 , EXCESS PAHSE (DEGREES)
m, PHASE MARGIN (DEGREES) fm 60
20 50 %, PERCENT OVERSHOOT
VCC/VEE = 15 V
Phase Gain 140 40 AVOL = +1.0 50
1 Margin
10 Margin 30 RL = 10 k
= 58 = 15 dB %
160 DVO = 20 mVpp 40
0 VCC/VEE = 15 V 2 20
TA = 25C
RL = 10 k 4
180 30
Vout = 0 V
-10 TA = 25C 3
1 - Phase 200 20
-20 2 - Phase, CL = 100 pF 10 10
3 - Gain
220
-30 4 - Gain, CL = 100 pF 1.0 M 10 M 0 10 20 50 100 200 0
100 k 500 1.0 k
f, FREQUENCY (Hz) CL, LOAD CAPACITANCE (pF)
Figure 4. Open Loop Voltage Gain and Figure 5. Phase Margin and Percent
Phase versus Frequency Overshoot versus Load Capacitance
1.3 5.0 ms/DIV
1.2
GBW AND SR (NORMALIZED) VCC/VEE = 15 V 50 mV/DIV VCC/VEE = 15 V
GBW RL = 10 k VCM = 0 V
1.1 0 VO = 0 V
SR
1.0 DIO = 0.5 mA
TA = 25C
0.9
10 V/DIV 0
0.8
5.0 ms/DIV
0.7 -25 0 25 50 75 100 125 Figure 7. Small and Large Signal
-55
Transient Response
TA, AMBIENT TEMPERATURE (C)
Figure 6. Normalized Gain Bandwidth Product
and Slew Rate versus Temperature
140 I D , I CC , POWER SUPPLY CURRENT (mA) 1.1
1. TA = -55C
VCC/VEE = 15 V 2. TA = 25C Quad 1
120 AV = +1.0 2
z o , OUTPUT IMPEDANCE ( ) RL = 10 k AV = 1000 0.9 3. TA = 125C 3
AV = 100
100 CL = 100 pF 1
TA = 25C 2
3
80 0.7 1
2
60 Dual 3
0.5
25
40 AV = 10 AV = 1.0 Single
20 0.3
0 2.0 k 20 k 200 k 2.0 M 0.1 5.0 10 15 20
200 0
f, FREQUENCY (Hz) VCC/VEE, SUPPLY VOLTAGE (V)
Figure 8. Output Impedance and Frequency Figure 9. Supply Current versus Supply Voltage
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5
MC33171, MC33172, MC33174, NCV33172
APPLICATIONS INFORMATION - CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the 0.8 V of the positive rail (VCC) and negative rail (VEE),
MC33171/72/74 amplifier family is similar to low power op providing a 28.4 Vpp swing from 15 V supplies. This large
amp products utilizing JFET input devices, these amplifiers output swing becomes most noticeable at lower supply
offer additional advantages as a result of the PNP transistor voltages.
differential inputs and an all NPN transistor output stage.
The positive swing is limited by the saturation voltage of
Because the input common mode voltage range of this the current source transistor Q7, the VBE of the NPN pull-up
input stage includes the VEE potential, single supply transistor Q17, and the voltage drop associated with the
operation is feasible to as low as 3.0 V with the common short circuit resistance, R5. For sink currents less than
mode input voltage at ground potential. 0.4 mA, the negative swing is limited by the saturation
voltage of the pull-down transistor Q15, and the voltage
The input stage also allows differential input voltages up drop across R4 and R5. For small valued sink currents, the
to 44 V, provided the maximum input voltage range is not above voltage drops are negligible, allowing the negative
exceeded. Specifically, the input voltages must range swing voltage to approach within millivolts of VEE. For sink
between VCC and VEE supply voltages as shown by the currents (> 0.4 mA), diode D3 clamps the voltage across R4.
maximum rating table. In practice, although not Thus the negative swing is limited by the saturation voltage
recommended, the input voltages can exceed the VCC of Q15, plus the forward diode drop of D3 (VEE +1.0 V).
voltage by approximately 3.0 V and decrease below the VEE Therefore an unprecedented peak-to-peak output voltage
voltage by 0.3 V without causing product damage, although swing is possible for a given supply voltage as indicated by
output phase reversal may occur. It is also possible to source the output swing specifications.
up to 5.0 mA of current from VEE through either inputs'
clamping diode without damage or latching, but phase If the load resistance is referenced to VCC instead of
reversal may again occur. If at least one input is within the ground for single supply applications, the maximum
common mode input voltage range and the other input is possible output swing can be achieved for a given supply
within the maximum input voltage range, no phase reversal voltage. For light load currents, the load resistance will pull
will occur. If both inputs exceed the upper common mode the output to VCC during the positive swing and the output
input voltage limit, the output will be forced to its lowest will pull the load resistance near ground during the negative
voltage state. swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull-up
Since the input capacitance associated with the small capability.
geometry input device is substantially lower (0.8 pF) than
that of a typical JFET (3.0 pF), the frequency response for Because the PNP output emitter-follower transistor has
a given input source resistance is greatly enhanced. This been eliminated, the MC33171/72/74 family offers a 15 mA
becomes evident in D-to-A current to voltage conversion minimum current sink capability, typically to an output
applications where the feedback resistance can form a pole voltage of (VEE +1.8 V). In single supply applications the
with the input capacitance of the op amp. This input pole output can directly source or sink base current from a
creates a 2nd Order system with the single pole op amp and common emitter NPN transistor for current switching
is therefore detrimental to its settling time. In this context, applications.
lower input capacitance is desirable especially for higher
values of feedback resistances (lower current DACs). This In addition, the all NPN transistor output stage is
input pole can be compensated for by creating a feedback inherently faster than PNP types, contributing to the bipolar
zero with a capacitance across the feedback resistance, if amplifier's improved gain bandwidth product. The
necessary, to reduce overshoot. For 10 kW of feedback associated high frequency low output impedance (200 W typ
resistance, the MC33171/72/74 family can typically settle to @ 1.0 MHz) allows capacitive drive capability from 0 pF to
within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12 400 pF without oscillation in the noninverting unity gain
bits in 4.8 ms for a 10 V step. In a standard inverting unity configuration. The 60 phase margin and 15 dB gain margin,
gain fast settling configuration, the symmetrical slew rate is as well as the general gain and phase characteristics, are
typically 2.1 V/ms. In the classic noninverting unity gain virtually independent of the source/sink output swing
configuration the typical output positive slew rate is also conditions. This allows easier system phase compensation,
2.1 V/ms, and the corresponding negative slew rate will since output swing will not be a phase consideration. The AC
usually exceed the positive slew rate as a function of the fall characteristics of the MC33171/72/74 family also allow
time of the input waveform. excellent active filter capability, especially for low voltage
single supply applications.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over Although the single supply specification is defined at
the more conventional NPN/PNP transistor Class AB output 5.0 V, these amplifiers are functional to at least 3.0 V @
stage. A 10 kW load resistance can typically swing within 25C. However slight changes in parametrics such as
bandwidth, slew rate, and DC gain may occur.
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6
MC33171, MC33172, MC33174, NCV33172
If power to this integrated circuit is applied in reverse pole for optimum frequency response, but also minimizes
polarity, or if the IC is installed backwards in a socket, large extraneous "pick up" at this node. Supply decoupling with
unlimited current surges will occur through the device that adequate capacitance immediately adjacent to the supply pin
may result in device destruction. is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
As usual with most high frequency amplifiers, proper lead changes over temperature.
dress, component placement and PC board layout should be
exercised for optimum frequency performance. For The output of any one amplifier is current limited and thus
example, long unshielded input or output leads may result in protected from a direct short to ground. However, under
unwanted input/output coupling. In order to preserve the such conditions, it is important not to allow the device to
relatively low input capacitance associated with these exceed the maximum junction temperature rating. Typically
amplifiers, resistors connected to the inputs should be for 15 V supplies, any one output can be shorted
immediately adjacent to the input pin to minimize additional continuously to ground without exceeding the maximum
stray input capacitance. This not only minimizes the input temperature rating.
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7
MC33171, MC33172, MC33174, NCV33172
2.2 k 510 k VCC
Cin
100 k VCC 3.6 Vpp 100 k VO 0 3.8 Vpp
Vin + VO 0
CO
- VO 100 k CO
100 k + VO
100 k RL 10 k
-
Cin 10 k
RL 100 k
1.0 k
Vin
AV = 101 AV = 10
BW ( -3.0 dB) = 20 kHz BW ( -3.0 dB) = 200 kHz
Figure 10. AC Coupled Noninverting Amplifier Figure 11. AC Coupled Inverting Amplifier
with Single +5.0 V Supply with Single +5.0 V Supply
100 k VCC
4.7 k + VCC 3+7 6
100 k - 50 k
1.0 M RL 2- 5
VO 1
4 10 k
Vin VO 2.5 V 4.2 Vpp VEE
AV = 10 Offset Nulling range is approximately 80 mV with
BW ( -3.0 dB) = 200 kHz a 10 k potentiometer, MC33171 only.
Figure 12. DC Coupled Inverting Amplifier Figure 13. Offset Nulling Circuit
Maximum Output Swing with Single
+5.0 V Supply
Vin 0.2 Vdc VCC
fo = 30 kHz
- C R3 Q = 10
0.047 2.2 k HO = 1.0
16 k 16 k VO R1
+ VO
Vin R R 1.1 k -
0.01 C Vin
C +
R2 0.047
5.6 k
2C 2R 2C fo = 1.0 kHz 0.4
1 VCC
0.02 32 k 0.02 Then: R1 = R3 R2 = R1 R3
fo = 4 p RC 2 HO 4Q2R1 -R3
Given fo = center frequency Q Qo fo < 0.1
Ao = Gain at center frequency R3 = GBW
Choose Value fo, Q, Ao, C p foC
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
Figure 14. Active High-Q Notch Filter Figure 15. Active Bandpass Filter
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8
MC33171, MC33172, MC33174, NCV33172
ORDERING INFORMATION
Op Amp Device Operating Package Shipping
Function MC33171D Temperature Range 98 Units/Rail
MC33171DG SO-8
SO-8
(Pb-Free)
Single MC33171DR2 TA = -40 to +85C SO-8 2500 / Tape & Reel
MC33171DR2G
SO-8
(Pb-Free)
MC33171P Plastic DIP 50 Units/Rail
MC33171PG
Plastic DIP
(Pb-Free)
MC33172D SO-8 98 Units/Rail
MC33172DG
SO-8
(Pb-Free)
MC33172DR2 TA = -40 to +85C SO-8 2500 / Tape & Reel
MC33172DR2G
SO-8
(Pb-Free)
Dual MC33172P Plastic DIP 50 Units/Rail
MC33172PG
Plastic DIP
(Pb-Free)
MC33172VD TA = -40 to +125C SO-8 98 Units/Rail
MC33172VDG 2500 / Tape & Reel
SO-8
MC33172VDR2 (Pb-Free)
MC33172VDR2G
SO-8
SO-8
(Pb-Free)
NCV33172DR2** SO-8 2500 / Tape & Reel
MC33174D SO-14 55 Units/Rail
MC33174DG
SO-14
(Pb-Free)
MC33174DR2 SO-14 2500 / Tape & Reel
MC33174DR2G
SO-14
(Pb-Free)
MC33174DTB TA = -40 to +85C TSSOP-14* 96 Units/Rail
MC33174DTBG TSSOP-14*
Quad MC33174DTBR2 TSSOP-14* 2500 / Tape & Reel
MC33174DTBR2G TSSOP-14*
MC33174P Plastic DIP 25 Units/Rail
MC33174PG
Plastic DIP
(Pb-Free)
MC33174VDR2 TA = -40 to +125C SO-14 2500 / Tape & Reel
MC33174VDR2G 25 Units/Rail
SO-14
MC33174VP (Pb-Free)
MC33174VPG
Plastic DIP
Plastic DIP
(Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
**NCV prefix for automotive and other applications requiring site and control changes.
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9
MC33171, MC33172, MC33174, NCV33172
MARKING DIAGRAMS
PDIP-8 SO-8 SO-8
P SUFFIX D SUFFIX MC33172VD
CASE 626 CASE 751 NCV33172D
CASE 751
8 8
3317x 8
MC3317xP ALYW 3317V
AWL G ALYW
G
YYWWG 1
1
1
PDIP-14 PDIP-14 SO-14 SO-14
P SUFFIX VP SUFFIX D SUFFIX VD SUFFIX
CASE 646 CASE 646 CASE 751A CASE 751A
14 14 14 14
MC33174P MC33174VP MC33174DG MC33174VDG
AWLYYWWG AWLYYWWG AWLYWW AWLYWW
1 1 1 1
TSSOP-14
DTB SUFFIX
CASE 948G
14
MC33
174
ALYW G
G
1
x = 1 or 2
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
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10
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP-8
P SUFFIX
CASE 626-05
ISSUE L
8 5 NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
-B- FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.40 10.16 0.370 0.400
-A-
B 6.10 6.60 0.240 0.260
NOTE 2 C 3.94 4.45 0.155 0.175
L D 0.38 0.51 0.015 0.020
J F 1.02 1.78 0.040 0.070
M
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
-T- M --- 10_ --- 10_
SEATING N 0.76 1.01 0.030 0.040
PLANE
N
H
D K
G
0.13 (0.005) M T A M B M
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11
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC-8 NB
CASE 751-07
ISSUE AH
-X- NOTES:
A 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
8 5 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
B S 0.25 (0.010) M Y M MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
4 K PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
-Y- IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
SEATING B 3.80 4.00 0.150 0.157
PLANE
C 1.35 1.75 0.053 0.069
-Z- D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
H D M J J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
0.25 (0.010) M Z Y S X S N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
SCALE 6:1
mm
inches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
PDIP-14
CASE 646-06
ISSUE P
14 8 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
B Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1 7 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N C F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
-T- J 0.008 0.015 0.20 0.38
SEATING K 0.115 0.135 2.92 3.43
PLANE
L 0.290 0.310 7.37 7.87
K J M --- 10 _ --- 10 _
H G D 14 PL M N 0.015 0.039 0.38 1.01
0.13 (0.005) M
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13
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
SOIC-14
CASE 751A-03
ISSUE H
14 -A- NOTES:
1. DIMENSIONING AND TOLERANCING PER
1 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
-T- -B- P 7 PL 3. DIMENSIONS A AND B DO NOT INCLUDE
0.25 (0.010) M B M MOLD PROTRUSION.
SEATING 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PLANE 7 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
G MILLIMETERS INCHES
C R X 45 _ F DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
K M J F 0.40 1.25 0.016 0.049
D 14 PL G 1.27 BSC 0.050 BSC
0.25 (0.010) M T B S A S J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X 14X
7.04 1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
14
MC33171, MC33172, MC33174, NCV33172
PACKAGE DIMENSIONS
TSSOP-14
CASE 948G-01
ISSUE B
14X K REF NOTES:
0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.15 (0.006) T U S N 0.25 (0.010) 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
2X L/2 14 8 FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
L M EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
PIN 1 B INTERLEAD FLASH OR PROTRUSION.
IDENT. -U- N INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
1 F 5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
7 DETAIL E DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
0.15 (0.006) T U S A J J1 K MILLIMETERS INCHES
K1
-V- DIM MIN MAX MIN MAX
SECTION N-N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C -W- C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
0.10 (0.004) F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
-T- SEATING G H H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
PLANE J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
D DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X 14X
0.36 1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
15
MC33171, MC33172, MC33174, NCV33172
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16
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