电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索
 

MC100ES6111ACR2

器件型号:MC100ES6111ACR2
器件类别:逻辑    逻辑   
厂商名称:IDT (Integrated Device Technology)
标准:  
下载文档 在线购买

MC100ES6111ACR2在线购买

供应商 器件名称 价格 最低购买 库存  
MC100ES6111ACR2 - - 点击查看 点击购买

器件描述

Low Skew Clock Driver, 100E Series, 10 True Output(s), 0 Inverted Output(s), ECL, PQFP32, LEAD FREE, LQFP-32

参数
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
零件包装代码QFP
包装说明LQFP, QFP32,.35SQ,32
针数32
Reach Compliance Codeunknown
ECCN代码EAR99
其他特性ECL MODE: VCC = 0V WITH VEE = -2.5V OR -3.3V SUPPLY; ALSO OPERATES AT 3.3V SUPPLY
系列100E
输入调节DIFFERENTIAL MUX
JESD-30 代码S-PQFP-G32
JESD-609代码e3
长度7 mm
逻辑集成电路类型LOW SKEW CLOCK DRIVER
最大I(ol)0.005 A
湿度敏感等级3
功能数量1
反相输出次数
端子数量32
实输出次数10
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP32,.35SQ,32
封装形状SQUARE
封装形式FLATPACK, LOW PROFILE
峰值回流温度(摄氏度)260
电源-2.5/-3.3/2.5/3.3 V
传播延迟(tpd)0.53 ns
认证状态Not Qualified
Same Edge Skew-Max(tskwd)0.035 ns
座面最大高度1.6 mm
最大供电电压 (Vsup)2.625 V
最小供电电压 (Vsup)2.375 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术ECL
端子面层Matte Tin (Sn) - annealed
端子形式GULL WING
端子节距0.8 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度7 mm

文档预览

Freescale Semiconductor
Technical Data
MC100ES6111
Rev. 5, 07/2005
Low Voltage 2.5/3.3 V Differential
ECL/PECL/HSTL Fanout Buffer
The MC100ES6111 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6111
supports various applications that require distribution of precisely aligned
differential clock signals. Using SiGe:C technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver is high performance clock
distribution in computing, networking and telecommunication systems.
Features
1:10 differential clock distribution
35 ps maximum device skew
Fully differential architecture from input to all outputs
SiGe:C technology supports near-zero output skew
Supports DC to 2.7 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL/HSTL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 32-lead LQFP package
32-lead Pb-free package available
Industrial temperature range
Pin and function compatible to the MC100EP111
MC100ES6111
LOW-VOLTAGE 1:10 DIFFERENTIAL
ECL/PECL/HSTL
CLOCK FANOUT DRIVER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7 GHz. The
device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts
HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If V
BB
is con-
nected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/
PECL signals utilizing the V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6111 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6111 supports positive (PECL) and negative (ECL) supplies. The MC100ES6111 is pin and function compatible to the
MC100EP111.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Q3
Q3
Q4
Q4
Q5
Q5
Q6
18
V
CC
CLKA
CLKA
0
V
CC
CLKB
CLKB
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
V
BB
24
V
CC
Q2
Q2
Q1
Q1
Q0
Q0
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
Q6
17
16
15
14
V
CC
Q7
Q7
Q8
Q8
Q9
Q9
V
CC
13
12
11
10
9
8
V
EE
MC100ES6111
2
3
4
5
6
7
CLK_SEL
V
CC
V
BB
CLKB
CLKA
Figure 1. MC100ES6111 Logic Diagram
Figure 2. 32-Lead Package Pinout
(Top View)
Table 1. Pin Configuration
Pin
CLKA, CLKA
CLKB, CLKB
CLK_SEL
Q[0–9], Q[0–9]
V
EE(1)
V
CC
V
BB
Input
Input
Input
Output
Supply
Supply
Output
DC
I/O
Type
ECL/PECL
HSTL
ECL/PECL
ECL/PECL
Function
Differential reference clock signal input
Alternative differential reference clock signal input
Active clock input select
Differential clock outputs
Negative power supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL or PECL operation
1. In ECL mode (negative power supply mode), V
EE
is either –3.3 V or –2.5 V and V
CC
is connected to GND (0 V). In PECL mode (positive
power supply mode), V
EE
is connected to GND (0 V) and V
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (V
CC
).
Table 2. Function Table
Control
CLK_SEL
Default
0
0
1
CLKA, CLKA input pair is active. CLKA can be CLKB, CLKB input pair is active. CLKB can be
driven by ECL or PECL compatible signals.
driven by HSTL compatible signals.
MC100ES6111
2
Advanced Clock Drivers Devices
Freescale Semiconductor
CLK_SEL
CLKA
CLKB
Table 3. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
T
Func
Characteristics
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Functional Temperature Range
–65
T
A
= –40
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
T
J
= +110
Unit
V
V
V
mA
mA
°C
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 4. General Specifications
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
θ
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-up Immunity
Input Capacitance
Thermal resistance junction to ambient
JESD 51–3, single layer test board
200
4000
2000
200
4.0
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
23.0
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
26.3
110
Min
Typ
V
CC
– 2
(1)
Max
Unit
V
V
V
V
mA
pF
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Inputs
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
MIL-SPEC 883E
Method 1012.1
Condition
JESD 51–6, 2S2P multilayer test board
θ
JC
T
J
Thermal Resistance Junction to Case
Operating Junction Temperature
(2)
(Continuous Operation)
MTBF = 9.1 years
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information).
The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES6111 to be used in applications
requiring industrial temperature range. It is recommended that users of the MC100ES6111 employ thermal modeling analysis to assist in
applying the junction temperature specifications to their particular application.
MC100ES6111
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 5. PECL/HSTL DC Characteristics
(V
CC
= 2.5 V ± 5% or V
CC
= 3.3 V ± 5%, V
EE
= GND, T
J
= 0°C to +110°C)
Symbol
Control Input CLK_SEL
V
IL
V
IH
I
IN
V
PP
V
CMR
I
IN
V
DIF
Input Voltage Low
Input Voltage High
Input Current
(1)
Differential Input Voltage
(2)
Differential Cross Point Voltage
(3)
Input Current
(1)
Differential Input Voltage
(4)
V
CC
= 3.3 V
V
CC
= 2.5 V
Differential Cross Point Voltage
(5)
Input Current
0.4
0.4
0
0.68 – 0.9
V
CC
– 1.1
200
V
V
V
µA
V
IN
= V
X
±
0.2 V
I
OH
= –30 mA
(6)
I
OL
= –5 mA
(6)
V
CC
– 1.810
V
CC
– 1.165
V
CC
– 1.475
V
CC
– 0.880
100
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA (PECL differential signals)
0.1
1.0
1.3
V
CC
– 0.3
100
V
V
µA
Clock Input Pair CLKB, CLKB (HSTL differential signals)
V
X
I
IN
V
OH
V
OL
PECL Clock Outputs (Q0-9, Q0-9)
Output High Voltage
Output Low Voltage
V
CC
= 3.3 V
±
5%
V
CC
= 2.5 V
±
5%
V
CC
– 1.2
V
CC
– 1.9
V
CC
– 1.9
V
CC
– 1.005
V
CC
– 1.705
V
CC
– 1.705
V
CC
– 0.7
V
CC
– 1.5
V
CC
– 1.3
100
V
CC
– 1.4
V
CC
– 1.2
V
V
Supply Current and V
BB
I
EE
V
BB
Maximum Quiescent Supply Current without
Output Termination Current
(7)
Output Reference Voltage
mA
V
V
EE
pin
I
BB
= 200
µA
1. Input have internal pullup/pulldown resistors which affect the input current.
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
4. V
DIF
(DC) is the minimum differential HSTL input voltage swing required for device functionality.
5. V
X
(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V
X
(DC)
range and the input swing lies within the V
PP
(DC) specification.
6. Equivalent to a termination of 50
to V
TT
.
7. I
CC
calculation:
I
CC
= (number of differential output pairs used) x (I
OH
+ I
OL
) + I
EE
I
CC
= (number of differential output pairs used) x (V
OH
– V
TT
)/R
load
+ (V
OL
– V
TT
)/R
load
+ I
EE
MC100ES6111
4
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. ECL DC Characteristics
(V
EE
= –2.5 V ± 5% or V
EE
= –3.3 V ± 5%, V
CC
= GND, T
J
= 0°C to +110°C)
Symbol
Control Input CLK_SEL
V
IL
V
IH
I
IN
V
PP
V
CMR
I
IN
V
OH
V
OL
Input Voltage Low
Input Voltage High
Input Current
(1)
Differential Input Voltage
(2)
Differential Cross Point Voltage
(3)
Input Current
(1)
–1.810
–1.165
–1.475
–0.880
100
V
V
µA
V
IN
= V
IL
or V
IN
= V
IH
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(4)
I
OL
= –5 mA
(4)
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
0.1
V
EE
+ 1.0
1.3
–0.3
100
V
V
µA
ECL Clock Outputs (Q0-9, Q0-9)
Output High Voltage
Output Low Voltage
V
EE
= –3.3 V
±
5%
V
EE
= –2.5 V
±
5%
–1.2
–1.9
–1.9
–1.005
–1.705
–1.705
–0.7
–1.5
–1.3
V
V
Supply Current and V
BB
I
EE
V
BB
Maximum Quiescent Supply Current without
Output Termination Current
(5)
Output Reference Voltage
V
CC
– 1.4
100
V
CC
– 1.2
mA
V
V
EE
pin
I
BB
= 200
µA
1. Input have internal pullup/pulldown resistors which affect the input current.
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
4. Equivalent to a termination of 50
to V
TT
.
5. I
CC
calculation:
I
CC
= (number of differential output pairs used) x (I
OH
+ I
OL
) + I
EE
I
CC
= (number of differential output pairs used) x (V
OH
– V
TT
)/R
load
+ (V
OL
– V
TT
)/R
load
+ I
EE
MC100ES6111
Advanced Clock Drivers Devices
Freescale Semiconductor
5
小广播

技术资料推荐

论坛推荐

技术视频推荐

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
搜索索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
器件入口   2Q 6P C0 GB I4 JF L6 OA P6 RJ TR UI W6 WJ

北京市海淀区知春路23号集成电路设计园量子银座1305 电话:(010)82350740 邮编:100191

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2021 EEWORLD.com.cn, Inc. All rights reserved