The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR DS07-13750-4E
DATA SHEET
16-bit Microcontroller
CMOS
F2MC-16LX MB90920 Series
MB90F922NC/F922NCS/922NCS/F923NC/F923NCS/
MB90F924NC/F924NCS/V920-101/V920-102
■ DESCRIPTION
The MB90920 series is a family of general-purpose FUJITSU SEMICONDUCTOR 16-bit microcontrollers de-
signed for applications such as vehicle instrument panel control.
The instruction set retains the AT architecture from the F2MC-8L and F2MC-16LX families, with further refinements
including high-level language instructions, extended addressing modes, improved multiplication and division
operations (signed), and bit processing. In addition, long word processing is made possible by the inclusion of a
built-in 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz).
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed.
• 16-bit input capture (8 channels)
Detects rising, falling, or both edges.
16-bit capture register × 8
The value of a 16-bit free-run timer counter is latched upon detection of an edge input to pin and an interrupt
request is generated.
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
MB90920 Series
(Continued)
• 16-bit reload timer (4 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Selectable event count function
• Real time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• PPG timer (6 channels)
Output pins (3 channels), external trigger input pin (1 channel)
Operation clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/cleared by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• 8/10-bit A/D converter (8 channels)
Conversion time : 3 μs (at fCP = 32 MHz)
External trigger activation available (P50/INT0/ADTG)
Internal timer activation available (16-bit reload timer 1)
• UART(LIN/SCI) (4 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available
• CAN interface (4 channels : CAN0 and CAN2, and CAN1 and CAN3 share transmission and reception pins,
and interrupt control registers).
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Flexible configuration for receive filter : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN wakeup function (RX connected to INT0 internally)
• LCD controller/driver (32 segment x 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Reset on detection of low voltage/program loop
Automatic reset when low voltage is detected
Program looping detection function
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator (2 channels)
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 125 kHz, 62.5 kHz, 31.2 kHz, 15.6 kHz (at fCP = 32 MHz)
Tone frequencies : PWM frequency /2/ , divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output) 93 ports
• Function for port input level selection
Automotive/CMOS-Schmitt
• Flash memory security function
Protects the contents of Flash memory (Flash memory product only)
2 DS07-13750-4E
MB90920 Series
■ PRODUCT LINEUP
Part number MB90 MB90 MB90 MB90 MB90 MB90 MB90 MB90 MB90
Parameter F922NC F922NCS F923NC F923NCS F924NC F924NCS 922NCS V920-101 V920-102
MASK
Type Flash memory product ROM Evaluation product
product
CPU F2MC-16LX CPU
System clock PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, × 8, 1/2 when PLL stopped)
Minimum instruction execution time 31.25 ns (with 4 MHz oscillation clock × 8)
Sub clock pins Yes No Yes No Yes No No No Yes
(X0A, X1A)
ROM Flash memory Flash memory Flash memory 256 K External
256 Kbytes 384 Kbytes 512 Kbytes bytes
RAM 10 Kbytes 16 Kbytes 24 Kbytes 10 K 30 Kbytes
bytes
I/O port 91 ports 93 ports 91 ports 93 ports 91 ports 93 ports 93 ports 93 ports 91 ports
LCD controller 32 segment × 4 common
LIN-UART UART (LIN/SCI) 4 channels
CAN interface 4 channels
16-bit 8 channels
input capture
16-bit 4 channels
reload timer
16-bit free-run 1 channel
timer
Real time watch 1 channel
timer
16-bit PPG timer 6 channels
External interrupt 8 channels
8/10-bit 8 channels
A/D converter
Low-voltage/
CPU operating Yes No
detection reset
Stepping motor 4 channels
controller
Sound generator 2 channels
Flash memory Yes ⎯
security
Operating 4.0 V to 5.5 V 4.5 V to 5.5 V
voltage
Package LQFP-120 PGA-299
DS07-13750-4E 3
MB90920 Series
■ PIN ASSIGNMENT
(TOP VIEW)
P27/SEG05 P26/SEG04 P25/SEG03 P24/SEG02 P23/SEG01 P22/SEG00 COM3 COM2 COM1 COM0 P15/IN0 P14/TIN2/IN1 X0 X1 VSS VCC P13/PPG5 P12/TIN0/PPG4 P11/TOT0/PPG3/IN4 P10/PPG2/IN5 P07/SEG31 P06/SEG30 P05/SEG29 P04/SEG28 P03/SEG27 P02/SEG26 P01/SEG25 P00/SEG24 P57/SGA0 P56/SGO0/FRCK
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
P30/SEG06 1 90 RST
P31/SEG07 2 89 MD0
P32/SEG08 3 88 MD1
P33/SEG09 4 87 MD2
P34/SEG10 5 86 DVSS
P35/SEG11 6 85 DVCC
P36/SEG12 7 84 P87/PWM2M3
P37/SEG13 8 83 P86/PWM2P3
P40/SEG14 9 82 P85/PWM1M3
P41/SEG15 10 81 P84/PWM1P3
P42/SEG16 11 80 P83/PWM2M2
P43/SEG17 12 79 P82/PWM2P2
* P92/X0A 13 78 P81/PWM1M2
* P93/X1A 14 77 P80/PWM1P2
VCC 15 LQFP-120 76 DVSS
VSS 16 75 DVCC
C 17 74 P77/PWM2M1
P44/SEG18 18 73 P76/PWM2P1
P45/SEG19 19 72 P75/PWM1M1
P46/SEG20 20 71 P74/PWM1P1
P47/SEG21 21 70 P73/PWM2M0
P90/SEG22 22 69 P72/PWM2P0
P91/SEG23 23 68 P71/PWM1M0
PD0/SIN2 24 67 P70/PWM1P0
PD1/SOT2 25 66 DVSS
PD2/SCK2 26 65 DVCC
PD3/SIN3 27 64 PE2/SGO1
PD4/SOT3 28 63 P55/RX0/RX2/INT2
PD5/SCK3 29 62 RSTO
PD6/TOT2 30 61 P54/TX0/TX2/SGA1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
P94/V0 P95/V1 P96/V2 V3 AVCC AVRH P50/INT0/ADTG AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VSS PC0/SIN0/INT4 PC1/SOT0/INT5/IN3 PC2/SCK0/INT6/IN2 PC3/SIN1/INT7 PC4/SOT1 PC5/SCK1/TRG PC6/PPG0/TOT1/IN7 PC7/PPG1/TIN1/IN6 PE0/TOT3 PE1/TIN3 P51/INT1/RX1/RX3 P52/TX1/TX3 P53/INT3
(FPT-120P-M21)
*: MB90V920-101, MB90F922NCS,MB90F923NCS,MB90F924NCS,MB90922NCS : P92, P93
MB90V920-102, MB90F922NC,MB90F923NC,MB90F924NC : X0A, X1A
4 DS07-13750-4E
MB90920 Series
■ PIN DESCRIPTIONS
Pin no. Pin name I/O circuit Function
type*1
108 X0 A High-speed oscillation input pin
107 X1 High-speed oscillation output pin
13 X0A B Low-speed oscillation input pin
P92 I General-purpose I/O port
14 X1A B Low-speed oscillation output pin
P93 I General-purpose I/O port
90 RST C Reset input pin
93 P00 F General-purpose I/O port
SEG24 LCD controller/driver segment output pin
94 P01 F General-purpose I/O port
SEG25 LCD controller/driver segment output pin
95 P02 F General-purpose I/O port
SEG26 LCD controller/driver segment output pin
96 P03 F General-purpose I/O port
SEG27 LCD controller/driver segment output pin
97 P04 F General-purpose I/O port
SEG28 LCD controller/driver segment output pin
98 P05 F General-purpose I/O port
SEG29 LCD controller/driver segment output pin
99 P06 F General-purpose I/O port
SEG30 LCD controller/driver segment output pin
100 P07 F General-purpose I/O port
SEG31 LCD controller/driver segment output pin
P10 General-purpose I/O port
101 PPG2 I 16-bit PPG ch.2 output pin
IN5 Input capture ch.5 trigger input pin
P11 General-purpose I/O port
102 TOT0 I 16-bit reload timer ch.0 TOT output pin
PPG3 16-bit PPG ch.3 output pin
IN4 Input capture ch.4 trigger input pin
P12 General-purpose I/O port
103 TIN0 I 16-bit reload timer ch.0 TIN input pin
PPG4 16-bit PPG ch.4 output pin
(Continued)
DS07-13750-4E 5
MB90920 Series
Pin no. Pin name I/O circuit Function
type*1
104 P13 I General-purpose I/O port
PPG5 16-bit PPG ch.5 output pin
P14 General-purpose I/O port
109 TIN2 I 16-bit reload timer ch.2 TIN input pin
IN1 Input capture ch.1 trigger input pin
110 P15 I General-purpose I/O port
IN0 Input capture ch.0 trigger input pin
111 COM0 P LCD controller/driver common output pin
112 COM1 P LCD controller/driver common output pin
113 COM2 P LCD controller/driver common output pin
114 COM3 P LCD controller/driver common output pin
115 P22 F General-purpose I/O port
SEG00 LCD controller/driver segment output pin
116 P23 F General-purpose I/O port
SEG01 LCD controller/driver segment output pin
117 P24 F General-purpose I/O port
SEG02 LCD controller/driver segment output pin
118 P25 F General-purpose I/O port
SEG03 LCD controller/driver segment output pin
119 P26 F General-purpose I/O port
SEG04 LCD controller/driver segment output pin
120 P27 F General-purpose I/O port
SEG05 LCD controller/driver segment output pin
1 P30 F General-purpose I/O port
SEG06 LCD controller/driver segment output pin
2 P31 F General-purpose I/O port
SEG07 LCD controller/driver segment output pin
3 P32 F General-purpose I/O port
SEG08 LCD controller/driver segment output pin
4 P33 F General-purpose I/O port
SEG09 LCD controller/driver segment output pin
5 P34 F General-purpose I/O port
SEG10 LCD controller/driver segment output pin
6 P35 F General-purpose I/O port
SEG11 LCD controller/driver segment output pin
(Continued)
6 DS07-13750-4E
MB90920 Series
Pin no. Pin name I/O circuit Function
type*1
7 P36 F General-purpose I/O port
SEG12 LCD controller/driver segment output pin
8 P37 F General-purpose I/O port
SEG13 LCD controller/driver segment output pin
9 P40 F General-purpose I/O port
SEG14 LCD controller/driver segment output pin
10 P41 F General-purpose I/O port
SEG15 LCD controller/driver segment output pin
11 P42 F General-purpose I/O port
SEG16 LCD controller/driver segment output pin
12 P43 F General-purpose I/O port
SEG17 LCD controller/driver segment output pin
18 P44 F General-purpose I/O port
SEG18 LCD controller/driver segment output pin
19 P45 F General-purpose I/O port
SEG19 LCD controller/driver segment output pin
20 P46 F General-purpose I/O port
SEG20 LCD controller/driver segment output pin
21 P47 F General-purpose I/O port
SEG21 LCD controller/driver segment output pin
P50 General-purpose I/O port
37 INT0 I INT0 external interrupt input pin
ADTG A/D converter external trigger input pin
P51 General-purpose I/O port
58 INT1 I INT1 external interrupt input pin
RX1 CAN interface 1 RX input pin
RX3 CAN interface 3 RX input pin
P52 General-purpose I/O port
59 TX1 I CAN interface 1 TX output pin
TX3 CAN interface 3 TX output pin
60 P53 I General-purpose I/O port
INT3 INT3 external interrupt input pin
(Continued)
DS07-13750-4E 7
MB90920 Series
Pin no. Pin name I/O circuit Function
type*1
P54 General-purpose I/O port
61 TX0 I CAN interface 0 TX output pin
TX2 CAN interface 2 TX output pin
SGA1 Sound generator ch.1 SGA output pin
P55 General-purpose I/O port
63 RX0 I CAN interface 0 RX input pin
RX2 CAN interface 2 RX input pin
INT2 INT2 external interrupt input pin
P56 General-purpose I/O port
91 SGO0 I Sound generator ch.0 SGO output pin
FRCK Free-run timer clock input pin
92 P57 I General-purpose I/O port
SGA0 Sound generator ch.0 SGA output pin
39 P60 H General-purpose I/O port
AN0 A/D converter input pin
40 P61 H General-purpose I/O port
AN1 A/D converter input pin
41 P62 H General-purpose I/O port
AN2 A/D converter input pin
42 P63 H General-purpose I/O port
AN3 A/D converter input pin
43 P64 H General-purpose I/O port
AN4 A/D converter input pin
44 P65 H General-purpose I/O port
AN5 A/D converter input pin
45 P66 H General-purpose I/O port
AN6 A/D converter input pin
46 P67 H General-purpose I/O port
AN7 A/D converter input pin
67 P70 L General-purpose output-only port
PWM1P0 Stepping motor controller ch.0 output pin
68 P71 L General-purpose output-only port
PWM1M0 Stepping motor controller ch.0 output pin
69 P72 L General-purpose output-only port
PWM2P0 Stepping motor controller ch.0 output pin
(Continued)
8 DS07-13750-4E
MB90920 Series
Pin no. Pin name I/O circuit Function
type*1
70 P73 L General-purpose output-only port
PWM2M0 Stepping motor controller ch.0 output pin
71 P74 L General-purpose output-only port
PWM1P1 Stepping motor controller ch.1 output pin
72 P75 L General-purpose output-only port
PWM1M1 Stepping motor controller ch.1 output pin
73 P76 L General-purpose output-only port
PWM2P1 Stepping motor controller ch.1 output pin
74 P77 L General-purpose output-only port
PWM2M1 Stepping motor controller ch.1 output pin
77 P80 L General-purpose output-only port
PWM1P2 Stepping motor controller ch.2 output pin
78 P81 L General-purpose output-only port
PWM1M2 Stepping motor controller ch.2 output pin
79 P82 L General-purpose output-only port
PWM2P2 Stepping motor controller ch.2 output pin
80 P83 L General-purpose output-only port
PWM2M2 Stepping motor controller ch.2 output pin
81 P84 L General-purpose output-only port
PWM1P3 Stepping motor controller ch.3 output pin
82 P85 L General-purpose output-only port
PWM1M3 Stepping motor controller ch.3 output pin
83 P86 L General-purpose output-only port
PWM2P3 Stepping motor controller ch.3 output pin
84 P87 L General-purpose output-only port
PWM2M3 Stepping motor controller ch.3 output pin
22 P90 F General-purpose I/O port
SEG22 LCD controller/driver segment output pin
23 P91 F General-purpose I/O port
SEG23 LCD controller/driver segment output pin
31 P94 G General-purpose I/O port
V0 LCD controller/driver reference power supply pin
32 P95 G General-purpose I/O port
V1 LCD controller/driver reference power supply pin
(Continued)
DS07-13750-4E 9
MB90920 Series
Pin no. Pin name I/O circuit Function
type*1
33 P96 G General-purpose I/O port
V2 LCD controller/driver reference power supply pin
34 V3 ⎯ LCD controller/driver reference power supply pin
PC0 General-purpose I/O port
48 SIN0 J UART ch.0 serial data input pin
INT4 INT4 external interrupt input pin
PC1 General-purpose I/O port
49 SOT0 I UART ch.0 serial data output pin
INT5 INT5 external interrupt input pin
IN3 Input capture ch.3 trigger input pin
PC2 General-purpose I/O port
50 SCK0 I UART ch.0 serial clock I/O pin
INT6 INT6 external interrupt input pin
IN2 Input capture ch.2 trigger input pin
PC3 General-purpose I/O port
51 SIN1 J UART ch.1 serial data input pin
INT7 INT7 external interrupt input pin
52 PC4 I General-purpose I/O port
SOT1 UART ch.1 serial data output pin
PC5 General-purpose I/O port
53 SCK1 I UART ch.1 serial clock I/O pin
TRG 16-bit PPG ch.0 to ch.5 external trigger input pin
PC6 General-purpose I/O port
54 PPG0 I 16-bit PPG ch.0 output pin
TOT1 16-bit reload timer ch.1 TOT output pin
IN7 Input capture ch.7 trigger input pin
PC7 General-purpose I/O port
55 PPG1 I 16-bit PPG ch.1 output pin
TIN1 16-bit reload timer ch.1 TIN input pin
IN6 Input capture ch.6 trigger input pin
24 PD0 J General-purpose I/O port
SIN2 UART ch.2 serial data input pin
25 PD1 I General-purpose I/O port
SOT2 UART ch.2 serial data output pin
(Continued)
10 DS07-13750-4E
MB90920 Series
(Continued)
Pin no. Pin name I/O circuit Function
type*1
26 PD2 I General-purpose I/O port
SCK2 UART ch.2 serial clock I/O pin
27 PD3 J General-purpose I/O port
SIN3 UART ch.3 serial data input pin
28 PD4 I General-purpose I/O port
SOT3 UART ch.3 serial data output pin
29 PD5 I General-purpose I/O port
SCK3 UART ch.3 serial clock I/O pin
30 PD6 I General-purpose I/O port
TOT2 16-bit reload timer ch.2 TOT output pin
56 PE0 I General-purpose I/O port
TOT3 16-bit reload timer ch.3 TOT output pin
57 PE1 I General-purpose I/O port
TIN3 16-bit reload timer ch.3 TIN input pin
64 PE2 I General-purpose I/O port
SGO1 Sound generator ch.1 SGO output pin
62 RSTO N Internal reset signal output pin
65, 75, 85 DVCC ⎯ Power supply input pins dedicated for high current output buffer
66, 76, 86 DVSS ⎯ Power supply GND pins dedicated for high current output buffer
35 AVCC ⎯ A/D converter dedicated power supply input pin
38 AVSS ⎯ A/D converter dedicated power supply GND pin
36 AVRH ⎯ A/D converter Vref+ input pin. Vref- is fixed to AVSS.
89 MD0 D Mode setting input pin. Connect to VCC pin.
88 MD1 D Mode setting input pin. Connect to VCC pin.
87 MD2 D/E*2 Mode setting input pin. Connect to VSS pin.
17 C ⎯ External capacitor pin.
Connect a 0.1 μF capacitor between this pin and the VSS pin.
15, 105 VCC ⎯ Power supply input pins
16, 47, 106 VSS ⎯ GND power supply pins
*1 : For I/O circuit type, refer to “ ■ I/O CIRCUIT TYPES”.
*2 : The I/O circuit type is D for Flash memory products and E for evaluation products.
DS07-13750-4E 11
MB90920 Series
■ I/O CIRCUIT TYPE
Type Circuit Remarks
A X1 Oscillation circuit
High-speed oscillation feedback
Xout resistance :
approx. 1 MΩ
(Flash memory product/MASK ROM
product/Evaluation product)
X0
Standby control signal
B Oscillation circuit
X1A Xout Low-speed oscillation feedback
resistance : approx. 10 MΩ
X0A
Standby control signal
C Input-only pin (with pull-up resistance)
Pull-up resistor • Attached pull-up resistor :
approx. 50 kΩ
• CMOS hysteresis input
CMOS hysteresis input (VIH/VIL = 0.8 VCC/0.2 VCC)
D Input-only pin
• CMOS hysteresis input
CMOS hysteresis input (VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the Flash
memory products uses this
circuit type.
(Continued)
12 DS07-13750-4E
MB90920 Series
Type Circuit Remarks
E Input-only pin (with pull-down
resistance)
CMOS hysteresis input • Attached pull-down resistance:
approx. 50 kΩ
• CMOS hysteresis input
Pull-down resistor (VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the evaluation
products uses this circuit type.
F LCD output common general-
purpose port
P-ch Pout • CMOS output
(IOH/IOL = ± 4 mA)
N-ch Nout • Hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
LCD input (VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
LCD input enable signal
Automotive input
Standby control signal or
LCD input enable signal
G LCDC reference power supply com-
mon general-purpose port
P-ch Pout • CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
N-ch Nout (VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
LCDC reference power supply (VIH/VIL = 0.8 VCC/0.5 VCC)
input
CMOS hysteresis input
Standby control signal or
LCD output switching signal
Automotive input
Standby control signal or
LCD output switching signal
(Continued)
DS07-13750-4E 13
MB90920 Series
Type Circuit Remarks
H A/D converter input common
general-purpose port
P-ch Pout • CMOS output
(IOH/IOL = ± 4 mA)
N-ch Nout • CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Analog input • Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
I General-purpose port
• CMOS output (IOH/IOL = ± 4 mA)
P-ch Pout • CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
N-ch Nout • Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal
Automotive input
Standby control signal
J General-purpose port (serial input)
P-ch Pout • CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
N-ch Nout (VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
CMOS hysteresis input (VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
Standby control signal (VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
(Continued)
14 DS07-13750-4E
MB90920 Series
Type Circuit Remarks
K A/D converter input common general-
purpose port (serial input)
P-ch Pout • CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
N-ch Nout (VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
Analog output (VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
CMOS hysteresis input (VIH/VIL = 0.8 VCC/0.5 VCC)
Standby control signal
or analog input enable signal
Automotive input
Standby control signal
or analog input enable signal
CMOS input (SIN)
Standby control signal
or analog input enable signal
L High current output port (SMC pin)
P-ch Pout CMOS output (IOH/IOL = ± 30 mA)
High current
N-ch Nout
M LCDC output common general-
P-ch Pout purpose port (serial input) )
• CMOS output (IOH/IOL = ±4 mA)
Nout • CMOS hysteresis input
N-ch (VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
LCDC output (VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
CMOS hysteresis input (VIH/VIL = 0.8 VCC/0.5 VCC)
Standby control signal or
LCDC output switching signal
Automotive input
Standby control signal or
LCDC output switching signal
CMOS input (SIN)
Standby control signal or
LCDC output switching signal
(Continued)
DS07-13750-4E 15
MB90920 Series
(Continued)
Type Circuit Remarks
N Evaluation product Flash memory product N-ch open-drain pin
IOL = 4 mA
P-ch
N-ch Nout N-ch Nout
O Input-only pin
Automotive input Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
P LCDC output pin (COM pin)
P-ch
LCDC output
N-ch
16 DS07-13750-4E
MB90920 Series
■ HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium or high withstand voltage pins, or if the voltage applied between
VCC and VSS pins exceeds the rated voltage level. If a latch-up occurs, the power supply current may increase
dramatically and may destroy semiconductor elements. When using semiconductor devices, always take suffi-
cient care to avoid exceeding maximum ratings.
When the analog system power supply is switched on or off, be careful not to apply the analog power supply
(AVCC, AVRH), the analog input voltages and the power supply voltage for the high current output buffer pins
(DVCC) in excess of the digital power supply voltage (VCC).
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Supply voltage stabilization
Rapid fluctuations in the power supply voltage can cause malfunctions even if the Vcc power supply voltage
remains within the warranted operating range. It is recommended that the power supply be stabilized such that
ripple fluctuations (P-P value) at commercial frequencies (50 Hz/60 Hz) be limited to within 10% of the standard
VCC value, and that transient fluctuations due to power supply switching, etc. be limited to a rate of 0.1 V/ms or less.
• Precautions when turning the power on
In order to prevent the built-in step-down circuits from malfunctioning, the time taken for the voltage to rise
(0.2 V to 2.7 V) during power-on should be less than 50 μs.
• Handling unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Unused input/output pins may be set to the output state and left open, or set to the input state and connected
to a pull-up or pull-down resistance of 2 kΩ or more.
• Handling A/D converter power supply pins
Even if the A/D converter is not used, the power supply pins should be connected such as AVCC = VCC, and
AVSS = AVRH = VSS.
• Notes on using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Furthermore, only the X0A pin should be driven when an external
clock is used, with the X1A pin open as shown in the following diagram. Do not use high-speed oscillation pins
(X0 and X1) for external clock input.
X0A
OPEN X1A
MB90920 Series
Sample external clock connection
DS07-13750-4E 17
MB90920 Series
• Notes on operating in PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, FUJITSU SEMICONDUCTOR will not guarantee results of operations if such
failure occurs.
• Crystal oscillator circuit
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable
operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as
possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross
the lines of other circuits.
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Power supply pins
Devices including multiple VCC or VSS pins are designed such that pins that need to be at the same potential
are interconnected internally to prevent malfunctions such as latch-up. To reduce unnecessary radiation, prevent
malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output
current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Always connect all of the VCC pins to the same potential and all of the VSS pins to ground as shown in the
following diagram. The device will not operate correctly if multiple VCC or VSS pins are connected to different
voltages, even if those voltages are within the guaranteed operating ranges.
VCC
VSS
VCC VSS
VSS
VCC VCC
VSS
VSS VCC
Power supply input pins (Vcc/Vss)
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 μF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
• Sequence for connecting the A/D converter power supply and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital
power supply (VCC) is switched on. When turning the power off, the A/D converter power supply and analog
inputs must be disconnected before the digital power supply is switched off (VCC). Ensure that AVRH does not
exceed AVcc during either power-on or power-off. Even when pins which double as analog input pins are used
as input ports, be sure that the input voltage does not exceed AVCC (turning on/off the analog and digital power
supplies simultaneously is acceptable).
18 DS07-13750-4E
MB90920 Series
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
• Flash memory products and MASK ROM products (MB90F922NC/F922NCS/922NCS/F923NC/
F923NCS/F924NC/F924NCS)
In the Flash memory products and MASK ROM products, the power supply for the high-current output
buffer pins (DVCC, DVSS) is isolated from the digital power supply (VCC).
Therefore, DVcc can therefore be set to a higher voltage than Vcc. If the power supply for the high-current
output buffer pins (DVCC, DVSS) is supplied before the digital power supply (VCC), however, care needs
to be taken because it is possible that the port 7 or port 8 stepping motor outputs may momentarily output
an “H” or “L” level. In order to prevent this, connect the digital power supply (VCC) prior to connecting the
power supply for the high-current output buffer pins. Even when the high-current output buffer pins are
used as general-purpose ports, power should be supplied to the power supply pins for the high-current
output buffer pins (DVCC, DVSS).
• Evaluation product (MB90V920-101/MB90V920-102)
In the evaluation products, the power supply for the high-current output buffer pins (DVCC, DVSS) is not
isolated from the digital power supply (VCC). Therefore, DVCC must therefore be set to a lower voltage than
Vcc. The power supply for the high-current output buffer pins (DVCC, DVSS) must always be applied after
the digital power supply (VCC) has been connected, and disconnected before the digital power supply (Vcc)
is disconnected (the power supply for the high-current output buffer pins may also be connected and
disconnected simultaneously with the digital power supply).
Even when the high-current output buffer pins are used as general-purpose ports, power should be
supplied to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Pull-up/pull-down resistors
MB90920 series does not support internal pull-up/pull-down resistors. Use external components as necessary.
• Precautions when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply a pull-down resistance to the X0A pin and
leave the X1A pin open.
• Notes on operating when the external clock is stopped
The MB90920 series is not guaranteed to operate correctly using the internal oscillator circuit when there is no
external oscillator or the external clock input is stopped.
• Flash memory security function
A security bit is located within the Flash memory region. The security function is activated by writing the protection
code 01H to the security bit.
Do not write the value 01H to this address if you are not using the security function.
Please refer to following table for the address of the security bit.
Flash memory size Address for security bit
MB90F922NC Built-in 2 Mbits Flash Memory FC0001H
MB90F922NCS
MB90F923NCS Built-in 3 Mbits Flash Memory F80001H
MB90F924NCS Built-in 4 Mbits Flash Memory F80001H
DS07-13750-4E 19
MB90920 Series
• Serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a
printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, detect errors
by measures such as adding a checksum to the end of data. If an error is detected, retransmit the data.
• Characteristic difference between flash device and MASK ROM device
In the flash device and the MASK ROM device, the electrical characteristic including current consumption, ESD,
latch-up, the noise characteristic, and oscillation characteristic, etc. is different according to the difference be-
tween the chip layout and the memory structure.
Reconfirm the electrical characteristic when the product is replaced by another product of the same series.
20 DS07-13750-4E
MB90920 Series
■ BLOCK DIAGRAM
Clock control circuit CPU
F2MC-16LX core
Watchdog timer
Time-base timer Interrupt controller
Watch timer
(for sub clock)
Low-voltage reset
Sound generator 0
Sound generator 1 CPU operation
detection reset
CAN controller 0
CAN controller 1
CAN controller 2
CAN controller 3
External interrupt Stepping motor controller 0
(8 channels)
LIN-UART 0 Stepping motor controller 1
Prescaler 0 Stepping motor controller 2
LIN-UART 1
Prescaler 1 Stepping motor controller 3
LIN-UART 2 F2MC-16LX BUS
Prescaler 2
LIN-UART 3 A/D converter
Prescaler 3 (8 channels)
16-bit PPG timer 0 LCD controller/driver
16-bit PPG timer 1 (32 SEG/4 COM)
16-bit PPG timer 2
16-bit PPG timer 3 RAM
16-bit PPG timer 4
16-bit PPG timer 5
16-bit reload timer 0 ROM/Flash
16-bit reload timer 1
16-bit reload timer 2 Tool interface
16-bit reload timer 3
Real-time watch timer
(main)
16-bit ICU 0 (2 channels)
16-bit ICU 1 (2 channels)
16-bit ICU 2 (2 channels)
16-bit ICU 3 (2 channels)
16-bit free-run timer
: Flash memory product and MASK ROM product only
: Evaluation product only
DS07-13750-4E 21
MB90920 Series
■ MEMORY MAP
000000H 000000H
Peripheral area Peripheral area
0000F0H 0000EFH
000100H 000100H
Register Register
RAM area RAM area
(13.5 Kbytes) Address #3
003700H 003700H
Peripheral area Peripheral area
004000H 004000H
RAM area RAM area
(16 Kbytes) Address #2
008000H 008000H
ROM area ROM area
(FF bank image) (FF bank image)
010000H 010000H
F80000H
Address #1
ROM area* ROM area*
: Internal access
FFFFFFH FFFFFFH : Internal access prohibited
MB90V920 (Evaluation product) MB90F922 / MB90922
MB90F923 / MB90F924
Parts No. ROM (Flash) RAM Address #1 Address #2 Address #3
capacitance capacitance
MB90F922NC/F922NCS/922NCS 256 Kbytes 10 Kbytes FC0000H 004000H 002900H
MB90F923NC/F923NCS 384 Kbytes 16 Kbytes FA0000H 004A00H 003700H
MB90F924NC/F924NCS 512 Kbytes 24 Kbytes F80000H 006A00H 003700H
* : Evaluation products do not contain internal ROM. Treat this address as the ROM decode area used by the tools.
Note: To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bits of the FF bank addresses are allocated
to the same addresses as the lower 16-bits of the 00 bank, making it possible to reference tables in ROM
without declaring the “far” modifier with the pointers. For example, when an access is made to the address
00C000H, the actual address to be accessed is FFC000H in ROM. Because the size of the FF bank ROM
area exceeds 32 Kbytes, it is not possible to view the entire region in the 00 bank image. Therefore because
the ROM data from FF8000H to FFFFFFH appears in the image from 008000H to 00FFFFH, it is recommended
that ROM data tables be stored in the area from FF8000H to FFFFFFH.
22 DS07-13750-4E
MB90920 Series
■ I/O MAP
Address Register name Symbol Read/write Resource name Initial value
000000H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB
000001H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB
000002H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB
000003H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB
000004H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB
000005H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB
000006H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB
000007H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB
000008H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB
000009H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB
00000AH, (Disabled)
00000BH
00000CH Port C data register PDRC R/W Port C XXXXXXXXB
00000DH Port D data register PDRD R/W Port D XXXXXXXXB
00000EH Port E data register PDRE R/W Port E XXXXXXXXB
00000FH (Disabled)
000010H Port 0 direction register DDR0 R/W Port 0 00000000B
000011H Port 1 direction register DDR1 R/W Port 1 XX000000B
000012H Port 2 direction register DDR2 R/W Port 2 000000XXB
000013H Port 3 direction register DDR3 R/W Port 3 00000000B
000014H Port 4 direction register DDR4 R/W Port 4 00000000B
000015H Port 5 direction register DDR5 R/W Port 5 00000000B
000016H Port 6 direction register DDR6 R/W Port 6 00000000B
000017H Port 7 direction register DDR7 R/W Port 7 00000000B
000018H Port 8 direction register DDR8 R/W Port 8 00000000B
000019H Port 9 direction register DDR9 R/W Port 9 X0000000B
00001AH Analog input enable ADER6 R/W Port 6, A/D 11111111B
00001BH (Disabled)
00001CH Port C direction register DDRC R/W Port C 00000000B
00001DH Port D direction register DDRD R/W Port D X0000000B
00001EH Port E direction register DDRE R/W Port E XXXXX000B
00001FH (Disabled)
000020H Lower A/D control status register ADCS0 R/W 000XXXX0B
000021H Higher A/D control status register ADCS1 R/W A/D converter 0000000XB
000022H Lower A/D control status register ADCR0 R 00000000B
000023H Higher A/D data register ADCR1 R XXXXXX00B
(Continued)
DS07-13750-4E 23
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
000024H Compare clear register CPCLR R/W XXXXXXXXB
000025H R/W XXXXXXXXB
000026H Timer data register TCDT R/W 16-bit 00000000B
000027H R/W free-run timer 00000000B
000028H Lower timer control status register TCCSL R/W 00000000B
000029H Higher timer control status register TCCSH R/W 01-00000B
00002AH Lower PPG0 control status register PCNTL0 R/W 16-bit PPG0 00000000B
00002BH Higher PPG0 control status register PCNTH0 R/W 00000001B
00002CH Lower PPG1 control status register PCNTL1 R/W 16-bit PPG1 00000000B
00002DH Higher PPG1 control status register PCNTH1 R/W 00000001B
00002EH Lower PPG2 control status register PCNTL2 R/W 16-bit PPG2 00000000B
00002FH Higher PPG2 control status register PCNTH2 R/W 00000001B
000030H External interrupt enable ENIR R/W 00000000B
000031H External interrupt request EIRR R/W External interrupt 00000000B
000032H Lower external interrupt level ELVRL R/W 00000000B
000033H Higher external interrupt level ELVRH R/W 00000000B
000034H Serial mode register 0 SMR0 R/W, W 00000000B
000035H Serial control register 0 SCR0 R/W, W 00000000B
000036H Reception/transmission data register 1 RDR0/ R/W 00000000B
TDR0
000037H Serial status register 0 SSR0 R/W, R UART 00001000B
000038H Extended communication control ECCR0 R/W, R (LIN/SCI) 0 000000XXB
register 0
000039H Extended status control register 0 ESCR0 R/W 00000100B
00003AH Baud rate generator register 00 BGR00 R/W 00000000B
00003BH Baud rate generator register 01 BGR01 R/W, R 00000000B
00003CH
to (Disabled)
00003FH
000040H
to Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
00004FH
000050H Lower timer control status register 0 TMCSR0L R/W 00000000B
000051H Higher timer control status register 0 TMCSR0H R/W 16-bit reload timer XXX10000B
000052H TMR0/ 0 XXXXXXXXB
000053H Timer register 0/reload register 0 TMRLR0 R/W XXXXXXXXB
(Continued)
24 DS07-13750-4E
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
000054H Lower timer control status register 1 TMCSR1L R/W 00000000B
000055H Higher timer control status register 1 TMCSR1H R/W 16-bit reload timer XXX10000B
000056H TMR1/ 1 XXXXXXXXB
000057H Timer register 1/reload register 1 TMRLR1 R/W XXXXXXXXB
000058H LCD output control register 1 LOCR1 R/W LCDC 11111111B
000059H LCD output control register 2 LOCR2 R/W 00000000B
00005AH Lower sound control register 0 SGCRL0 R/W 00000000B
00005BH Higher sound control register 0 SGCRH0 R/W 0XXXX100B
00005CH Frequency data register 0 SGFR0 R/W Sound generator 0 XXXXXXXXB
00005DH Amplitude data register 0 SGAR0 R/W 00000000B
00005EH Decrement grade register 0 SGDR0 R/W XXXXXXXXB
00005FH Tone count register 0 SGTR0 R/W XXXXXXXXB
000060H Input capture register 0 IPCP0 R XXXXXXXXB
000061H Input capture 0/1 XXXXXXXXB
000062H Input capture register 1 IPCP1 R XXXXXXXXB
000063H XXXXXXXXB
000064H Input capture register 2 IPCP2 R XXXXXXXXB
000065H Input capture 2/3 XXXXXXXXB
000066H Input capture register 3 IPCP3 R XXXXXXXXB
000067H XXXXXXXXB
000068H Input capture control status 0/1 ICS01 R/W Input capture 0/1 00000000B
000069H Input capture edge register 0/1 ICE01 R/W XXX0X0XXB
00006AH Input capture control status 2/3 ICS23 R/W Input capture 2/3 00000000B
00006BH Input capture edge register 2/3 ICE23 R/W XXXXXXXXB
00006CH Lower LCD control register LCRL R/W LCD controller/ 00010000B
00006DH Higher LCD control register LCRH R/W driver 00000000B
Low voltage/CPU operation Low voltage/CPU
00006EH detection reset control register LVRC R/W operation 00111000B
detection reset
00006FH ROM mirror ROMM W ROM mirror XXXXXXX1B
000070H
to Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
00007FH
000080H PWM control register 0 PWC0 R/W Stepping motor 000000X0B
controller 0
000081H (Disabled)
000082H PWM control register 1 PWC1 R/W Stepping motor 000000X0B
controller 1
(Continued)
DS07-13750-4E 25
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
000083H (Disabled)
000084H PWM control register 2 PWC2 R/W Stepping motor 000000X0B
controller 2
000085H (Disabled)
000086H PWM control register 3 PWC3 R/W Stepping motor 000000X0B
controller 3
000087H (Disabled)
000088H LCD output control register 3 LOCR3 R/W LCDC XXXXX111B
000089H (Disabled)
00008AH A/D setting register 0 ADSR0 R/W A/D converter 00000000B
00008BH A/D setting register 1 ADSR1 R/W 00000000B
00008CH Port input level select 0 PIL0 R/W 00000000B
00008DH Port input level select 1 PIL1 R/W Port input level XXXX0000B
select
00008EH Port input level select 2 PIL2 R/W XXXX0000B
00008FH
to (Disabled)
00009DH
00009EH Program address detection control PACSR R/W Address match XXXX0X0XB
register detection
00009FH Delayed Interrupt/Release Register DIRR R/W Delay interrupt XXXXXXX0B
0000A0H Power saving mode control register LPMCR R/W Power saving 00011000B
0000A1H Clock select register CKSCR R/W, R control circuit 11111100B
0000A2H
to (Disabled)
0000A7H
0000A8H Watchdog timer control register WDTC R, W Watchdog timer XXXXX111B
0000A9H Time-base timer control register TBTC R/W, W Time-base timer 1XX00100B
0000AAH Watch timer control register WTC R/W, W, R Watch timer 10001000B
(sub clock)
0000ABH
to (Disabled)
0000ADH
0000AEH Flash memory control status register FMCS R/W Flash interface 000X0000B
0000AFH (Disabled)
(Continued)
26 DS07-13750-4E
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
0000B0H Interrupt control register 00 ICR00 R/W 00000111B
0000B1H Interrupt control register 01 ICR01 R/W 00000111B
0000B2H Interrupt control register 02 ICR02 R/W 00000111B
0000B3H Interrupt control register 03 ICR03 R/W 00000111B
0000B4H Interrupt control register 04 ICR04 R/W 00000111B
0000B5H Interrupt control register 05 ICR05 R/W 00000111B
0000B6H Interrupt control register 06 ICR06 R/W 00000111B
0000B7H Interrupt control register 07 ICR07 R/W Interrupt controller 00000111B
0000B8H Interrupt control register 08 ICR08 R/W 00000111B
0000B9H Interrupt control register 09 ICR09 R/W 00000111B
0000BAH Interrupt control register 10 ICR10 R/W 00000111B
0000BBH Interrupt control register 11 ICR11 R/W 00000111B
0000BCH Interrupt control register 12 ICR12 R/W 00000111B
0000BDH Interrupt control register 13 ICR13 R/W 00000111B
0000BEH Interrupt control register 14 ICR14 R/W 00000111B
0000BFH Interrupt control register 15 ICR15 R/W 00000111B
0000C0H
to (Disabled)
0000C3H
0000C4H Serial mode register 1 SMR1 R/W, W 00000000B
0000C5H Serial control register 1 SCR1 R/W, W 00000000B
0000C6H Reception/transmission RDR1/ R/W 00000000B
data register 1 TDR1
0000C7H Serial status register 1 SSR1 R/W, R UART 00001000B
0000C8H Extended communication ECCR1 R/W, R (LIN/SCI) 1 000000XXB
control register 1
0000C9H Extended status control register 1 ESCR1 R/W 00000100B
0000CAH Baud rate generator register 10 BGR10 R/W 00000000B
0000CBH Baud rate generator register 11 BGR11 R/W, R 00000000B
0000CCH Lower watch timer control register WTCRL R/W 000XXXX0B
0000CDH Middle watch timer control register WTCRM R/W Real-time 00000000B
watch timer
0000CEH Higher watch timer control register WTCRH R/W XXXXXX00B
0000CFH Sub clock control register PSCCR W Sub clock XXXX0000B
0000D0H Input capture control status 4/5 ICS45 R/W Input capture 4/5 00000000B
0000D1H Input capture edge register 4/5 ICE45 R/W, R XXXXXXXXB
0000D2H Input capture control status 6/7 ICS67 R/W Input capture 6/7 00000000B
0000D3H Input capture edge register 6/7 ICE67 R/W, R XXX0X0XXB
(Continued)
DS07-13750-4E 27
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
0000D4H Lower timer control status register 2 TMCSR2L R/W 16-bit 00000000B
0000D5H Higher timer control status register 2 TMCSR2H R/W reload timer 2 XXX10000B
0000D6H Lower timer control status register 3 TMCSR3L R/W 16-bit 00000000B
0000D7H Higher timer control status register 3 TMCSR3H R/W reload timer 3 XXX10000B
0000D8H Lower sound control register 1 SGCRL1 R/W Sound generator 1 00000000B
0000D9H Higher sound control register 1 SGCRH1 R/W 0XXXX100B
0000DAH Lower PPG3 control status register PCNTL3 R/W 16-bit PPG3 00000000B
0000DBH Higher PPG3 control status register PCNTH3 R/W 00000001B
0000DCH Lower PPG4 control status register PCNTL4 R/W 16-bit PPG4 00000000B
0000DDH Higher PPG4 control status register PCNTH4 R/W 00000001B
0000DEH Lower PPG5 control status register PCNTL5 R/W 16-bit PPG5 00000000B
0000DFH Higher PPG5 control status register PCNTH5 R/W 00000001B
0000E0H Serial mode register 2 SMR2 R/W, W 00000000B
0000E1H Serial control register 2 SCR2 R/W, W 00000000B
0000E2H Reception/transmission data register 2 RDR2/ R/W 00000000B
TDR2
0000E3H Serial status register 2 SSR2 R/W, R UART 00001000B
0000E4H Extended communication control ECCR2 R/W, R (LIN/SCI) 2 000000XXB
register 2
0000E5H Extended status control register 2 ESCR2 R/W 00000100B
0000E6H Baud rate generator register 20 BGR20 R/W 00000000B
0000E7H Baud rate generator register 21 BGR21 R/W, R 00000000B
0000E8H Serial mode register 3 SMR3 R/W, W 00000000B
0000E9H Serial control register 3 SCR3 R/W, W 00000000B
0000EAH Reception/transmission data register 3 RDR3/ R/W 00000000B
TDR3
0000EBH Serial status register 3 SSR3 R/W, R UART 00001000B
0000ECH Extended communication control ECCR3 R/W, R (LIN/SCI) 3 000000XXB
register 3
0000EDH Extended status control register 3 ESCR3 R/W 00000100B
0000EEH Baud rate generator register 30 BGR30 R/W 00000000B
0000EFH Baud rate generator register 31 BGR31 R/W, R 00000000B
001FF0H Program address detection register 0 PADR0 R/W XXXXXXXXB
001FF1H Program address detection register 1 PADR0 R/W XXXXXXXXB
001FF2H Program address detection register 2 PADR0 R/W Address match XXXXXXXXB
001FF3H Program address detection register 3 PADR1 R/W detection XXXXXXXXB
001FF4H Program address detection register 4 PADR1 R/W XXXXXXXXB
001FF5H Program address detection register 5 PADR1 R/W XXXXXXXXB
(Continued)
28 DS07-13750-4E
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
003700H
to Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
0037FFH
003800H
to Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
0038FFH
003900H
to (Disabled)
00391FH
003920H PPG0 down counter register PDCR0 R 11111111B
003921H 16-bit PPG0 11111111B
003922H PPG0 cycle setting register PCSR0 W 11111111B
003923H 11111111B
003924H PPG0 duty setting register PDUT0 W 00000000B
003925H 16-bit PPG0 00000000B
003926H PPG0 output division setting register PPGDIV0 R/W, R 11111100B
003927H (Disabled)
003928H PPG1 down counter register PDCR1 R 11111111B
003929H 11111111B
00392AH PPG1 cycle setting register PCSR1 W 11111111B
00392BH 16-bit PPG1 11111111B
00392CH PPG1 duty setting register PDUT1 W 00000000B
00392DH 00000000B
00392EH PPG1output division setting register PPGDIV1 R/W, R 11111100B
00392FH (Disabled)
003930H PPG2 down counter register PDCR2 R 11111111B
003931H 11111111B
003932H PPG2 cycle setting register PCSR2 W 11111111B
003933H 16-bit PPG2 11111111B
003934H PPG2 duty setting register PDUT2 W 00000000B
003935H 00000000B
003936H PPG2 output division setting register PPGDIV2 R/W, R 11111100B
003937H
to (Disabled)
00393FH
003940H Input capture register 4 IPCP4 R XXXXXXXXB
003941H Input capture 4/5 XXXXXXXXB
003942H Input capture register 5 IPCP5 R XXXXXXXXB
003943H XXXXXXXXB
(Continued)
DS07-13750-4E 29
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
003944H Input capture register 6 IPCP6 R XXXXXXXXB
003945H Input capture 6/7 XXXXXXXXB
003946H Input capture register 7 IPCP7 R XXXXXXXXB
003947H XXXXXXXXB
003948H
to (Disabled)
00394FH
003950H Minute data register 2/Reload register 2 TMR2/ R/W 16-bit reload timer XXXXXXXXB
003951H TMRLR2 2 XXXXXXXXB
003952H Minute data register 3/Reload register 3 TMR3/ R/W 16-bit reload timer XXXXXXXXB
003953H TMRLR3 3 XXXXXXXXB
003954H
to (Disabled)
003957H
003958H XXXXXXXXB
003959H Sub second data register WTBR R/W XXXXXXXXB
00395AH XXXXXXXXB
00395BH Second data register WTSR R/W Real time XX000000B
watch timer
00395CH Minute data register WTMR R/W XX000000B
00395DH Hour data register WTHR R/W XXX00000B
00395EH Day data register WTDR R/W 00X00001B
00395FH (Disabled)
003960H XXXXXXXXB
003961H XXXXXXXXB
003962H XXXXXXXXB
003963H XXXXXXXXB
003964H XXXXXXXXB
003965H XXXXXXXXB
003966H XXXXXXXXB
003967H LCD XXXXXXXXB
003968H LCD display RAM VRAM R/W controller/ XXXXXXXXB
driver
003969H XXXXXXXXB
00396AH XXXXXXXXB
00396BH XXXXXXXXB
00396CH XXXXXXXXB
00396DH XXXXXXXXB
00396EH XXXXXXXXB
00396FH XXXXXXXXB
(Continued)
30 DS07-13750-4E
MB90920 Series
Address Register name Symbol Read/write Resource name Initial value
003970H
to (Disabled)
003973H
003974H Frequency data register 1 SGFR1 R/W XXXXXXXXB
003975H Amplitude data register 1 SGAR1 R/W Sound generator 1 00000000B
003976H Decrement grade register 1 SGDR1 R/W XXXXXXXXB
003977H Tone count register 1 SGTR1 R/W XXXXXXXXB
003978H
to (Disabled)
00397FH
003980H PWM1 compare register 0 PWC10 R/W XXXXXXXXB
003981H XXXXXXXXB
003982H PWM2 compare register 0 PWC20 R/W Stepping motor XXXXXXXXB
003983H controller 0 XXXXXXXXB
003984H PWM1 select register 0 PWS10 R/W 00000000B
003985H PWM2 select register 0 PWS20 R/W X0000000B
003986H, (Disabled)
003987H
003988H PWM1 compare register 1 PWC11 R/W XXXXXXXXB
003989H XXXXXXXXB
00398AH PWM2 compare register 1 PWC21 R/W Stepping motor XXXXXXXXB
00398BH controller 1 XXXXXXXXB
00398CH PWM1 select register 1 PWS11 R/W 00000000B
00398DH PWM2 select register 1 PWS21 R/W X0000000B
00398EH, (Disabled)
00398FH
003990H PWM1 compare register 2 PWC12 R/W XXXXXXXXB
003991H XXXXXXXXB
003992H PWM2 compare register 2 PWC22 R/W Stepping motor XXXXXXXXB
003993H controller 2 XXXXXXXXB
003994H PWM1 select register 2 PWS12 R/W 00000000B
003995H PWM2 select register 2 PWS22 R/W X0000000B
003996H, (Disabled)
003997H
(Continued)
DS07-13750-4E 31
MB90920 Series
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003998H PWM1 compare register 3 PWC13 R/W XXXXXXXXB
003999H XXXXXXXXB
00399AH PWM2 compare register 3 PWC23 R/W Stepping motor XXXXXXXXB
00399BH controller 3 XXXXXXXXB
00399CH PWM1 select register 3 PWS13 R/W 00000000B
00399DH PWM2 select register 3 PWS23 R/W X0000000B
00399EH
to (Disabled)
0039A5H
0039A6H Flash write control register 0 FWR0 R/W Flash I/F 00000000B
0039A7H Flash write control register 1 FWR1 00000000B
0039A8H
to (Disabled)
0039BFH
0039C0H
to Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
0039DFH
0039E0H
to Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
0039FFH
003A00H
to Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
003AFFH
003B00H
to Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
003BFFH
003C00H
to Area reserved for CAN Controller 0. Refer to “■ CAN CONTROLLERS”
003CFFH
003D00H
to Area reserved for CAN Controller 1. Refer to “■ CAN CONTROLLERS”
003DFFH
003E00H
to Area reserved for CAN Controller 2. Refer to “■ CAN CONTROLLERS”
003EFFH
003F00H
to Area reserved for CAN Controller 3. Refer to “■ CAN CONTROLLERS”
003FFFH
32 DS07-13750-4E
MB90920 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers(1)
Address Register Abbreviation Access Initial Value
CAN0 CAN1 CAN2 CAN3
003C00H 003D00H 003E00H 003F00H Control status register CSR R/W, R 00---000B
003C01H 003D01H 003E01H 003F01H 0----0-1B
003C02H 003D02H 003E02H 003F02H Last event indicator LEIR R/W --------B
003C03H 003D03H 003E03H 003F03H register 000-0000B
003C04H 003D04H 003E04H 003F04H RX/TX error counter RTEC R 00000000B
003C05H 003D05H 003E05H 003F05H 00000000B
003C06H 003D06H 003E06H 003F06H Bit timing register BTR R/W -1111111B
003C07H 003D07H 003E07H 003F07H 11111111B
DS07-13750-4E 33
MB90920 Series
List of Control Registers(2)
Address Register Abbre- Access Initial Value
CAN0 CAN1 CAN2 CAN3 viation
000040H 000070H 0039C0H 0039D0H Message buffer valid register BVALR R/W 00000000B
000041H 000071H 0039C1H 0039D1H 00000000B
000042H 000072H 0039C2H 0039D2H Transmit request register TREQR R/W 00000000B
000043H 000073H 0039C3H 0039D3H 00000000B
000044H 000074H 0039C4H 0039D4H Transmit cancel register TCANR W 00000000B
000045H 000075H 0039C5H 0039D5H 00000000B
000046H 000076H 0039C6H 0039D6H Transmit complete register TCR R/W 00000000B
000047H 000077H 0039C7H 0039D7H 00000000B
000048H 000078H 0039C8H 0039D8H Receive complete register RCR R/W 00000000B
000049H 000079H 0039C9H 0039D9H 00000000B
00004AH 00007AH 0039CAH 0039DAH Remote request receive RRTRR R/W 00000000B
00004BH 00007BH 0039CBH 0039DBH register 00000000B
00004CH 00007CH 0039CCH 0039DCH Receive overrun register ROVRR R/W 00000000B
00004DH 00007DH 0039CDH 0039DDH 00000000B
00004EH 00007EH 0039CEH 0039DEH Receive interrupt enable RIER R/W 00000000B
00004FH 00007FH 0039CFH 0039DFH register 00000000B
003C08H 003D08H 003E08H 003F08H IDE register IDER R/W XXXXXXXXB
003C09H 003D09H 003E09H 003F09H XXXXXXXXB
003C0AH 003D0AH 003E0AH 003F0AH Transmit RTR register TRTRR R/W 00000000B
003C0BH 003D0BH 003E0BH 003F0BH 00000000B
003C0CH 003D0CH 003E0CH 003F0CH Remote frame receive wait RFWTR R/W XXXXXXXXB
003C0DH 003D0DH 003E0DH 003F0DH register XXXXXXXXB
003C0EH 003D0EH 003E0EH 003F0EH Transmit interrupt enable TIER R/W 00000000B
003C0FH 003D0FH 003E0FH 003F0FH register 00000000B
003C10H 003D10H 003E10H 003F10H XXXXXXXXB
003C11H 003D11H 003E11H 003F11H Acceptance mask select XXXXXXXXB
003C12H 003D12H 003E12H 003F12H register AMSR R/W
XXXXXXXXB
003C13H 003D13H 003E13H 003F13H XXXXXXXXB
003C14H 003D14H 003E14H 003F14H XXXXXXXXB
003C15H 003D15H 003E15H 003F15H XXXXXXXXB
003C16H 003D16H 003E16H 003F16H Acceptance mask register 0 AMR0 R/W
XXXXX---B
003C17H 003D17H 003E17H 003F17H XXXXXXXXB
003C18H 003D18H 003E18H 003F18H XXXXXXXXB
003C19H 003D19H 003E19H 003F19H XXXXXXXXB
003C1AH 003D1AH 003E1AH 003F1AH Acceptance mask register 1 AMR1 R/W
XXXXX---B
003C1BH 003D1BH 003E1BH 003F1BH XXXXXXXXB
34 DS07-13750-4E
MB90920 Series
List of Message Buffers (ID Registers)
Address Register Abbre- Access Initial Value
CAN0 CAN1 CAN2 CAN3 viation
003A00H 003B00H 003700H 003800H XXXXXXXXB
to to to to General-purpose RAM ⎯ R/W to
003A1FH 003B1FH 00371FH 00381FH XXXXXXXXB
003A20H 003B20H 003720H 003820H XXXXXXXXB
003A21H 003B21H 003721H 003821H XXXXXXXXB
003A22H 003B22H 003722H 003822H ID register 0 IDR0 R/W
XXXXX---B
003A23H 003B23H 003723H 003823H XXXXXXXXB
003A24H 003B24H 003724H 003824H XXXXXXXXB
003A25H 003B25H 003725H 003825H XXXXXXXXB
003A26H 003B26H 003726H 003826H ID register 1 IDR1 R/W
XXXXX---B
003A27H 003B27H 003727H 003827H XXXXXXXXB
003A28H 003B28H 003728H 003828H XXXXXXXXB
003A29H 003B29H 003729H 003829H XXXXXXXXB
003A2AH 003B2AH 00372AH 00382AH ID register 2 IDR2 R/W
XXXXX---B
003A2BH 003B2BH 00372BH 00382BH XXXXXXXXB
003A2CH 003B2CH 00372CH 00382CH XXXXXXXXB
003A2DH 003B2DH 00372DH 00382DH XXXXXXXXB
003A2EH 003B2EH 00372EH 00382EH ID register 3 IDR3 R/W
XXXXX---B
003A2FH 003B2FH 00372FH 00382FH XXXXXXXXB
003A30H 003B30H 003730H 003830H XXXXXXXXB
003A31H 003B31H 003731H 003831H XXXXXXXXB
003A32H 003B32H 003732H 003832H ID register 4 IDR4 R/W
XXXXX---B
003A33H 003B33H 003733H 003833H XXXXXXXXB
003A34H 003B34H 003734H 003834H XXXXXXXXB
003A35H 003B35H 003735H 003835H XXXXXXXXB
003A36H 003B36H 003736H 003836H ID register 5 IDR5 R/W
XXXXX---B
003A37H 003B37H 003737H 003837H XXXXXXXXB
003A38H 003B38H 003738H 003838H XXXXXXXXB
003A39H 003B39H 003739H 003839H XXXXXXXXB
003A3AH 003B3AH 00373AH 00383AH ID register 6 IDR6 R/W
XXXXX---B
003A3BH 003B3BH 00373BH 00383BH XXXXXXXXB
003A3CH 003B3CH 00373CH 00383CH XXXXXXXXB
003A3DH 003B3DH 00373DH 00383DH XXXXXXXXB
003A3EH 003B3EH 00373EH 00383EH ID register 7 IDR7 R/W
XXXXX---B
003A3FH 003B3FH 00373FH 00383FH XXXXXXXXB
(Continued)
DS07-13750-4E 35
MB90920 Series
(Continued)
Address Register Abbre- Access Initial Value
CAN0 CAN1 CAN2 CAN3 viation
003A40H 003B40H 003740H 003840H XXXXXXXXB
003A41H 003B41H 003741H 003841H XXXXXXXXB
003A42H 003B42H 003742H 003842H ID register 8 IDR8 R/W
XXXXX---B
003A43H 003B43H 003743H 003843H XXXXXXXXB
003A44H 003B44H 003744H 003844H XXXXXXXXB
003A45H 003B45H 003745H 003845H XXXXXXXXB
003A46H 003B46H 003746H 003846H ID register 9 IDR9 R/W
XXXXX---B
003A47H 003B47H 003747H 003847H XXXXXXXXB
003A48H 003B48H 003748H 003848H XXXXXXXXB
003A49H 003B49H 003749H 003849H XXXXXXXXB
003A4AH 003B4AH 00374AH 00384AH ID register 10 IDR10 R/W
XXXXX---B
003A4BH 003B4BH 00374BH 00384BH XXXXXXXXB
003A4CH 003B4CH 00374CH 00384CH XXXXXXXXB
003A4DH 003B4DH 00374DH 00384DH XXXXXXXXB
003A4EH 003B4EH 00374EH 00384EH ID register 11 IDR11 R/W
XXXXX---B
003A4FH 003B4FH 00374FH 00384FH XXXXXXXXB
003A50H 003B50H 003750H 003850H XXXXXXXXB
003A51H 003B51H 003751H 003851H XXXXXXXXB
003A52H 003B52H 003752H 003852H ID register 12 IDR12 R/W
XXXXX---B
003A53H 003B53H 003753H 003853H XXXXXXXXB
003A54H 003B54H 003754H 003854H XXXXXXXXB
003A55H 003B55H 003755H 003855H XXXXXXXXB
003A56H 003B56H 003756H 003856H ID register 13 IDR13 R/W
XXXXX---B
003A57H 003B57H 003757H 003857H XXXXXXXXB
003A58H 003B58H 003758H 003858H XXXXXXXXB
003A59H 003B59H 003759H 003859H XXXXXXXXB
003A5AH 003B5AH 00375AH 00385AH ID register 14 IDR14 R/W
XXXXX---B
003A5BH 003B5BH 00375BH 00385BH XXXXXXXXB
003A5CH 003B5CH 00375CH 00385CH XXXXXXXXB
003A5DH 003B5DH 00375DH 00385DH XXXXXXXXB
003A5EH 003B5EH 00375EH 00385EH ID register 15 IDR15 R/W
XXXXX---B
003A5FH 003B5FH 00375FH 00385FH XXXXXXXXB
36 DS07-13750-4E
MB90920 Series
List of Message Buffers (DLC Registers)
Address Register Abbrevia- Access Initial Value
CAN0 CAN1 CAN2 CAN3 tion
003A60H 003B60H 003760H 003860H DLC register 0 DLCR0 R/W ----XXXXB
003A61H 003B61H 003761H 003861H
003A62H 003B62H 003762H 003862H DLC register 1 DLCR1 R/W ----XXXXB
003A63H 003B63H 003763H 003863H
003A64H 003B64H 003764H 003864H DLC register 2 DLCR2 R/W ----XXXXB
003A65H 003B65H 003765H 003865H
003A66H 003B66H 003766H 003866H DLC register 3 DLCR3 R/W ----XXXXB
003A67H 003B67H 003767H 003867H
003A68H 003B68H 003768H 003868H DLC register 4 DLCR4 R/W ----XXXXB
003A69H 003B69H 003769H 003869H
003A6AH 003B6AH 00376AH 00386AH DLC register 5 DLCR5 R/W ----XXXXB
003A6BH 003B6BH 00376BH 00386BH
003A6CH 003B6CH 00376CH 00386CH DLC register 6 DLCR6 R/W ----XXXXB
003A6DH 003B6DH 00376DH 00386DH
003A6EH 003B6EH 00376EH 00386EH DLC register 7 DLCR7 R/W ----XXXXB
003A6FH 003B6FH 00376FH 00386FH
003A70H 003B70H 003770H 003870H DLC register 8 DLCR8 R/W ----XXXXB
003A71H 003B71H 003771H 003871H
003A72H 003B72H 003772H 003872H DLC register 9 DLCR9 R/W ----XXXXB
003A73H 003B73H 003773H 003873H
003A74H 003B74H 003774H 003874H DLC register 10 DLCR10 R/W ----XXXXB
003A75H 003B75H 003775H 003875H
003A76H 003B76H 003776H 003876H DLC register 11 DLCR11 R/W ----XXXXB
003A77H 003B77H 003777H 003877H
003A78H 003B78H 003778H 003878H DLC register 12 DLCR12 R/W ----XXXXB
003A79H 003B79H 003779H 003879H
003A7AH 003B7AH 00377AH 00387AH DLC register 13 DLCR13 R/W ----XXXXB
003A7BH 003B7BH 00377BH 00387BH
003A7CH 003B7CH 00377CH 00387CH DLC register 14 DLCR14 R/W ----XXXXB
003A7DH 003B7DH 00377DH 00387DH
003A7EH 003B7EH 00377EH 00387EH DLC register 15 DLCR15 R/W ----XXXXB
003A7FH 003B7FH 00377FH 00387FH
DS07-13750-4E 37
MB90920 Series
List of Message Buffers (Data register)
Address Register Abbre- Access Initial Value
CAN0 CAN1 CAN2 CAN3 viation
003A80H 003B80H 003780H 003880H XXXXXXXXB
to to to to Data register 0 (8 bytes) DTR0 R/W to
003A87H 003B87H 003787H 003887H XXXXXXXXB
003A88H 003B88H 003788H 003888H XXXXXXXXB
to to to to Data register 1 (8 bytes) DTR1 R/W to
003A8FH 003B8FH 00378FH 00388FH XXXXXXXXB
003A90H 003B90H 003790H 003890H XXXXXXXXB
to to to to Data register 2 (8 bytes) DTR2 R/W to
003A97H 003B97H 003797H 003897H XXXXXXXXB
003A98H 003B98H 003798H 003898H XXXXXXXXB
to to to to Data register 3 (8 bytes) DTR3 R/W to
003A9FH 003B9FH 00379FH 00389FH XXXXXXXXB
003AA0H 003BA0H 0037A0H 0038A0H XXXXXXXXB
to to to to Data register 4 (8 bytes) DTR4 R/W to
003AA7H 003BA7H 0037A7H 0038A7H XXXXXXXXB
003AA8H 003BA8H 0037A8H 0038A8H XXXXXXXXB
to to to to Data register 5 (8 bytes) DTR5 R/W to
003AAFH 003BAFH 0037AFH 0038AFH XXXXXXXXB
003AB0H 003BB0H 0037B0H 0038B0H XXXXXXXXB
to to to to Data register 6 (8 bytes) DTR6 R/W to
003AB7H 003BB7H 0037B7H 0038B7H XXXXXXXXB
003AB8H 003BB8H 0037B8H 0038B8H XXXXXXXXB
to to to to Data register 7 (8 bytes) DTR7 R/W to
003ABFH 003BBFH 0037BFH 0038BFH XXXXXXXXB
003AC0H 003BC0H 0037C0H 0038C0H XXXXXXXXB
to to to to Data register 8 (8 bytes) DTR8 R/W to
003AC7H 003BC7H 0037C7H 0038C7H XXXXXXXXB
003AC8H 003BC8H 0037C8H 0038C8H XXXXXXXXB
to to to to Data register 9 (8 bytes) DTR9 R/W to
003ACFH 003BCFH 0037CFH 0038CFH XXXXXXXXB
003AD0H 003BD0H 0037D0H 0038D0H XXXXXXXXB
to to to to Data register 10 (8 bytes) DTR10 R/W to
003AD7H 003BD7H 0037D7H 0038D7H XXXXXXXXB
003AD8H 003BD8H 0037D8H 0038D8H XXXXXXXXB
to to to to Data register 11 (8 bytes) DTR11 R/W to
003ADFH 003BDFH 0037DFH 0038DFH XXXXXXXXB
003AE0H 003BE0H 0037E0H 0038E0H XXXXXXXXB
to to to to Data register 12 (8 bytes) DTR12 R/W to
003AE7H 003BE7H 0037E7H 0038E7H XXXXXXXXB
003AE8H 003BE8H 0037E8H 0038E8H XXXXXXXXB
to to to to Data register 13 (8 bytes) DTR13 R/W to
003AEFH 003BEFH 0037EFH 0038EFH XXXXXXXXB
003AF0H 003BF0H 0037F0H 0038F0H XXXXXXXXB
to to to to Data register 14 (8 bytes) DTR14 R/W to
003AF7H 003BF7H 0037F7H 0038F7H XXXXXXXXB
003AF8H 003BF8H 0037F8H 0038F8H XXXXXXXXB
to to to to Data register 15 (8 bytes) DTR15 R/W to
003AFFH 003BFFH 0037FFH 0038FFH XXXXXXXXB
38 DS07-13750-4E
MB90920 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
EI2OS Interrupt vector Interrupt control Priority
Interrupt source register
corresponding Number Address ICR Address *2
Reset × #08 08H FFFFDCH ⎯ ⎯ High
INT9 instruction × #09 09H FFFFD8H ⎯ ⎯
Exception processing × #10 0AH FFFFD4H ⎯ ⎯
CAN0 received/CAN2 received × #11 0BH FFFFD0H
CAN0 transmitted/node status/ × #12 0CH FFFFCCH ICR00 0000B0H*1
CAN2 transmitted/node status
CAN1 received/CAN3 received × #13 0DH FFFFC8H
CAN1 transmitted/node status/ × #14 0EH FFFFC4H ICR01 0000B1H*1
CAN3 transmitted/node status/SIO
Input capture 0 #15 0FH FFFFC0H
DTP/ external interrupt #16 10H FFFFBCH ICR02 0000B2H*1
- ch.0/ch.1 detected
Reload timer 0 #17 11H FFFFB8H ICR03 0000B3H*1
Reload timer 2 #18 12H FFFFB4H
Input capture 1 #19 13H FFFFB0H
DTP/ external interrupt #20 14H FFFFACH ICR04 0000B4H*1
- ch.2/ch.3 detected
Input capture 2 #21 15H FFFFA8H ICR05 0000B5H*1
Reload timer 3 #22 16H FFFFA4H
Input capture 3/4/5/6/7 #23 17H FFFFA0H
DTP/ external interrupt #24 18H FFFF9CH ICR06 0000B6H*1
- ch.4/ ch.5 detected UART3 RX
PPG timer 0 #25 19H FFFF98H
DTP/ external interrupt #26 1AH FFFF94H ICR07 0000B7H*1
- ch.6/ ch.7 detected UART3 TX
PPG timer 1 #27 1BH FFFF90H ICR08 0000B8H*1
Reload timer 1 #28 1CH FFFF8CH
PPG timer 2/3/4/5 #29 1DH FFFF88H
Real time watch timer × #30 1EH FFFF84H ICR09 0000B9H*1
watch timer (sub clock)
Free-run timer overflow/clear × #31 1FH FFFF80H ICR10 0000BAH *1
A/D converter conversion complete #32 20H FFFF7CH
Sound generator 0/1 × #33 21H FFFF78H ICR11 0000BBH*1
Time-base timer × #34 22H FFFF74H
UART2 RX #35 23H FFFF70H ICR12 0000BCH*1
UART2 TX #36 24H FFFF6CH Low
(Continued)
DS07-13750-4E 39
MB90920 Series
(Continued)
EI2OS Interrupt vector Interrupt control Priority
Interrupt source register
corresponding Number Address ICR Address *2
UART 1 RX #37 25H FFFF68H ICR13 0000BDH*1 High
UART 1 TX #38 26H FFFF64H
UART 0 RX #39 27H FFFF60H ICR14 0000BEH*1
UART 0 TX #40 28H FFFF5CH
Flash memory status × #41 29H FFFF58H ICR15 0000BFH*1
Delay interrupt generator module × #42 2AH FFFF54H Low
: Usable, and has expanded intelligent I/O services (EI2OS) stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions that share the ICR register have the same interrupt level.
• If the expanded intelligent I/O service (EI2OS) is used with peripheral functions that share the ICR register,
only one of the peripheral functions that share the register can be used.
• When the expanded intelligent I/O service (EI2OS) is specified for one of the peripheral functions that shares
the ICR register, interrupts cannot be used from the other peripheral functions that share the register.
*2 : Priority applies when interrupts of the same level are generated.
40 DS07-13750-4E
MB90920 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Rating Unit Remarks
Min Max
VCC VSS − 0.3 VSS + 6.0 V
Power supply voltage*1 AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2
AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2
DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2
Input voltage*1 VI VSS − 0.3 VCC + 0.3 V *3
Output voltage*1 VO VSS − 0.3 VCC + 0.3 V
Maximum clamp current ICLAMP −4 +4 mA *7
Total maximum clamp current Σ| ICLAMP | ⎯ 40 mA *7
“L” level maximum IOL1 ⎯ 15 mA Except P70 to P77 and P80 to P87
output current*4 IOL2 ⎯ 40 mA P70 to P77 and P80 to P87
“L” level average output IOLAV1 ⎯ 4 mA Except P70 to P77 and P80 to P87
current*5 IOLAV2 ⎯ 30 mA P70 to P77 and P80 to P87
“L” level maximum ΣIOL1 ⎯ 100 mA Except P70 to P77 and P80 to P87
total output current ΣIOL2 ⎯ 330 mA P70 to P77 and P80 to P87
“L” level average total ΣIOLAV1 ⎯ 50 mA Except P70 to P77 and P80 to P87
output current ΣIOLAV2 ⎯ 250 mA P70 to P77 and P80 to P87
“H” level maximum IOH1*4 ⎯ −15 mA Except P70 to P77 and P80 to P87
output current IOH2*4 ⎯ −40 mA P70 to P77 and P80 to P87
“H” level average IOHAV1*5 ⎯ −4 mA Except P70 to P77 and P80 to P87
output current IOHAV2*5 ⎯ −30 mA P70 to P77 and P80 to P87
“H” level maximum ΣIOH1 ⎯ −100 mA Except P70 to P77 and P80 to P87
total output current ΣIOH2 ⎯ −330 mA P70 to P77 and P80 to P87
“H” level average total ΣIOHAV1*6 ⎯ −50 mA Except P70 to P77 and P80 to P87
output current ΣIOHAV2*6 ⎯ −250 mA P70 to P77 and P80 to P87
Power consumption PD ⎯ 625 mW
Operating temperature TA − 40 + 105 °C
Storage temperature TSTG − 55 + 150 °C
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH must not exceed VCC, and AVRH must not exceed AVCC.
When using an evaluation product, DVCC must not exceed VCC (however, DVCC can be set to a higher voltage
than VCC when using a Flash memory product).
*3 : If the input current or the maximum input current is limited using external components, ICLAMP is the applicable
rating instead of VI.
*4 : Maximum output current is defined as the peak value of current through any one of the corresponding pins.
(Continued)
DS07-13750-4E 41
MB90920 Series
(Continued)
*5 : Average output current is defined as the average value of the current flowing through any one of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “operating factor”.
*6 : Average total output current is defined as the average value of the current flowing through all of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “ operating factor”.
*7 : • Applicable to pins: P10 to P15,P50 to P57,P60 to P67,P70 to P77,P80 to P87,PC0 to PC7,PD0 to PD6,
PE0 to PE2
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the
microcontroller may partially malfunction on power supplied through the +B signal pin.
• Note that if the +B input is applied during power-on, the power supply voltage may reach a level such that
the power-on reset does not function due to the power supplied from the +B signal.
• Care must be taken not to leave +B input pins open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept
+B signal inputs.
• Sample recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
42 DS07-13750-4E
MB90920 Series
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
Parameter Symbol Value Unit Remarks
Min Max
4.0 5.5 V The low voltage detection reset operates when the power
Power supply VCC supply voltage reaches 4.2 V ± 0.2 V.
voltage AVCC Maintain stop operation status
DVCC 4.4 5.5 V The low voltage detection reset operates when the power
supply voltage reaches 4.2 V ± 0.2 V.
Use a ceramic capacitor or other capacitor of equivalent
Smoothing CS 0.1 1.0 μF frequency characteristics. Use a capacitor with a capaci-
capacitor* tance greater than this capacitor as the bypass capacitor for
the VCC pin.
Operating TA − 40 + 105 °C
temperature
* : Refer to the following diagram for details on the connection of the smoothing capacitor CS.
• C pin connection diagram
C
CS VSS DVSS AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13750-4E 43
MB90920 Series
3. DC Characteristics
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin Conditions Value Unit Remarks
name Min Typ Max
Pin inputs if
VIHA ⎯ ⎯ 0.8 VCC ⎯ ⎯ V Automotive input
levels are selected
“H” level Pin inputs if CMOS
input voltage VIHS ⎯ ⎯ 0.8 VCC ⎯ ⎯ V hysteresis input
levels are selected
VIHC ⎯ ⎯ 0.7 VCC ⎯ ⎯ V RST input pin
(CMOS hysteresis)
Pin inputs if
VILA ⎯ ⎯ ⎯ ⎯ 0.5 VCC V Automotive input
levels are selected
“L” level Pin inputs if CMOS
input voltage VILS ⎯ ⎯ ⎯ ⎯ 0.2 VCC V hysteresis input
levels are selected
VILR ⎯ ⎯ ⎯ ⎯ 0.3 VCC V RST input pin
(CMOS hysteresis)
Maximum operating
frequency FCP = 32 MHz, ⎯ 35 45 mA
ICC normal operation
Maximum operating
frequency FCP = 32 MHz, ⎯ 55 65 mA
writing Flash memory
Operating frequency
ICCS FCP = 32 MHz, ⎯ 13 20 mA
sleep mode
Operating frequency
ICTS FCP = 2 MHz, ⎯ 0.6 1.0 mA
time-base timer mode
Power supply VCC Operating frequency
current* ICTSPLL FCP = 32 MHz, ⎯ 2.5 4 mA
PLL timer mode,
External frequency = 4 MHz
Operating frequency
ICCL FCP = 8 kHz, TA = + 25 °C, ⎯ 120 270 μA
sub clock operation
Operating frequency
ICCLS FCP = 8 kHz, TA = + 25 °C, ⎯ 100 200 μA
sub sleep operation
Operating frequency
ICCT FCP = 8 kHz, TA = + 25 °C, ⎯ 90 180 μA
watch mode
ICCH TA = + 25 °C, stop mode ⎯ 80 170 μA
(Continued)
44 DS07-13750-4E
MB90920 Series
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Input leakage VCC = DVCC = AVCC =
current IIL All input pins 5.5 V, ⎯ ⎯ 10 μA
VSS < VI < VCC
All pins except
VCC, VSS,
Input DVCC, DVSS,
capacitance 1 CIN1 AVCC, AVSS, ⎯ ⎯ ⎯ 15 pF
C,
P70 to P77,
P80 to P87
Input capacitance 2 CIN2 P70 to P77, ⎯ ⎯ ⎯ 45 pF
P80 to P87
Pull-up resistance RUP RST ⎯ 25 50 100 kΩ
Excluding
Pull-down RDOWN MD2 ⎯ ⎯ ⎯ 100 kΩ Flash
resistance memory
product
General-purpose All pins except VCC = 4.5 V,
output “H” voltage VOH1 P70 to P77, IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V
P80 to P87
Stepping motor VOH2 P70 to P77, VCC = 4.5 V, VCC − 0.5 ⎯ ⎯ V
output “H” voltage P80 to P87 IOH = −30.0 mA
General-purpose All pins except VCC = 4.5 V,
output “L” voltage VOL1 P70 to P77, IOL = 4.0 mA ⎯ ⎯ 0.4 V
P80 to P87
Stepping motor VOL2 P70 to P77, VCC = 4.5 V, ⎯ ⎯ 0.55 V
output “L” voltage P80 to P87 IOL = 30.0 mA
PWM1Pn, VCC = 4.5 V,
Stepping motor PWM1Mn, IOH = −30.0 mA,
output phase ΔVOH PWM2Pn, maximum deviation ⎯ ⎯ 90 mV
variation “H” PWM2Mn, VOH2
n = 0 to 3
PWM1Pn, VCC = 4.5 V,
Stepping motor PWM1Mn, IOL = 30.0 mA,
output phase ΔVOL PWM2Pn, maximum deviation ⎯ ⎯ 90 mV
variation “L” PWM2Mn, VOH2
n = 0 to 3
Between V0 50 100 200 kΩ Evaluation
and V1, product
LCD internal RLCD Between V1 ⎯ Flash
divider resistance and V2, 8.75 12.5 17.0 kΩ memory
Between V2 product
and V3
(Continued)
DS07-13750-4E 45
MB90920 Series
(Continued)
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
V0 to V3,
LCDC leakage COMm
current ILCDC (m = 0 to 3) , ⎯ ⎯ ⎯ 5.0 μA
SEGn,
(n = 00 to 31)
Rvcom COMn ⎯ ⎯ ⎯ 4.5 kΩ
LCD output (n = 0 to 3)
impedance SEGn ⎯ ⎯ ⎯ 17 kΩ
Rvseg (n = 00 to 31)
* : Power supply current values assume an external clock supplied to the X1 pin and X1A pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
46 DS07-13750-4E
MB90920 Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Condi- Value Unit Remarks
tions Min Typ Max
1/2 (PLL stopped)
3 ⎯ 16 MHz When using the
oscillator circuit
1/2 (PLL stopped)
3 ⎯ 32 MHz When using an external
clock
FC X0, X1 4 ⎯ 32 MHz PLL multiplied by 1
Clock frequency 3 ⎯ 16 MHz PLL multiplied by 2
3 ⎯ 10.7 MHz PLL multiplied by 3
3 ⎯ 8 MHz PLL multiplied by 4
3 ⎯ 5.33 MHz PLL multiplied by 6
3 ⎯ 4 MHz PLL multiplied by 8
FLC X0A, X1A ⎯ 32.768 ⎯ kHz
⎯ 62.5 ⎯ 333 ns When using an
tCYL X0, X1 oscillator
Clock cycle time 31.25 ⎯ 333 ns External clock input
tLCYL X0A, X1A ⎯ 30.5 ⎯ μs
Input clock pulse PWH, PWL X0 5 ⎯ ⎯ ns Use duty ratio of
width 50% ± 3% as a guideline
PWLH, PWLL X0A ⎯ 15.2 ⎯ μs
Input clock tcr, tcf X0 ⎯ ⎯ 5 ns When using an external
rise and fall time clock signal
Internal operating FCP ⎯ 1.5 ⎯ 32 MHz Using main clock
clock frequency (PLL clock)
FLCP ⎯ ⎯ 8.192 ⎯ kHz Using sub clock
Internal operating tCP ⎯ 31.25 — 666 ns Using main clock
clock cycle time (PLL clock)
tLCP ⎯ ⎯ 122.1 ⎯ μs Using sub clock
DS07-13750-4E 47
MB90920 Series
• X0, X1 clock timing
tCYL
X0 0.8 VCC
X1 0.2 VCC
PWH PWL
tcf tcr
• X0A, X1A clock timing
tLCYL
X0A 0.8 VCC
X1A 0.1 VCC
PWLH PWLL
tcf tcr
48 DS07-13750-4E
MB90920 Series
• Guaranteed PLL Operation Range
Internal operating clock frequency vs. Power supply voltage
Power supply voltage VCC (V) 5.5
Range of warranted PLL operation
4.0
Normal operating range
1.5 4 32
Internal clock fCP (MHz)
Notes : • For PLL 1 × only, use with tcp = 4 MHz or greater.
• Refer to “5. A/D Converter (1) Electrical Characteristics” for details on the A/D converter operating
frequency.
(Continued)
DS07-13750-4E 49
MB90920 Series
(Continued)
Base oscillator frequency vs. Internal operating clock frequency
32
Internal clock fCP (MHz) x 8*3
25 x 3*1
24 x 6*3 No multiplier
20 x 2*1,*2 x 1*1
18
16 x4
*1,*2
12
9
8
6
4
1.5
3456 8 10 12.5 16 20 25 32
Base oscillator clock FCP (MHz)
*1 : When the PLL multiplier is × 1, × 2, × 3 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, set
DIV2 bit = “1”*4, CS2 bit = “1” in the PSCCR register.
[Example] When using a base oscillator frequency of 24 MHz at PLL × 1 :
CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4,CS2 bit = “1”
[Example] When using a base oscillator frequency of 6 MHz at PLL × 3 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4, CS2 bit = “1”
*2 : When the PLL multiplier is × 2 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, the following
settings are also supported.
PLL × 2 : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4, CS2 bit = “0”
PLL × 4 : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4, CS2 bit = “0”
*3 : When the PLL multiplier is set to × 6 or × 8 set “DIV2 bit = “0”*4 CS2 bit = “1”
and “PLL2 bit = 1” in the PSCCR register.
[Example] When using a base oscillator frequency of 4 MHz at PLL × 6 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PLLOS register : DIV2 bit = “0”*4, CS2 bit = “1”
[Example] When using a base oscillator frequency of 3 MHz at PLL × 8 :
CKSCR register : CS1 bit = “1”, CS0 bit = “1”
PLLOS register : DIV2 bit = “0”*4, CS2 bit = “1”
*4 : The DIV2 bit is assigned to bit 9 of the PSCCR register and the CS2 bit is assigned to bit 8 of the PSCCR
register. Both bits have a default value of “0”.
50 DS07-13750-4E
MB90920 Series
(2) Reset input
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin name Value Unit Remarks
Min Max
500 ⎯ ns During normal
operation
In stop mode,
Reset input time tRSTL RST Oscillator oscillation time* + 16 tCP ⎯ ms sub clock mode,
sub sleep mode,
and watch mode
100 ⎯ μs In time-base timer
mode
*: The oscillation time of the oscillator is the time taken to reach 90% of the amplitude. The oscillation time of a
crystal oscillator is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between
hundreds of μs and several ms. The oscillation time of an external clock is 0 ms.
Note : tCP is the internal operating clock cycle time. (Unit : ns)
• During normal operation
tRSTL
RST
0.2 VCC 0.2 VCC
• In stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 Vcc 0.2 Vcc
90 % of
X0 amplitude
Internal
operating Oscillator
clock oscillation time 16 tCP
Oscillation stabilization wait time
Execution of the instructions
Internal
reset
DS07-13750-4E 51
MB90920 Series
(3) Power-on reset
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Pin Conditions Value Unit Remarks
Symbol name
Min Max
Power supply rise time tR 0.05 30 ms
Power off time tOFF VCC ⎯ 1 ⎯ ms Waiting time until
power-on
tR
VCC 2.7 V
0.2 V 0.2 V 0.2 V
tOFF
Note : Extreme variations in power supply voltage may trigger a power-on reset. When the power
supply voltage is changed during operation, it is recommended that increases in the voltage
smoothed out as shown in the following diagram. The PLL clock of the device should not be
in use when varying the voltage. However, the PLL clock may continue to be used if the rate
of the voltage drop is 1 V/s or less.
5.0 V VCC
It is recommended that rises
in voltage have a slope of
RAM data hold 50 mV/ms or less
0V VSS
52 DS07-13750-4E
MB90920 Series
(4) UART0/1/2/3 (LIN/SCI)
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin name Value Unit
Conditions
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3 5 tCP ⎯ ns
SCK ↓ → SOT delay time tSLOVI SCK0 to SCK3, Internal shift clock − 50 + 50 ns
SOT0 to SOT3 mode output pin
Valid SIN → SCK ↑ tIVSHI SCK0 to SCK3, CL = 80 pF + 1TTL tCP + 80 ⎯ ns
SCK ↑ → valid SIN hold time tSHIXI SIN0 to SIN3 0 ⎯ ns
Serial clock “L” pulse width tSLSH SCK0 to SCK3 3 tCP − tR ⎯ ns
Serial clock “H” pulse width tSHSL tCP + 10 ⎯ ns
SCK ↓ → SOT delay time tSLOVE SCK0 to SCK3, ⎯ 2 tCP + 60 ns
SOT0 to SOT3 External shift clock
Valid SIN → SCK ↑ tIVSHE SCK0 to SCK3, mode output pin 30 ⎯ ns
SIN0 to SIN3 CL = 80 pF + 1TTL
SCK ↑ → valid SIN hold time tSHIXE tCP + 30 ⎯ ns
SCK ↓ time tF SCK0 to SCK3 ⎯ 10 ns
SCK ↑ time tR ⎯ 10 ns
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13750-4E 53
MB90920 Series
• Internal shift clock mode
SCK tSCYC
2.4 V
0.8 V 0.8 V
tSLOVI
2.4 V
SOT 0.8 V
tIVSHI tSHIXI
VIH VIH
SIN VIL VIL
• External shift clock mode
SCK tSLSH tSHSL
VIH VIH
VIL VIL
tF tSLOVE tR
2.4 V
SOT 0.8 V
tIVSHE tSHIXE
VIH VIH
SIN VIL VIL
54 DS07-13750-4E
MB90920 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter Symbol Pin name Value Unit
Conditions
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3 5 tCP ⎯ ns
SCK ↑ → SOT delay time tSHOVI SCK0 to SCK3, Internal shift clock − 50 + 50 ns
SOT0 to SOT3 mode output pin
Valid SIN → SCK ↓ tIVSLI SCK0 to SCK3, CL = 80 pF + 1TTL tCP + 80 ⎯ ns
SCK ↓ → valid SIN hold time tSLIXI SIN0 to SIN3 0 ⎯ ns
Serial clock “H” pulse width tSHSL SCK0 to SCK3 3 tCP − tR ⎯ ns
Serial clock “L” pulse width tSLSH tCP + 10 ⎯ ns
SCK ↑ → SOT delay time tSHOVE SCK0 to SCK3, ⎯ 2 tCP + 60 ns
SOT0 to SOT3 External shift clock
Valid SIN → SCK ↓ tIVSLE SCK0 to SCK3, mode output pin 30 ⎯ ns
SIN0 to SIN3 CL = 80 pF + 1TTL
SCK ↓ → valid SIN hold time tSLIXE tCP + 30 ⎯ ns
SCK ↓ time tF SCK0 to SCK3 ⎯ 10 ns
SCK ↑ time tR ⎯ 10 ns
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13750-4E 55
MB90920 Series
• Internal shift clock mode
SCK tSCYC
2.4 V 2.4 V
0.8 V
tSHOVI
2.4 V
SOT 0.8 V
tIVSLI tSLIXI
VIH VIH
SIN VIL VIL
• External shift clock mode
SCK tSHSL tSLSH
VIH VIH
VIL VIL
tR tSHOVE tF
2.4 V
SOT 0.8 V
tIVSLE tSLIXE
VIH VIH
SIN VIL VIL
56 DS07-13750-4E
MB90920 Series
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Value Unit
Conditions
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3 5 tCP ⎯ ns
SCK ↑ → SOT delay time tSHOVI SCK0 to SCK3, − 50 + 50 ns
SOT0 to SOT3 Internal shift clock
Valid SIN → SCK ↓ tIVSLI SCK0 to SCK3, mode output pin tCP + 80 ⎯ ns
SCK ↓ → valid SIN hold time tSLIXI SIN0 to SIN3 CL = 80 pF + 1TTL 0 ⎯ ns
SOT → SCK ↓ delay time tSOVLI SCK0 to SCK3, 3 tCP − 70 ⎯ ns
SOT0 to SOT3
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
SCK tSCYC
2.4 V
0.8 V 0.8 V
tSOVLI tSHOVI
2.4 V 2.4 V
SOT 0.8 V 0.8 V
tIVSLI tSLIXI
VIH VIH
SIN VIL VIL
DS07-13750-4E 57
MB90920 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Value Unit
Conditions
Min Max
Serial clock cycle time tSCYC SCK0 to SCK3 5 tCP ⎯ ns
SCK ↓ → SOT delay time tSLOVI SCK0 to SCK3, − 50 + 50 ns
SOT0 to SOT3 Internal shift clock
Valid SIN → SCK ↓ tIVSHI SCK0 to SCK3, mode output pin tCP + 80 ⎯ ns
SCK ↑ → valid SIN hold time tSHIXI SIN0 to SIN3 CL = 80 pF + 1TTL 0 ⎯ ns
SOT → SCK ↑ delay time tSOVHI SCK0 to SCK3, 3 tCP − 70 ⎯ ns
SOT0 to SOT3
Notes : • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by
some parameters. These parameters are shown in “MB90920 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
SCK tSCYC
2.4 V 2.4 V
0.8 V
tSOVHI tSLOVI
2.4 V 2.4 V
SOT 0.8 V 0.8 V
tIVSHI tSHIXI
VIH VIH
SIN VIL VIL
58 DS07-13750-4E
MB90920 Series
(5) Timer input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit
Min Max
Input pulse width tTIWH TIN0, TIN1, ⎯ 4 tCP ⎯ ns
tTIWL IN0 to IN3
Note : tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Timer input timing
tTIWH tTIWL
TIN0, TIN1 VIH VIH
IN0 to IN3 VIL VIL
DS07-13750-4E 59
MB90920 Series
(6) Trigger input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Max
tTRGH, INT0 to INT7 ⎯ 200 ⎯ ns During normal
Input pulse width tTRGL operation
ADTG ⎯ tCP + 200 ⎯ ns
Note : tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Trigger input timing
tTRGH tTRGL
INT0 to INT7 VIH VIH
ADTG VIL VIL
60 DS07-13750-4E
MB90920 Series
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Pin name Value Unit Remarks
Symbol Conditions
Min Typ Max
Flash memory
4.0 4.2 4.4 V product, during
Detection voltage VDL VCC ⎯ voltage drop
3.7 4.0 4.3 V Evaluation product,
during voltage drop
Flash memory
190 ⎯ ⎯ mV product, during
Hysteresis width VHYS VCC ⎯ voltage rise
0.1 ⎯ ⎯ V Evaluation product,
during voltage rise
Flash memory
− 0.1 ⎯ + 0.1 V/μs product, dV/dt at low
voltage reset
Flash memory
Power supply voltage dV/dt VCC ⎯ product, dV/dt at
change rate −0.004 ⎯ + 0.004 V/μs standard value of
low voltage
detection/release
voltage
− 0.1 ⎯ + 0.02 V/μs Evaluation product
Flash memory
Detection delay time td ⎯ ⎯ ⎯ ⎯ 3.2 μs product, when
dV/dt ≤ 0.004 V/μs
⎯ ⎯ 35 μs Evaluation product
Internal reset
VCC
dV
dt VHYS
td td
DS07-13750-4E 61
MB90920 Series
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = AVRH = 4.0 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution ⎯ ⎯ ⎯ ⎯ 10 bit
Total error ⎯ ⎯ − 3.0 ⎯ + 3.0 LSB
Non-linear error ⎯ ⎯ − 2.5 ⎯ + 2.5 LSB
Differential linear error ⎯ ⎯ − 1.9 ⎯ + 1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVSS − AVSS + AVSS + V 1 LSB =
1.5 LSB 0.5 LSB 2.5 LSB (AVRH − AVSS) /
Full scale transition VFST AN0 to AN7 AVRH − AVRH − AVRH + V 1024
voltage 3.5 LSB 1.5 LSB 0.5 LSB
Sampling time tSMP ⎯ 0.4 ⎯ 16500 μs 4.5 V ≤ AVcc ≤ 5.5 V
1.0 4.0 V ≤ AVcc ≤ 4.5 V
Compare time tCMP ⎯ 0.66 ⎯ ⎯ μs 4.5 V ≤ AVcc ≤ 5.5 V
2.2 4.0 V ≤ AVcc ≤ 4.5 V
A/D conversion time tCNV ⎯ 1.44 ⎯ ⎯ μs *1
Analog port IAIN AN0 to AN7 − 0.3 ⎯ + 10 μA
input current
Analog input voltage VAIN AN0 to AN7 0 ⎯ AVRH V
Reference voltage AV+ AVRH AVss + ⎯ AVCC V
2.7
Power supply current IA AVCC ⎯ 2.3 6.0 mA
IAH ⎯ ⎯ 5 μA *2
Reference voltage IR AVRH ⎯ 520 900 μA VAVRH = 5.0 V
supply current IRH ⎯ ⎯ 5 μA *2
Inter-channel variation — AN0 to AN7 ⎯ ⎯ 4 LSB
*1 : The time per channel (4.5 V ≤ AVCC ≤ 5.5 V, and internal operating frequency = 32 MHz) .
*2 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
62 DS07-13750-4E
MB90920 Series
• Notes on the external impedance and sampling time of analog inputs
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
If the sampling time is still not sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input Comparator
C
During sampling : ON
MB90F922NC/F922NCS/ F923NC/F923NCS/F924NC/F924NCS
MB90922NCS
R C
4.5 V ≤ AVcc ≤ 5.5 V : 2.6 kΩ (Max) 8.5 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 12.1 kΩ (Max) 8.5 pF (Max)
MB90V920-101/102
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 14.4 pF (Max)
Note : The values are reference values.
DS07-13750-4E 63
MB90920 Series
• The relationship between the external impedance and minimum sampling time
• At 4.5 V ≤ AVcc ≤ 5.5 V
(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)
100 MB90V920-101/102 MB90V920-101/102
20
External impedance [kΩ] 90 MB90F922NC/F922NCS/922NCS/ External impedance [kΩ] 18 MB90F922NC/F922NCS/922NCS/
80 MB90F923NC/F923NCS/ 16 MB90F923NC/F923NCS/
MB90F924NC/F924NCS MB90F924NC/F924NCS
70 14
60 12
50 10
40 8
30 6
20 4
10 2
0 0
0 5 10 15 20 25 30 35 0 1 2 3 4 5 6 7 8
Minimum sampling time [μs] Minimum sampling time [μs]
• At 4.0 V ≤ AVcc ≤ 4.5 V
(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)
100 MB90V920-101/102 20 MB90V920-101/102
External impedance [kΩ] 90 MB90F922NC/F922NCS/922NCS/ External impedance [kΩ] 18 MB90F922NC/F922NCS/922NCS/
80 MB90F923NC/F923NCS/ 16 MB90F923NC/F923NCS/
MB90F924NC/F924NCS 14 MB90F924NC/F924NCS
70
60 12
50 10
40 8
30 6
20 4
10 2
0 0
0 5 10 15 20 25 30 35 0 1 2 3 4 5 6 7 8
Minimum sampling time [μs] Minimum sampling time [μs]
• About errors
As |AVRH - AVSS| becomes smaller, the relative errors grow larger.
64 DS07-13750-4E
MB90920 Series
(2) Definition of terms
Resolution : Analog changes that are identifiable by the A/D converter.
Non-Linear error : The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ←→ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ←→ “11 1111 1111”) from actual conversion characteristics.
Differential linear : The deviation from the ideal value of the input voltage needed to change the output code by
error 1 LSB.
Total error : The total error is the difference between the actual value and the theoretical value,
and includes zero-transition error/full-scale transition error and linear error.
Total error
3FFH
3FEH Actual conversion
3FDH value
1.5 LSB
Digital output {1 LSB x (N - 1) + 0.5 LSB}
004H VNT
003H Actual conversion (Measured value)
002H value
Ideal
001H characteristics
0.5 LSB
AVSS AVRH
Analog input
Total error for digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB]
1 LSB
1 LSB (Ideal) = AVRH − AVSS [V]
1024
N : A/D converter digital output value
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage when the digital output changes from (N - 1) to N
(Continued)
DS07-13750-4E 65
MB90920 Series
(Continued)
Non-Linear error Differential linear error
Ideal
3FFH Actual conversion characteristics
3FEH value (N + 1) Actual conversion
3FDH {1 LSB x (N -1) value
+ VOT} VFST
Digital output (Measured Digital output
value) N
V(N + 1)T
004H VNT (N - 1) (Measured
(Measured value) value)
003H Actual conversion VNT
002H value (Measured value)
Ideal (N - 2) Actual conversion
001H characteristics value
VOT (Measured value)
AVss AVRH AVss AVRH
Analog input Analog input
Non-linear error of = VNT − {1 LSB × (N − 1) + VOT} [LSB]
digital output N 1 LSB
Differential linear error = V (N + 1) T − VNT − 1 [LSB]
of digital output N 1 LSB
1 LSB = VFST − VOT [V]
1022
N : A/D converter digital output value
VOT : Voltage when digital output changes from 000H to 001H
VFST : Voltage when digital output changes from 3FEH to 3FFH
66 DS07-13750-4E
MB90920 Series
6. Flash Memory Program/Erase Characteristics
Parameter Value Unit Remarks
Conditions
Min Typ Max
Sector erase time ⎯ 0.9 3.6 s Excludes pre-programming before
TA = + 25 °C erase
Word (16-bit width) VCC = 5.0 V ⎯ 23 370 μs Excludes system-level overhead
programming time
Chip programming TA = + 25 °C, ⎯ 3.4 55 s
time VCC = 5.0 V
Erase/program cycle ⎯ 10000 ⎯ ⎯ cycle
Flash memory data Average 20 ⎯ ⎯ year *
retention time TA = + 85 °C
* : This value is calculated from the results of evaluating the reliability of the technology (using Arrhenius equation
to translate high temperature measurements into normalized value at + 85 °C) .
DS07-13750-4E 67
MB90920 Series
■ ORDERING INFORMATION
Part number Package Remarks
MB90F922NCPMC
MB90F922NCSPMC
MB90922NCSPMC 120-pin plastic LQFP
MB90F923NCPMC (FPT-120P-M21)
MB90F923NCSPMC
MB90F924NCPMC
MB90F924NCSPMC
MB90V920-101CR 299-pin ceramic PGA For evaluation
MB90V920-102CR (PGA-299C-A01)
68 DS07-13750-4E
MB90920 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP Lead pitch 0.50 mm
Package width × 16.0 × 16.0 mm
package length
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.70 mm MAX
Weight 0.88 g
(FPT-120P-M21) Code P-LFQFP120-16×16-0.50
(Reference)
120-pin plastic LQFP Note 1) * : These dimensions do not include resin protrusion.
(FPT-120P-M21) Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
* 16.00 +0.40 .630 +.016 SQ
–0.10 –.004
90 61
91 60
0.08(.003) Details of "A" part
1.50 +0.20
–0.10 (Mounting height)
.059 +.008
–.004
INDEX
0~8°
120 31 "A"
0.10±0.05
LEAD No. 1 30 (.004±.002)
0.22±0.05 0.145 +0.05 0.60±0.15 (Stand off)
0.50(.020) 0.08(.003) M –0.03
(.009±.002) .006 +.002 (.024±.006)
–.001 0.25(.010)
Dimensions in mm (inches).
C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F120033S-c-4-7 Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13750-4E 69
MB90920 Series
■ MAJOR CHANGES IN THIS EDITION
Page Section Change Results
12 ■I/O CIRCUIT TYPE Corrected the circuit type B.
■ HANDLING DEVICES Added the following items;
20 • Serial communication
• Characteristic difference between flash device and
MASK ROM device
31 ■ I/O MAP Corrected “Address: 003970H”.
Clock supervisor control register → (Disabled)
46 ■ ELECTRICAL CHARACTERISTICS Added the item for “LCD output impedance”.
3. DC Characteristics
■ ORDERING INFORMATION Corrected the part numbers;
68 MB90V920-101 → MB90V920-101CR
MB90V920-102 → MB90V920-102CR
The vertical lines marked in the left side of the page show the changes.
70 DS07-13750-4E
MB90920 Series
MEMO
DS07-13750-4E 71
MB90920 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC. FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
1250 E. Arques Avenue, M/S 333 151 Lorong Chuan,
Sunnyvale, CA 94085-5401, U.S.A. #05-08 New Tech Park 556741 Singapore
Tel: +1-408-737-5600 Fax: +1-408-737-5999 Tel : +65-6281-0770 Fax : +65-6281-0220
http://us.fujitsu.com/micro/ http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
FUJITSU SEMICONDUCTOR EUROPE GmbH Rm. 3102, Bund Center, No.222 Yan An Road (E),
Pittlerstrasse 47, 63225 Langen, Germany Shanghai 200002, China
Tel: +49-6103-690-0 Fax: +49-6103-690-122 Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://emea.fujitsu.com/semiconductor/ http://cn.fujitsu.com/fss/
Korea FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
FUJITSU SEMICONDUCTOR KOREA LTD. 10/F., World Commerce Centre, 11 Canton Road,
206 Kosmo Tower Building, 1002 Daechi-Dong, Tsimshatsui, Kowloon, Hong Kong
Gangnam-Gu, Seoul 135-280, Republic of Korea Tel : +852-2377-0226 Fax : +852-2376-3269
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://cn.fujitsu.com/fsp/
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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MB90922NCSPMC-GS-266E1 MB90922NCSPMC-GS-264E1 MB90922NCSPMC-GS-234E1 MB90922NCSPMC-
GS-128E1 MB90922NCSPMC-GS-231E1 MB90922NCSPMC-GS-204E1 MB90922NCSPMC-GS-147E1
MB90922NCSPMC-GS-192E1 MB90922NCSPMC-GS-224E1 MB90922NCSPMC-GS-249E1 MB90922NCSPMC-GS-
213E1 MB90922NCSPMC-GS-137E1 MB90922NCSPMC-GS-258E1 MB90922NCSPMC-GS-159E1
MB90922NCSPMC-GS-114E1 MB90922NCSPMC-GS-256E1 MB90922NCSPMC-GS-171E1 MB90922NCSPMC-GS-
136E1 MB90922NCSPMC-GS-161E1 MB90922NCSPMC-GS-222E1 MB90922NCSPMC-GS-259E1
MB90922NCSPMC-GS-187E1 MB90922NCSPMC-GS-206E1 MB90922NCSPMC-GS-132E1 MB90922NCSPMC-GS-
167E1 MB90922NCSPMC-GS-207E1 MB90922NCSPMC-GS-143E1 MB90922NCSPMC-GS-154E1
MB90922NCSPMC-GS-208E1 MB90922NCSPMC-GS-235E1 MB90922NCSPMC-GS-135E1 MB90922NCSPMC-GS-
225E1 MB90922NCSPMC-GS-257E1 MB90922NCSPMC-GS-164E1 MB90922NCSPMC-GS-214E1
MB90922NCSPMC-GS-178E1 MB90922NCSPMC-GS-190E1 MB90922NCSPMC-GS-160E1 MB90922NCSPMC-GS-
138E1 MB90922NCSPMC-GS-262E1 MB90922NCSPMC-GS-173E1 MB90922NCSPMC-GS-201E1
MB90922NCSPMC-GS-184E1 MB90922NCSPMC-GS-223E1 MB90922NCSPMC-GS-248E1 MB90922NCSPMC-GS-
148E1 MB90922NCSPMC-GS-134E1 MB90922NCSPMC-GS-177E1 MB90922NCSPMC-GS-183E1
MB90922NCSPMC-GS-181E1 MB90922NCSPMC-GS-261E1 MB90922NCSPMC-GS-211E1 MB90922NCSPMC-GS-
122E1 MB90922NCSPMC-GS-180E1 MB90922NCSPMC-GS-151E1 MB90922NCSPMC-GS-115E1
MB90922NCSPMC-GS-238E1 MB90922NCSPMC-GS-189E1 MB90922NCSPMC-GS-233E1 MB90922NCSPMC-GS-
152E1 MB90922NCSPMC-GS-199E1 MB90922NCSPMC-GS-150E1 MB90922NCSPMC-GS-125E1
MB90922NCSPMC-GS-252E1 MB90922NCSPMC-GS-188E1 MB90922NCSPMC-GS-144E1 MB90922NCSPMC-GS-
127E1 MB90922NCSPMC-GS-162E1 MB90922NCSPMC-GS-193E1 MB90922NCSPMC-GS-246E1
MB90922NCSPMC-GS-230E1 MB90922NCSPMC-GS-202E1 MB90922NCSPMC-GS-244E1 MB90922NCSPMC-GS-
140E1 MB90922NCSPMC-GS-176E1 MB90922NCSPMC-GS-172E1 MB90922NCSPMC-GS-209E1
MB90922NCSPMC-GS-221E1 MB90922NCSPMC-GS-205E1 MB90922NCSPMC-GS-163E1 MB90922NCSPMC-GS-
191E1 MB90922NCSPMC-GS-218E1 MB90922NCSPMC-GS-271E1 MB90922NCSPMC-GS-166E1
MB90922NCSPMC-GS-240E1 MB90922NCSPMC-GS-220E1 MB90922NCSPMC-GS-139E1 MB90922NCSPMC-GS-
170E1 MB90922NCSPMC-GS-157E1 MB90922NCSPMC-GS-117E1 MB90922NCSPMC-GS-129E1
MB90922NCSPMC-G-003E1 MB90922NCSPMC-GS-212E1 MB90922NCPMC-GS-165E1 MB90922NCSPMC-GS-
126E1 MB90922NCSPMC-GS-186E1 MB90922NCSPMC-GS-153E1 MB90922NCSPMC-GS-131E1
MB90922NCSPMC-GS-197E1 MB90922NCSPMC-GS-263E1
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